library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
use work.textmode_vga_component_pkg.all;
use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;

entity display is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;
		-- History
		d_new_eingabe : in std_logic;
		d_new_result : in std_logic;
		d_zeile : out hzeile;
		d_spalte : out hspalte;
		d_get : out std_logic;
		d_done : in std_logic;
		d_char : in hbyte;
		-- VGA
		command : out std_logic_vector(7 downto 0);
		command_data : out std_logic_vector(31 downto 0);
		free : in std_logic
	);
end entity display;

architecture beh of display is
	type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT);
	signal state_int, state_next : DISPLAY_STATE;
	signal d_zeile_int, d_zeile_next : hzeile;
	signal d_spalte_int, d_spalte_next : hspalte;
	signal d_get_int, d_get_next : std_logic;
	signal command_int, command_next : std_logic_vector(7 downto 0);
	signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
begin
	d_zeile <= d_zeile_int;
	d_spalte <= d_spalte_int;
	d_get <= d_get_int;
	command <= command_int;
	command_data <= command_data_int;

	process(sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			-- internal
			state_int <= SIDLE;
			-- out
			d_zeile_int <= (others => '0');
			d_spalte_int <= (others => '0');
			d_get_int <= '0';
			command_int <= COMMAND_NOP;
			command_data_int <= (others => '0');
		elsif rising_edge(sys_clk) then
			-- internal
			state_int <= state_next;
			-- out
			d_zeile_int <= d_zeile_next;
			d_spalte_int <= d_spalte_next;
			d_get_int <= d_get_next;
			command_int <= command_next;
			command_data_int <= command_data_next;
		end if;
	end process;

	-- next state
	process(state_int, d_new_result, d_new_eingabe, d_done, free)
	begin
		state_next <= state_int;

		case state_int is
			when SIDLE =>
				if free = '1' then
					if d_new_eingabe = '1' then
						state_next <= S_NEW_INPUT;
					end if;
					if d_new_result = '1' then
						state_next <= S_NEW_RESULT;
					end if;
				end if;
			when S_NEW_RESULT | S_NEW_INPUT =>
				if free = '0' then
					state_next <= SIDLE;
				end if;
		end case;
	end process;

	-- out
	process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
		command_data_int)
	begin
		d_zeile_next <= d_zeile_int;
		d_spalte_next <= d_spalte_int;
		d_get_next <= d_get_int;
		command_next <= command_int;
		command_data_next <= command_data_int;

		case state_int is
			when SIDLE | S_NEW_INPUT | S_NEW_RESULT =>
				null;
		end case;
	end process;
end architecture beh;