-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

-- DATE "03/30/2009 19:53:36"

-- 
-- Device: Altera EP2C35F484C6 Package FBGA484
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	demo_top IS
    PORT (
	LEDS : OUT std_logic_vector(7 DOWNTO 0);
	CLK : IN std_logic;
	RESET : IN std_logic
	);
END demo_top;

ARCHITECTURE structure OF demo_top IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_LEDS : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_CLK : std_logic;
SIGNAL ww_RESET : std_logic;
SIGNAL \inst1|altpll_component|pll_INCLK_bus\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \inst1|altpll_component|pll_CLK_bus\ : std_logic_vector(2 DOWNTO 0);
SIGNAL \inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst1|altpll_component|pll~CLK1\ : std_logic;
SIGNAL \inst1|altpll_component|pll~CLK2\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\ : std_logic;
SIGNAL \inst|ledstate_next~434\ : std_logic;
SIGNAL \inst|ledstate_next~435\ : std_logic;
SIGNAL \CLK~combout\ : std_logic;
SIGNAL \inst1|altpll_component|_clk0\ : std_logic;
SIGNAL \inst1|altpll_component|_clk0~clkctrl\ : std_logic;
SIGNAL \inst|Add0~101\ : std_logic;
SIGNAL \inst|Add0~103\ : std_logic;
SIGNAL \inst|Add0~105\ : std_logic;
SIGNAL \inst|Add0~107\ : std_logic;
SIGNAL \inst|Add0~108\ : std_logic;
SIGNAL \inst|Add0~104\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\ : std_logic;
SIGNAL \inst|Add0~96\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ : std_logic;
SIGNAL \inst|Add0~106\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\ : std_logic;
SIGNAL \RESET~combout\ : std_logic;
SIGNAL \inst|Add0~97\ : std_logic;
SIGNAL \inst|Add0~98\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\ : std_logic;
SIGNAL \inst|Add0~99\ : std_logic;
SIGNAL \inst|Add0~100\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\ : std_logic;
SIGNAL \inst|Add0~102\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\ : std_logic;
SIGNAL \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\ : std_logic;
SIGNAL \inst|Equal1~58\ : std_logic;
SIGNAL \inst|Equal1~59\ : std_logic;
SIGNAL \inst|knightlight~1269\ : std_logic;
SIGNAL \inst|knightlight~1270\ : std_logic;
SIGNAL \inst|knightlight~1271\ : std_logic;
SIGNAL \inst|knightlight~1272\ : std_logic;
SIGNAL \inst|knightlight~1273\ : std_logic;
SIGNAL \inst|knightlight~1274\ : std_logic;
SIGNAL \inst|knightlight~1277\ : std_logic;
SIGNAL \inst|knightlight~1275\ : std_logic;
SIGNAL \inst|knightlight~1276\ : std_logic;
SIGNAL \inst|ledstate_next~431\ : std_logic;
SIGNAL \inst|ledstate_next~432\ : std_logic;
SIGNAL \inst|ledstate_next~433\ : std_logic;
SIGNAL \inst|ledstate_next~436\ : std_logic;
SIGNAL \inst|ledstate\ : std_logic;
SIGNAL \inst|knightlight~1267\ : std_logic;
SIGNAL \inst|knightlight~1268\ : std_logic;
SIGNAL \inst|knightlight~1265\ : std_logic;
SIGNAL \inst|knightlight~1266\ : std_logic;
SIGNAL \inst|knightlight~1264\ : std_logic;
SIGNAL \inst|knightlight\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst|counter\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \inst|ALT_INV_knightlight\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \ALT_INV_RESET~combout\ : std_logic;

BEGIN

LEDS <= ww_LEDS;
ww_CLK <= CLK;
ww_RESET <= RESET;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\inst1|altpll_component|pll_INCLK_bus\ <= (gnd & \CLK~combout\);

\inst1|altpll_component|_clk0\ <= \inst1|altpll_component|pll_CLK_bus\(0);
\inst1|altpll_component|pll~CLK1\ <= \inst1|altpll_component|pll_CLK_bus\(1);
\inst1|altpll_component|pll~CLK2\ <= \inst1|altpll_component|pll_CLK_bus\(2);

\inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \inst1|altpll_component|_clk0\);
\inst|ALT_INV_knightlight\(7) <= NOT \inst|knightlight\(7);
\inst|ALT_INV_knightlight\(6) <= NOT \inst|knightlight\(6);
\inst|ALT_INV_knightlight\(5) <= NOT \inst|knightlight\(5);
\inst|ALT_INV_knightlight\(4) <= NOT \inst|knightlight\(4);
\inst|ALT_INV_knightlight\(3) <= NOT \inst|knightlight\(3);
\inst|ALT_INV_knightlight\(2) <= NOT \inst|knightlight\(2);
\inst|ALT_INV_knightlight\(1) <= NOT \inst|knightlight\(1);
\inst|ALT_INV_knightlight\(0) <= NOT \inst|knightlight\(0);
\ALT_INV_RESET~combout\ <= NOT \RESET~combout\;

\inst|counter[3]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|counter\(3));

\inst|counter[6]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|counter\(6));

\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ = \inst|Add0~104\ & (GND # !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\) # !\inst|Add0~104\ & 
-- (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ $ GND)
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ = CARRY(\inst|Add0~104\ # !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst|Add0~104\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\);

\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ = \inst|Add0~106\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ # !\inst|Add0~106\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ # 
-- GND)
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\ # !\inst|Add0~106\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Add0~106\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~21\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\);

\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\ = \inst|Add0~108\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ $ GND) # !\inst|Add0~108\ & 
-- !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\ & VCC
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\ = CARRY(\inst|Add0~108\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst|Add0~108\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~23\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\);

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ # 
-- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ & 
-- !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ & 
-- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000100000001",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\,
	datab => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\);

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ # 
-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & ((\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ # 
-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\))
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ # 
-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000100001110",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\,
	datab => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\);

\inst|Mod0|auto_generated|divider|divider|StageOut[54]~25_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ = !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~24\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\);

\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[5]~22\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\);

\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[4]~20\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\);

\inst|Mod0|auto_generated|divider|divider|StageOut[50]~21_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\ = \inst|Add0~100\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|Add0~100\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\);

\inst|Mod0|auto_generated|divider|divider|StageOut[49]~22_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ = \inst|Add0~98\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Add0~98\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\);

\inst|Mod0|auto_generated|divider|divider|StageOut[59]~638_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ # \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\) 
-- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\,
	datab => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~21\,
	datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~22\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[59]~638\);

\inst|Mod0|auto_generated|divider|divider|StageOut[62]~641_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\ # \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\) 
-- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~26\,
	datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~28\,
	datac => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[62]~641\);

\inst|ledstate_next~434_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|ledstate_next~434\ = \inst|knightlight\(3) $ \inst|Equal1~59\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|knightlight\(3),
	datad => \inst|Equal1~59\,
	combout => \inst|ledstate_next~434\);

\inst|ledstate_next~435_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|ledstate_next~435\ = \inst|knightlight\(4) & (\inst|ledstate\ # \inst|ledstate_next~434\) # !\inst|knightlight\(4) & (\inst|ledstate_next~434\ & \inst|ledstate\ # !\inst|ledstate_next~434\ & (\inst|knightlight\(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110101111101000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ledstate\,
	datab => \inst|knightlight\(4),
	datac => \inst|ledstate_next~434\,
	datad => \inst|knightlight\(7),
	combout => \inst|ledstate_next~435\);

\CLK~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_CLK,
	combout => \CLK~combout\);

\inst1|altpll_component|pll\ : cycloneii_pll
-- pragma translate_off
GENERIC MAP (
	bandwidth => 0,
	bandwidth_type => "auto",
	c0_high => 4,
	c0_initial => 1,
	c0_low => 4,
	c0_mode => "even",
	c0_ph => 0,
	c1_mode => "bypass",
	c1_ph => 0,
	c2_mode => "bypass",
	c2_ph => 0,
	charge_pump_current => 80,
	clk0_counter => "c0",
	clk0_divide_by => 1,
	clk0_duty_cycle => 50,
	clk0_multiply_by => 4,
	clk0_phase_shift => "0",
	clk1_duty_cycle => 50,
	clk1_phase_shift => "0",
	clk2_duty_cycle => 50,
	clk2_phase_shift => "0",
	compensate_clock => "clk0",
	gate_lock_counter => 0,
	gate_lock_signal => "no",
	inclk0_input_frequency => 40000,
	inclk1_input_frequency => 40000,
	invalid_lock_multiplier => 5,
	loop_filter_c => 3,
	loop_filter_r => " 2.500000",
	m => 32,
	m_initial => 1,
	m_ph => 0,
	n => 1,
	operation_mode => "normal",
	pfd_max => 100000,
	pfd_min => 2484,
	pll_compensation_delay => 5370,
	self_reset_on_gated_loss_lock => "off",
	simulation_type => "timing",
	valid_lock_multiplier => 1,
	vco_center => 1333,
	vco_max => 2000,
	vco_min => 1000)
-- pragma translate_on
PORT MAP (
	inclk => \inst1|altpll_component|pll_INCLK_bus\,
	clk => \inst1|altpll_component|pll_CLK_bus\);

\inst1|altpll_component|_clk0~clkctrl_I\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \inst1|altpll_component|_clk0~clkctrl_I_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst1|altpll_component|_clk0~clkctrl\);

\inst|Add0~100_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Add0~100\ = \inst|counter\(3) & (\inst|Add0~99\ $ GND) # !\inst|counter\(3) & !\inst|Add0~99\ & VCC
-- \inst|Add0~101\ = CARRY(\inst|counter\(3) & !\inst|Add0~99\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|counter\(3),
	datad => VCC,
	cin => \inst|Add0~99\,
	combout => \inst|Add0~100\,
	cout => \inst|Add0~101\);

\inst|Add0~102_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Add0~102\ = \inst|counter\(4) & !\inst|Add0~101\ # !\inst|counter\(4) & (\inst|Add0~101\ # GND)
-- \inst|Add0~103\ = CARRY(!\inst|Add0~101\ # !\inst|counter\(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst|counter\(4),
	datad => VCC,
	cin => \inst|Add0~101\,
	combout => \inst|Add0~102\,
	cout => \inst|Add0~103\);

\inst|Add0~104_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Add0~104\ = \inst|counter\(5) & (\inst|Add0~103\ $ GND) # !\inst|counter\(5) & !\inst|Add0~103\ & VCC
-- \inst|Add0~105\ = CARRY(\inst|counter\(5) & !\inst|Add0~103\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|counter\(5),
	datad => VCC,
	cin => \inst|Add0~103\,
	combout => \inst|Add0~104\,
	cout => \inst|Add0~105\);

\inst|Add0~106_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Add0~106\ = \inst|counter\(6) & !\inst|Add0~105\ # !\inst|counter\(6) & (\inst|Add0~105\ # GND)
-- \inst|Add0~107\ = CARRY(!\inst|Add0~105\ # !\inst|counter\(6))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|counter\(6),
	datad => VCC,
	cin => \inst|Add0~105\,
	combout => \inst|Add0~106\,
	cout => \inst|Add0~107\);

\inst|Add0~108_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Add0~108\ = !\inst|Add0~107\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	cin => \inst|Add0~107\,
	combout => \inst|Add0~108\);

\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ = \inst|Add0~102\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ & VCC # !\inst|Add0~102\ & 
-- !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\ = CARRY(!\inst|Add0~102\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100000101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Add0~102\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~19\);

\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\ = !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[6]~25\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\);

\inst|Mod0|auto_generated|divider|divider|StageOut[48]~31_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ = \inst|Add0~96\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Add0~96\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\);

\inst|Mod0|auto_generated|divider|divider|StageOut[48]~23_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\ = \inst|Add0~96\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Add0~96\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\);

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\ = \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\ # \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~31\,
	datad => \inst|Mod0|auto_generated|divider|divider|StageOut[48]~23\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\);

\inst|Add0~96_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Add0~96\ = \inst|counter\(0) & (\inst|counter\(1) $ VCC) # !\inst|counter\(0) & \inst|counter\(1) & VCC
-- \inst|Add0~97\ = CARRY(\inst|counter\(0) & \inst|counter\(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110011010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|counter\(0),
	datab => \inst|counter\(1),
	datad => VCC,
	combout => \inst|Add0~96\,
	cout => \inst|Add0~97\);

\inst|Mod0|auto_generated|divider|divider|StageOut[54]~17_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ = \inst|Add0~108\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Add0~108\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\);

\inst|Mod0|auto_generated|divider|divider|StageOut[53]~18_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\ = \inst|Add0~106\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Add0~106\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[53]~18\);

\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ = \inst|Add0~104\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Add0~104\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\);

\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ = \inst|Add0~100\ $ VCC
-- \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\ = CARRY(\inst|Add0~100\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Add0~100\,
	datad => VCC,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~17\);

\inst|Mod0|auto_generated|divider|divider|StageOut[50]~29_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[2]~16\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[50]~29\);

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\ = (\inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ # \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\)
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\ = CARRY(\inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\ # \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000111101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~22\,
	datab => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\,
	datad => VCC,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~21\);

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ & ((\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ # 
-- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\)) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ # 
-- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ # GND)
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ = CARRY(\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ # \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ # 
-- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001111011101111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\,
	datab => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[3]~23\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\);

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\ = \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & (!\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\) # 
-- !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ # 
-- !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\ # GND))
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\ # 
-- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001111000011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\,
	datab => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~25\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~27\);

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\ = CARRY(!\inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\ & !\inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\ & 
-- !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~25\,
	datab => \inst|Mod0|auto_generated|divider|divider|StageOut[54]~17\,
	datad => VCC,
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[6]~29\,
	cout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\);

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	cin => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[7]~31\,
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\);

\inst|Mod0|auto_generated|divider|divider|StageOut[57]~636_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Add0~96\) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & 
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[1]~18\,
	datac => \inst|Add0~96\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\);

\RESET~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_RESET,
	combout => \RESET~combout\);

\inst|counter[1]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|Mod0|auto_generated|divider|divider|StageOut[57]~636\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|counter\(1));

\inst|Add0~98_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Add0~98\ = \inst|counter\(2) & !\inst|Add0~97\ # !\inst|counter\(2) & (\inst|Add0~97\ # GND)
-- \inst|Add0~99\ = CARRY(!\inst|Add0~97\ # !\inst|counter\(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst|counter\(2),
	datad => VCC,
	cin => \inst|Add0~97\,
	combout => \inst|Add0~98\,
	cout => \inst|Add0~99\);

\inst|Mod0|auto_generated|divider|divider|StageOut[49]~30_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\ = \inst|Add0~98\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Add0~98\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[49]~30\);

\inst|Mod0|auto_generated|divider|divider|StageOut[58]~639_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & \inst|Add0~98\ # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & 
-- (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Add0~98\,
	datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[2]~20\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\);

\inst|counter[2]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|Mod0|auto_generated|divider|divider|StageOut[58]~639\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|counter\(2));

\inst|Mod0|auto_generated|divider|divider|StageOut[51]~28_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ = \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\ & !\inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[3]~18\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\);

\inst|Mod0|auto_generated|divider|divider|StageOut[51]~20_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\ = \inst|Add0~102\ & \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|Add0~102\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_6_result_int[7]~26\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\);

\inst|Mod0|auto_generated|divider|divider|StageOut[60]~642_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\ # \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\) 
-- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~28\,
	datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[4]~24\,
	datac => \inst|Mod0|auto_generated|divider|divider|StageOut[51]~20\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\);

\inst|counter[4]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|Mod0|auto_generated|divider|divider|StageOut[60]~642\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|counter\(4));

\inst|Mod0|auto_generated|divider|divider|StageOut[61]~640_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\ # \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\) 
-- # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~27\,
	datab => \inst|Mod0|auto_generated|divider|divider|StageOut[52]~19\,
	datac => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[5]~26\,
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\);

\inst|counter[5]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|Mod0|auto_generated|divider|divider|StageOut[61]~640\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|counter\(5));

\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\ = !\inst|counter\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|counter\(0),
	combout => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\);

\inst|Mod0|auto_generated|divider|divider|StageOut[56]~637_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\ = \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & (!\inst|counter\(0)) # !\inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\ & 
-- \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[0]~34\,
	datac => \inst|counter\(0),
	datad => \inst|Mod0|auto_generated|divider|divider|add_sub_7_result_int[8]~32\,
	combout => \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\);

\inst|counter[0]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|Mod0|auto_generated|divider|divider|StageOut[56]~637\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|counter\(0));

\inst|Equal1~58_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Equal1~58\ = !\inst|counter\(3) & \inst|counter\(0) & \inst|counter\(1) & !\inst|counter\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|counter\(3),
	datab => \inst|counter\(0),
	datac => \inst|counter\(1),
	datad => \inst|counter\(2),
	combout => \inst|Equal1~58\);

\inst|Equal1~59_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|Equal1~59\ = \inst|counter\(6) & !\inst|counter\(4) & \inst|counter\(5) & \inst|Equal1~58\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|counter\(6),
	datab => \inst|counter\(4),
	datac => \inst|counter\(5),
	datad => \inst|Equal1~58\,
	combout => \inst|Equal1~59\);

\inst|knightlight~1269_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1269\ = \inst|ledstate\ & (\inst|knightlight\(5)) # !\inst|ledstate\ & \inst|knightlight\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ledstate\,
	datac => \inst|knightlight\(3),
	datad => \inst|knightlight\(5),
	combout => \inst|knightlight~1269\);

\inst|knightlight~1270_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1270\ = \inst|Equal1~59\ & \inst|knightlight~1269\ # !\inst|Equal1~59\ & (\inst|knightlight\(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|knightlight~1269\,
	datac => \inst|knightlight\(4),
	datad => \inst|Equal1~59\,
	combout => \inst|knightlight~1270\);

\inst|knightlight[4]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|knightlight~1270\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|knightlight\(4));

\inst|knightlight~1271_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1271\ = \inst|ledstate\ & (\inst|knightlight\(4)) # !\inst|ledstate\ & \inst|knightlight\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|knightlight\(2),
	datac => \inst|ledstate\,
	datad => \inst|knightlight\(4),
	combout => \inst|knightlight~1271\);

\inst|knightlight~1272_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1272\ = \inst|Equal1~59\ & (\inst|knightlight~1271\) # !\inst|Equal1~59\ & \inst|knightlight\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Equal1~59\,
	datac => \inst|knightlight\(3),
	datad => \inst|knightlight~1271\,
	combout => \inst|knightlight~1272\);

\inst|knightlight[3]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|knightlight~1272\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|knightlight\(3));

\inst|knightlight~1273_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1273\ = \inst|ledstate\ & (\inst|knightlight\(3)) # !\inst|ledstate\ & \inst|knightlight\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100101011001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|knightlight\(1),
	datab => \inst|knightlight\(3),
	datac => \inst|ledstate\,
	combout => \inst|knightlight~1273\);

\inst|knightlight~1274_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1274\ = \inst|Equal1~59\ & (\inst|knightlight~1273\) # !\inst|Equal1~59\ & \inst|knightlight\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal1~59\,
	datac => \inst|knightlight\(2),
	datad => \inst|knightlight~1273\,
	combout => \inst|knightlight~1274\);

\inst|knightlight[2]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|knightlight~1274\,
	sdata => VCC,
	sload => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|knightlight\(2));

\inst|knightlight~1277_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1277\ = \inst|Equal1~59\ & \inst|ledstate\ & (\inst|knightlight\(1)) # !\inst|Equal1~59\ & (\inst|knightlight\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal1~59\,
	datab => \inst|ledstate\,
	datac => \inst|knightlight\(0),
	datad => \inst|knightlight\(1),
	combout => \inst|knightlight~1277\);

\inst|knightlight[0]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|knightlight~1277\,
	sdata => VCC,
	sload => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|knightlight\(0));

\inst|knightlight~1275_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1275\ = \inst|ledstate\ & \inst|knightlight\(2) # !\inst|ledstate\ & (\inst|knightlight\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|knightlight\(2),
	datac => \inst|ledstate\,
	datad => \inst|knightlight\(0),
	combout => \inst|knightlight~1275\);

\inst|knightlight~1276_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1276\ = \inst|Equal1~59\ & (\inst|knightlight~1275\) # !\inst|Equal1~59\ & \inst|knightlight\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal1~59\,
	datac => \inst|knightlight\(1),
	datad => \inst|knightlight~1275\,
	combout => \inst|knightlight~1276\);

\inst|knightlight[1]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|knightlight~1276\,
	sdata => VCC,
	sload => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|knightlight\(1));

\inst|ledstate_next~431_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|ledstate_next~431\ = \inst|knightlight\(2) & (\inst|knightlight\(6) # \inst|knightlight\(5)) # !\inst|knightlight\(2) & \inst|knightlight\(6) & \inst|knightlight\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|knightlight\(2),
	datac => \inst|knightlight\(6),
	datad => \inst|knightlight\(5),
	combout => \inst|ledstate_next~431\);

\inst|ledstate_next~432_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|ledstate_next~432\ = \inst|ledstate\ & \inst|knightlight\(2) & \inst|knightlight\(1) & !\inst|ledstate_next~431\ # !\inst|ledstate\ & !\inst|knightlight\(2) & !\inst|knightlight\(1) & \inst|ledstate_next~431\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000110000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ledstate\,
	datab => \inst|knightlight\(2),
	datac => \inst|knightlight\(1),
	datad => \inst|ledstate_next~431\,
	combout => \inst|ledstate_next~432\);

\inst|ledstate_next~433_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|ledstate_next~433\ = \inst|knightlight\(0) # \inst|knightlight\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|knightlight\(0),
	datad => \inst|knightlight\(3),
	combout => \inst|ledstate_next~433\);

\inst|ledstate_next~436_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|ledstate_next~436\ = \inst|ledstate_next~435\ & (\inst|ledstate\ # \inst|ledstate_next~432\ & !\inst|ledstate_next~433\) # !\inst|ledstate_next~435\ & \inst|ledstate\ & (!\inst|ledstate_next~433\ # !\inst|ledstate_next~432\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011000011111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ledstate_next~435\,
	datab => \inst|ledstate_next~432\,
	datac => \inst|ledstate\,
	datad => \inst|ledstate_next~433\,
	combout => \inst|ledstate_next~436\);

\inst|ledstate~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|ledstate_next~436\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|ledstate\);

\inst|knightlight~1267_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1267\ = \inst|ledstate\ & \inst|knightlight\(6) # !\inst|ledstate\ & (\inst|knightlight\(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|knightlight\(6),
	datac => \inst|ledstate\,
	datad => \inst|knightlight\(4),
	combout => \inst|knightlight~1267\);

\inst|knightlight~1268_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1268\ = \inst|Equal1~59\ & (\inst|knightlight~1267\) # !\inst|Equal1~59\ & \inst|knightlight\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Equal1~59\,
	datac => \inst|knightlight\(5),
	datad => \inst|knightlight~1267\,
	combout => \inst|knightlight~1268\);

\inst|knightlight[5]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|knightlight~1268\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|knightlight\(5));

\inst|knightlight~1265_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1265\ = \inst|ledstate\ & (\inst|knightlight\(7)) # !\inst|ledstate\ & \inst|knightlight\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|knightlight\(5),
	datac => \inst|ledstate\,
	datad => \inst|knightlight\(7),
	combout => \inst|knightlight~1265\);

\inst|knightlight~1266_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1266\ = \inst|Equal1~59\ & (\inst|knightlight~1265\) # !\inst|Equal1~59\ & \inst|knightlight\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Equal1~59\,
	datac => \inst|knightlight\(6),
	datad => \inst|knightlight~1265\,
	combout => \inst|knightlight~1266\);

\inst|knightlight[6]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|knightlight~1266\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|knightlight\(6));

\inst|knightlight~1264_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \inst|knightlight~1264\ = \inst|Equal1~59\ & !\inst|ledstate\ & \inst|knightlight\(6) # !\inst|Equal1~59\ & (\inst|knightlight\(7))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100010011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ledstate\,
	datab => \inst|knightlight\(6),
	datac => \inst|knightlight\(7),
	datad => \inst|Equal1~59\,
	combout => \inst|knightlight~1264\);

\inst|knightlight[7]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \inst1|altpll_component|_clk0~clkctrl\,
	datain => \inst|knightlight~1264\,
	sclr => \ALT_INV_RESET~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|knightlight\(7));

\LEDS[7]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst|ALT_INV_knightlight\(7),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDS(7));

\LEDS[6]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst|ALT_INV_knightlight\(6),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDS(6));

\LEDS[5]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst|ALT_INV_knightlight\(5),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDS(5));

\LEDS[4]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst|ALT_INV_knightlight\(4),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDS(4));

\LEDS[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst|ALT_INV_knightlight\(3),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDS(3));

\LEDS[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst|ALT_INV_knightlight\(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDS(2));

\LEDS[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst|ALT_INV_knightlight\(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDS(1));

\LEDS[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \inst|ALT_INV_knightlight\(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDS(0));
END structure;