bsp2/Designflow/syn/rev_1/vga.vhm

   1 --
   2 -- Written by Synplicity
   3 -- Product Version "C-2009.06"
   4 -- Program "Synplify Pro", Mapper "map450rc, Build 029R"
   5 -- Wed Oct 21 17:26:36 2009
   6 --
   7
   8 --
   9 -- Written by Synplify Pro version Build 029R
  10 -- Wed Oct 21 17:26:36 2009
  11 --
  12
  13 --
  14 library ieee, stratix;
  15 use ieee.std_logic_1164.all;
  16 use ieee.numeric_std.all;
  17 library synplify;
  18 use synplify.components.all;
  19 use stratix.stratix_components.all;
  20
  21 entity vga_control is
  22 port(
  23   line_counter_sig_0 :  in std_logic;
  24   line_counter_sig_2 :  in std_logic;
  25   line_counter_sig_1 :  in std_logic;
  26   line_counter_sig_3 :  in std_logic;
  27   line_counter_sig_6 :  in std_logic;
  28   line_counter_sig_5 :  in std_logic;
  29   line_counter_sig_4 :  in std_logic;
  30   line_counter_sig_7 :  in std_logic;
  31   line_counter_sig_8 :  in std_logic;
  32   column_counter_sig_0 :  in std_logic;
  33   column_counter_sig_1 :  in std_logic;
  34   column_counter_sig_2 :  in std_logic;
  35   column_counter_sig_8 :  in std_logic;
  36   column_counter_sig_3 :  in std_logic;
  37   column_counter_sig_5 :  in std_logic;
  38   column_counter_sig_4 :  in std_logic;
  39   column_counter_sig_9 :  in std_logic;
  40   column_counter_sig_7 :  in std_logic;
  41   column_counter_sig_6 :  in std_logic;
  42   toggle_counter_sig_0 :  out std_logic;
  43   toggle_counter_sig_1 :  out std_logic;
  44   toggle_counter_sig_2 :  out std_logic;
  45   toggle_counter_sig_3 :  out std_logic;
  46   toggle_counter_sig_4 :  out std_logic;
  47   toggle_counter_sig_5 :  out std_logic;
  48   toggle_counter_sig_6 :  out std_logic;
  49   toggle_counter_sig_7 :  out std_logic;
  50   toggle_counter_sig_8 :  out std_logic;
  51   toggle_counter_sig_9 :  out std_logic;
  52   toggle_counter_sig_10 :  out std_logic;
  53   toggle_counter_sig_11 :  out std_logic;
  54   toggle_counter_sig_12 :  out std_logic;
  55   toggle_counter_sig_13 :  out std_logic;
  56   toggle_counter_sig_14 :  out std_logic;
  57   toggle_counter_sig_15 :  out std_logic;
  58   toggle_counter_sig_16 :  out std_logic;
  59   toggle_counter_sig_17 :  out std_logic;
  60   toggle_counter_sig_18 :  out std_logic;
  61   toggle_counter_sig_19 :  out std_logic;
  62   toggle_counter_sig_20 :  out std_logic;
  63   toggle_counter_sig_21 :  out std_logic;
  64   toggle_counter_sig_22 :  out std_logic;
  65   toggle_counter_sig_23 :  out std_logic;
  66   toggle_counter_sig_24 :  out std_logic;
  67   h_enable_sig :  in std_logic;
  68   g :  out std_logic;
  69   b :  out std_logic;
  70   v_enable_sig :  in std_logic;
  71   r :  out std_logic;
  72   toggle_sig :  out std_logic;
  73   un6_dly_counter_0_x :  in std_logic;
  74   clk_pin_c :  in std_logic);
  75 end vga_control;
  76
  77 architecture beh of vga_control is
  78   signal devclrn : std_logic := '1';
  79   signal devpor : std_logic := '1';
  80   signal devoe : std_logic := '0';
  81   signal TOGGLE_COUNTER_SIG_COUT : std_logic_vector(18 downto 1);
  82   signal UN2_TOGGLE_COUNTER_NEXT_COUT : std_logic_vector(0 to 0);
  83   signal GND : std_logic ;
  84   signal TOGGLE_SIG_0_0_0_G1 : std_logic ;
  85   signal TOGGLE_SIG_83 : std_logic ;
  86   signal B_NEXT_0_SQMUXA_7_4 : std_logic ;
  87   signal B_NEXT_0_SQMUXA_7_5 : std_logic ;
  88   signal TOGGLE_SIG_0_0_0_G1_2 : std_logic ;
  89   signal UN1_TOGGLE_COUNTER_SIGLTO18 : std_logic ;
  90   signal UN1_TOGGLE_COUNTER_SIGLTO15 : std_logic ;
  91   signal UN5_V_ENABLELTO5 : std_logic ;
  92   signal B_NEXT_0_SQMUXA_7_3 : std_logic ;
  93   signal UN13_V_ENABLELTO6 : std_logic ;
  94   signal B_NEXT_0_SQMUXA_7_4_A : std_logic ;
  95   signal UN17_V_ENABLELTO3 : std_logic ;
  96   signal B_NEXT_0_SQMUXA_7_2 : std_logic ;
  97   signal UN9_V_ENABLELTO6 : std_logic ;
  98   signal UN1_TOGGLE_COUNTER_SIGLTO12 : std_logic ;
  99   signal UN5_V_ENABLELT2 : std_logic ;
 100   signal UN1_TOGGLE_COUNTER_SIGLTO9 : std_logic ;
 101   signal UN13_V_ENABLELTO4_0 : std_logic ;
 102   signal UN9_V_ENABLELTO4 : std_logic ;
 103   signal UN1_TOGGLE_COUNTER_SIGLT6 : std_logic ;
 104   signal TOGGLE_COUNTER_SIG_58 : std_logic ;
 105   signal TOGGLE_COUNTER_SIG_59 : std_logic ;
 106   signal TOGGLE_COUNTER_SIG_60 : std_logic ;
 107   signal TOGGLE_COUNTER_SIG_61 : std_logic ;
 108   signal TOGGLE_COUNTER_SIG_62 : std_logic ;
 109   signal TOGGLE_COUNTER_SIG_63 : std_logic ;
 110   signal TOGGLE_COUNTER_SIG_64 : std_logic ;
 111   signal TOGGLE_COUNTER_SIG_65 : std_logic ;
 112   signal TOGGLE_COUNTER_SIG_66 : std_logic ;
 113   signal TOGGLE_COUNTER_SIG_67 : std_logic ;
 114   signal TOGGLE_COUNTER_SIG_68 : std_logic ;
 115   signal TOGGLE_COUNTER_SIG_69 : std_logic ;
 116   signal TOGGLE_COUNTER_SIG_70 : std_logic ;
 117   signal TOGGLE_COUNTER_SIG_71 : std_logic ;
 118   signal TOGGLE_COUNTER_SIG_72 : std_logic ;
 119   signal TOGGLE_COUNTER_SIG_73 : std_logic ;
 120   signal TOGGLE_COUNTER_SIG_74 : std_logic ;
 121   signal TOGGLE_COUNTER_SIG_75 : std_logic ;
 122   signal TOGGLE_COUNTER_SIG_76 : std_logic ;
 123   signal TOGGLE_COUNTER_SIG_77 : std_logic ;
 124   signal TOGGLE_COUNTER_SIG_78 : std_logic ;
 125   signal TOGGLE_COUNTER_SIG_79 : std_logic ;
 126   signal TOGGLE_COUNTER_SIG_80 : std_logic ;
 127   signal TOGGLE_COUNTER_SIG_81 : std_logic ;
 128   signal TOGGLE_COUNTER_SIG_82 : std_logic ;
 129   signal VCC : std_logic ;
 130   signal TOGGLE_SIG_0_0_0_G1_I : std_logic ;
 131 begin
 132 \TOGGLE_COUNTER_SIG_24_\: stratix_lcell generic map (
 133     operation_mode => "normal",
 134     output_mode => "reg_only",
 135     synch_mode => "off",
 136      sum_lutc_input => "datac",
 137     lut_mask => "ff00")
 138 port map (
 139 regout => TOGGLE_COUNTER_SIG_82,
 140 clk => clk_pin_c,
 141 datad => GND,
 142 aclr => un6_dly_counter_0_x,
 143         devpor => devpor,
 144         devclrn => devclrn,
 145         dataa => VCC,
 146         datab => VCC,
 147         datac => VCC,
 148         sclr => GND,
 149         sload => GND,
 150         ena => VCC,
 151         cin => GND,
 152         inverta => GND,
 153         aload => GND);
 154 \TOGGLE_COUNTER_SIG_23_\: stratix_lcell generic map (
 155     operation_mode => "normal",
 156     output_mode => "reg_only",
 157     synch_mode => "off",
 158      sum_lutc_input => "datac",
 159     lut_mask => "ff00")
 160 port map (
 161 regout => TOGGLE_COUNTER_SIG_81,
 162 clk => clk_pin_c,
 163 datad => GND,
 164 aclr => un6_dly_counter_0_x,
 165         devpor => devpor,
 166         devclrn => devclrn,
 167         dataa => VCC,
 168         datab => VCC,
 169         datac => VCC,
 170         sclr => GND,
 171         sload => GND,
 172         ena => VCC,
 173         cin => GND,
 174         inverta => GND,
 175         aload => GND);
 176 \TOGGLE_COUNTER_SIG_22_\: stratix_lcell generic map (
 177     operation_mode => "normal",
 178     output_mode => "reg_only",
 179     synch_mode => "off",
 180      sum_lutc_input => "datac",
 181     lut_mask => "ff00")
 182 port map (
 183 regout => TOGGLE_COUNTER_SIG_80,
 184 clk => clk_pin_c,
 185 datad => GND,
 186 aclr => un6_dly_counter_0_x,
 187         devpor => devpor,
 188         devclrn => devclrn,
 189         dataa => VCC,
 190         datab => VCC,
 191         datac => VCC,
 192         sclr => GND,
 193         sload => GND,
 194         ena => VCC,
 195         cin => GND,
 196         inverta => GND,
 197         aload => GND);
 198 \TOGGLE_COUNTER_SIG_21_\: stratix_lcell generic map (
 199     operation_mode => "normal",
 200     output_mode => "reg_only",
 201     synch_mode => "off",
 202      sum_lutc_input => "datac",
 203     lut_mask => "ff00")
 204 port map (
 205 regout => TOGGLE_COUNTER_SIG_79,
 206 clk => clk_pin_c,
 207 datad => GND,
 208 aclr => un6_dly_counter_0_x,
 209         devpor => devpor,
 210         devclrn => devclrn,
 211         dataa => VCC,
 212         datab => VCC,
 213         datac => VCC,
 214         sclr => GND,
 215         sload => GND,
 216         ena => VCC,
 217         cin => GND,
 218         inverta => GND,
 219         aload => GND);
 220 \TOGGLE_COUNTER_SIG_20_\: stratix_lcell generic map (
 221     operation_mode => "normal",
 222     output_mode => "reg_only",
 223     synch_mode => "on",
 224      sum_lutc_input => "cin",
 225      cin_used => "true",
 226     lut_mask => "5a5a")
 227 port map (
 228 regout => TOGGLE_COUNTER_SIG_78,
 229 clk => clk_pin_c,
 230 dataa => TOGGLE_COUNTER_SIG_78,
 231 aclr => un6_dly_counter_0_x,
 232 sclr => TOGGLE_SIG_0_0_0_G1_I,
 233 cin => TOGGLE_COUNTER_SIG_COUT(18),
 234         devpor => devpor,
 235         devclrn => devclrn,
 236         datab => VCC,
 237         datac => VCC,
 238         datad => VCC,
 239         sload => GND,
 240         ena => VCC,
 241         inverta => GND,
 242         aload => GND);
 243 \TOGGLE_COUNTER_SIG_19_\: stratix_lcell generic map (
 244     operation_mode => "normal",
 245     output_mode => "reg_only",
 246     synch_mode => "on",
 247      sum_lutc_input => "cin",
 248      cin_used => "true",
 249     lut_mask => "6c6c")
 250 port map (
 251 regout => TOGGLE_COUNTER_SIG_77,
 252 clk => clk_pin_c,
 253 dataa => TOGGLE_COUNTER_SIG_76,
 254 datab => TOGGLE_COUNTER_SIG_77,
 255 aclr => un6_dly_counter_0_x,
 256 sclr => TOGGLE_SIG_0_0_0_G1_I,
 257 cin => TOGGLE_COUNTER_SIG_COUT(17),
 258         devpor => devpor,
 259         devclrn => devclrn,
 260         datac => VCC,
 261         datad => VCC,
 262         sload => GND,
 263         ena => VCC,
 264         inverta => GND,
 265         aload => GND);
 266 \TOGGLE_COUNTER_SIG_18_\: stratix_lcell generic map (
 267     operation_mode => "arithmetic",
 268     output_mode => "reg_and_comb",
 269     synch_mode => "on",
 270      sum_lutc_input => "cin",
 271      cin_used => "true",
 272     lut_mask => "5a80")
 273 port map (
 274 regout => TOGGLE_COUNTER_SIG_76,
 275 cout => TOGGLE_COUNTER_SIG_COUT(18),
 276 clk => clk_pin_c,
 277 dataa => TOGGLE_COUNTER_SIG_76,
 278 datab => TOGGLE_COUNTER_SIG_77,
 279 aclr => un6_dly_counter_0_x,
 280 sclr => TOGGLE_SIG_0_0_0_G1_I,
 281 cin => TOGGLE_COUNTER_SIG_COUT(16),
 282         devpor => devpor,
 283         devclrn => devclrn,
 284         datac => VCC,
 285         datad => VCC,
 286         sload => GND,
 287         ena => VCC,
 288         inverta => GND,
 289         aload => GND);
 290 \TOGGLE_COUNTER_SIG_17_\: stratix_lcell generic map (
 291     operation_mode => "arithmetic",
 292     output_mode => "reg_and_comb",
 293     synch_mode => "on",
 294      sum_lutc_input => "cin",
 295      cin_used => "true",
 296     lut_mask => "6c80")
 297 port map (
 298 regout => TOGGLE_COUNTER_SIG_75,
 299 cout => TOGGLE_COUNTER_SIG_COUT(17),
 300 clk => clk_pin_c,
 301 dataa => TOGGLE_COUNTER_SIG_74,
 302 datab => TOGGLE_COUNTER_SIG_75,
 303 aclr => un6_dly_counter_0_x,
 304 sclr => TOGGLE_SIG_0_0_0_G1_I,
 305 cin => TOGGLE_COUNTER_SIG_COUT(15),
 306         devpor => devpor,
 307         devclrn => devclrn,
 308         datac => VCC,
 309         datad => VCC,
 310         sload => GND,
 311         ena => VCC,
 312         inverta => GND,
 313         aload => GND);
 314 \TOGGLE_COUNTER_SIG_16_\: stratix_lcell generic map (
 315     operation_mode => "arithmetic",
 316     output_mode => "reg_and_comb",
 317     synch_mode => "on",
 318      sum_lutc_input => "cin",
 319      cin_used => "true",
 320     lut_mask => "5a80")
 321 port map (
 322 regout => TOGGLE_COUNTER_SIG_74,
 323 cout => TOGGLE_COUNTER_SIG_COUT(16),
 324 clk => clk_pin_c,
 325 dataa => TOGGLE_COUNTER_SIG_74,
 326 datab => TOGGLE_COUNTER_SIG_75,
 327 aclr => un6_dly_counter_0_x,
 328 sclr => TOGGLE_SIG_0_0_0_G1_I,
 329 cin => TOGGLE_COUNTER_SIG_COUT(14),
 330         devpor => devpor,
 331         devclrn => devclrn,
 332         datac => VCC,
 333         datad => VCC,
 334         sload => GND,
 335         ena => VCC,
 336         inverta => GND,
 337         aload => GND);
 338 \TOGGLE_COUNTER_SIG_15_\: stratix_lcell generic map (
 339     operation_mode => "arithmetic",
 340     output_mode => "reg_and_comb",
 341     synch_mode => "on",
 342      sum_lutc_input => "cin",
 343      cin_used => "true",
 344     lut_mask => "6c80")
 345 port map (
 346 regout => TOGGLE_COUNTER_SIG_73,
 347 cout => TOGGLE_COUNTER_SIG_COUT(15),
 348 clk => clk_pin_c,
 349 dataa => TOGGLE_COUNTER_SIG_72,
 350 datab => TOGGLE_COUNTER_SIG_73,
 351 aclr => un6_dly_counter_0_x,
 352 sclr => TOGGLE_SIG_0_0_0_G1_I,
 353 cin => TOGGLE_COUNTER_SIG_COUT(13),
 354         devpor => devpor,
 355         devclrn => devclrn,
 356         datac => VCC,
 357         datad => VCC,
 358         sload => GND,
 359         ena => VCC,
 360         inverta => GND,
 361         aload => GND);
 362 \TOGGLE_COUNTER_SIG_14_\: stratix_lcell generic map (
 363     operation_mode => "arithmetic",
 364     output_mode => "reg_and_comb",
 365     synch_mode => "on",
 366      sum_lutc_input => "cin",
 367      cin_used => "true",
 368     lut_mask => "5a80")
 369 port map (
 370 regout => TOGGLE_COUNTER_SIG_72,
 371 cout => TOGGLE_COUNTER_SIG_COUT(14),
 372 clk => clk_pin_c,
 373 dataa => TOGGLE_COUNTER_SIG_72,
 374 datab => TOGGLE_COUNTER_SIG_73,
 375 aclr => un6_dly_counter_0_x,
 376 sclr => TOGGLE_SIG_0_0_0_G1_I,
 377 cin => TOGGLE_COUNTER_SIG_COUT(12),
 378         devpor => devpor,
 379         devclrn => devclrn,
 380         datac => VCC,
 381         datad => VCC,
 382         sload => GND,
 383         ena => VCC,
 384         inverta => GND,
 385         aload => GND);
 386 \TOGGLE_COUNTER_SIG_13_\: stratix_lcell generic map (
 387     operation_mode => "arithmetic",
 388     output_mode => "reg_and_comb",
 389     synch_mode => "on",
 390      sum_lutc_input => "cin",
 391      cin_used => "true",
 392     lut_mask => "6c80")
 393 port map (
 394 regout => TOGGLE_COUNTER_SIG_71,
 395 cout => TOGGLE_COUNTER_SIG_COUT(13),
 396 clk => clk_pin_c,
 397 dataa => TOGGLE_COUNTER_SIG_70,
 398 datab => TOGGLE_COUNTER_SIG_71,
 399 aclr => un6_dly_counter_0_x,
 400 sclr => TOGGLE_SIG_0_0_0_G1_I,
 401 cin => TOGGLE_COUNTER_SIG_COUT(11),
 402         devpor => devpor,
 403         devclrn => devclrn,
 404         datac => VCC,
 405         datad => VCC,
 406         sload => GND,
 407         ena => VCC,
 408         inverta => GND,
 409         aload => GND);
 410 \TOGGLE_COUNTER_SIG_12_\: stratix_lcell generic map (
 411     operation_mode => "arithmetic",
 412     output_mode => "reg_and_comb",
 413     synch_mode => "on",
 414      sum_lutc_input => "cin",
 415      cin_used => "true",
 416     lut_mask => "5a80")
 417 port map (
 418 regout => TOGGLE_COUNTER_SIG_70,
 419 cout => TOGGLE_COUNTER_SIG_COUT(12),
 420 clk => clk_pin_c,
 421 dataa => TOGGLE_COUNTER_SIG_70,
 422 datab => TOGGLE_COUNTER_SIG_71,
 423 aclr => un6_dly_counter_0_x,
 424 sclr => TOGGLE_SIG_0_0_0_G1_I,
 425 cin => TOGGLE_COUNTER_SIG_COUT(10),
 426         devpor => devpor,
 427         devclrn => devclrn,
 428         datac => VCC,
 429         datad => VCC,
 430         sload => GND,
 431         ena => VCC,
 432         inverta => GND,
 433         aload => GND);
 434 \TOGGLE_COUNTER_SIG_11_\: stratix_lcell generic map (
 435     operation_mode => "arithmetic",
 436     output_mode => "reg_and_comb",
 437     synch_mode => "on",
 438      sum_lutc_input => "cin",
 439      cin_used => "true",
 440     lut_mask => "6c80")
 441 port map (
 442 regout => TOGGLE_COUNTER_SIG_69,
 443 cout => TOGGLE_COUNTER_SIG_COUT(11),
 444 clk => clk_pin_c,
 445 dataa => TOGGLE_COUNTER_SIG_68,
 446 datab => TOGGLE_COUNTER_SIG_69,
 447 aclr => un6_dly_counter_0_x,
 448 sclr => TOGGLE_SIG_0_0_0_G1_I,
 449 cin => TOGGLE_COUNTER_SIG_COUT(9),
 450         devpor => devpor,
 451         devclrn => devclrn,
 452         datac => VCC,
 453         datad => VCC,
 454         sload => GND,
 455         ena => VCC,
 456         inverta => GND,
 457         aload => GND);
 458 \TOGGLE_COUNTER_SIG_10_\: stratix_lcell generic map (
 459     operation_mode => "arithmetic",
 460     output_mode => "reg_and_comb",
 461     synch_mode => "on",
 462      sum_lutc_input => "cin",
 463      cin_used => "true",
 464     lut_mask => "5a80")
 465 port map (
 466 regout => TOGGLE_COUNTER_SIG_68,
 467 cout => TOGGLE_COUNTER_SIG_COUT(10),
 468 clk => clk_pin_c,
 469 dataa => TOGGLE_COUNTER_SIG_68,
 470 datab => TOGGLE_COUNTER_SIG_69,
 471 aclr => un6_dly_counter_0_x,
 472 sclr => TOGGLE_SIG_0_0_0_G1_I,
 473 cin => TOGGLE_COUNTER_SIG_COUT(8),
 474         devpor => devpor,
 475         devclrn => devclrn,
 476         datac => VCC,
 477         datad => VCC,
 478         sload => GND,
 479         ena => VCC,
 480         inverta => GND,
 481         aload => GND);
 482 \TOGGLE_COUNTER_SIG_9_\: stratix_lcell generic map (
 483     operation_mode => "arithmetic",
 484     output_mode => "reg_and_comb",
 485     synch_mode => "on",
 486      sum_lutc_input => "cin",
 487      cin_used => "true",
 488     lut_mask => "6c80")
 489 port map (
 490 regout => TOGGLE_COUNTER_SIG_67,
 491 cout => TOGGLE_COUNTER_SIG_COUT(9),
 492 clk => clk_pin_c,
 493 dataa => TOGGLE_COUNTER_SIG_66,
 494 datab => TOGGLE_COUNTER_SIG_67,
 495 aclr => un6_dly_counter_0_x,
 496 sclr => TOGGLE_SIG_0_0_0_G1_I,
 497 cin => TOGGLE_COUNTER_SIG_COUT(7),
 498         devpor => devpor,
 499         devclrn => devclrn,
 500         datac => VCC,
 501         datad => VCC,
 502         sload => GND,
 503         ena => VCC,
 504         inverta => GND,
 505         aload => GND);
 506 \TOGGLE_COUNTER_SIG_8_\: stratix_lcell generic map (
 507     operation_mode => "arithmetic",
 508     output_mode => "reg_and_comb",
 509     synch_mode => "on",
 510      sum_lutc_input => "cin",
 511      cin_used => "true",
 512     lut_mask => "5a80")
 513 port map (
 514 regout => TOGGLE_COUNTER_SIG_66,
 515 cout => TOGGLE_COUNTER_SIG_COUT(8),
 516 clk => clk_pin_c,
 517 dataa => TOGGLE_COUNTER_SIG_66,
 518 datab => TOGGLE_COUNTER_SIG_67,
 519 aclr => un6_dly_counter_0_x,
 520 sclr => TOGGLE_SIG_0_0_0_G1_I,
 521 cin => TOGGLE_COUNTER_SIG_COUT(6),
 522         devpor => devpor,
 523         devclrn => devclrn,
 524         datac => VCC,
 525         datad => VCC,
 526         sload => GND,
 527         ena => VCC,
 528         inverta => GND,
 529         aload => GND);
 530 \TOGGLE_COUNTER_SIG_7_\: stratix_lcell generic map (
 531     operation_mode => "arithmetic",
 532     output_mode => "reg_and_comb",
 533     synch_mode => "on",
 534      sum_lutc_input => "cin",
 535      cin_used => "true",
 536     lut_mask => "6c80")
 537 port map (
 538 regout => TOGGLE_COUNTER_SIG_65,
 539 cout => TOGGLE_COUNTER_SIG_COUT(7),
 540 clk => clk_pin_c,
 541 dataa => TOGGLE_COUNTER_SIG_64,
 542 datab => TOGGLE_COUNTER_SIG_65,
 543 aclr => un6_dly_counter_0_x,
 544 sclr => TOGGLE_SIG_0_0_0_G1_I,
 545 cin => TOGGLE_COUNTER_SIG_COUT(5),
 546         devpor => devpor,
 547         devclrn => devclrn,
 548         datac => VCC,
 549         datad => VCC,
 550         sload => GND,
 551         ena => VCC,
 552         inverta => GND,
 553         aload => GND);
 554 \TOGGLE_COUNTER_SIG_6_\: stratix_lcell generic map (
 555     operation_mode => "arithmetic",
 556     output_mode => "reg_and_comb",
 557     synch_mode => "on",
 558      sum_lutc_input => "cin",
 559      cin_used => "true",
 560     lut_mask => "5a80")
 561 port map (
 562 regout => TOGGLE_COUNTER_SIG_64,
 563 cout => TOGGLE_COUNTER_SIG_COUT(6),
 564 clk => clk_pin_c,
 565 dataa => TOGGLE_COUNTER_SIG_64,
 566 datab => TOGGLE_COUNTER_SIG_65,
 567 aclr => un6_dly_counter_0_x,
 568 sclr => TOGGLE_SIG_0_0_0_G1_I,
 569 cin => TOGGLE_COUNTER_SIG_COUT(4),
 570         devpor => devpor,
 571         devclrn => devclrn,
 572         datac => VCC,
 573         datad => VCC,
 574         sload => GND,
 575         ena => VCC,
 576         inverta => GND,
 577         aload => GND);
 578 \TOGGLE_COUNTER_SIG_5_\: stratix_lcell generic map (
 579     operation_mode => "arithmetic",
 580     output_mode => "reg_and_comb",
 581     synch_mode => "on",
 582      sum_lutc_input => "cin",
 583      cin_used => "true",
 584     lut_mask => "6c80")
 585 port map (
 586 regout => TOGGLE_COUNTER_SIG_63,
 587 cout => TOGGLE_COUNTER_SIG_COUT(5),
 588 clk => clk_pin_c,
 589 dataa => TOGGLE_COUNTER_SIG_62,
 590 datab => TOGGLE_COUNTER_SIG_63,
 591 aclr => un6_dly_counter_0_x,
 592 sclr => TOGGLE_SIG_0_0_0_G1_I,
 593 cin => TOGGLE_COUNTER_SIG_COUT(3),
 594         devpor => devpor,
 595         devclrn => devclrn,
 596         datac => VCC,
 597         datad => VCC,
 598         sload => GND,
 599         ena => VCC,
 600         inverta => GND,
 601         aload => GND);
 602 \TOGGLE_COUNTER_SIG_4_\: stratix_lcell generic map (
 603     operation_mode => "arithmetic",
 604     output_mode => "reg_and_comb",
 605     synch_mode => "on",
 606      sum_lutc_input => "cin",
 607      cin_used => "true",
 608     lut_mask => "5a80")
 609 port map (
 610 regout => TOGGLE_COUNTER_SIG_62,
 611 cout => TOGGLE_COUNTER_SIG_COUT(4),
 612 clk => clk_pin_c,
 613 dataa => TOGGLE_COUNTER_SIG_62,
 614 datab => TOGGLE_COUNTER_SIG_63,
 615 aclr => un6_dly_counter_0_x,
 616 sclr => TOGGLE_SIG_0_0_0_G1_I,
 617 cin => TOGGLE_COUNTER_SIG_COUT(2),
 618         devpor => devpor,
 619         devclrn => devclrn,
 620         datac => VCC,
 621         datad => VCC,
 622         sload => GND,
 623         ena => VCC,
 624         inverta => GND,
 625         aload => GND);
 626 \TOGGLE_COUNTER_SIG_3_\: stratix_lcell generic map (
 627     operation_mode => "arithmetic",
 628     output_mode => "reg_and_comb",
 629     synch_mode => "on",
 630      sum_lutc_input => "cin",
 631      cin_used => "true",
 632     lut_mask => "6c80")
 633 port map (
 634 regout => TOGGLE_COUNTER_SIG_61,
 635 cout => TOGGLE_COUNTER_SIG_COUT(3),
 636 clk => clk_pin_c,
 637 dataa => TOGGLE_COUNTER_SIG_60,
 638 datab => TOGGLE_COUNTER_SIG_61,
 639 aclr => un6_dly_counter_0_x,
 640 sclr => TOGGLE_SIG_0_0_0_G1_I,
 641 cin => TOGGLE_COUNTER_SIG_COUT(1),
 642         devpor => devpor,
 643         devclrn => devclrn,
 644         datac => VCC,
 645         datad => VCC,
 646         sload => GND,
 647         ena => VCC,
 648         inverta => GND,
 649         aload => GND);
 650 \TOGGLE_COUNTER_SIG_2_\: stratix_lcell generic map (
 651     operation_mode => "arithmetic",
 652     output_mode => "reg_and_comb",
 653     synch_mode => "on",
 654      sum_lutc_input => "cin",
 655      cin_used => "true",
 656     lut_mask => "5a80")
 657 port map (
 658 regout => TOGGLE_COUNTER_SIG_60,
 659 cout => TOGGLE_COUNTER_SIG_COUT(2),
 660 clk => clk_pin_c,
 661 dataa => TOGGLE_COUNTER_SIG_60,
 662 datab => TOGGLE_COUNTER_SIG_61,
 663 aclr => un6_dly_counter_0_x,
 664 sclr => TOGGLE_SIG_0_0_0_G1_I,
 665 cin => UN2_TOGGLE_COUNTER_NEXT_COUT(0),
 666         devpor => devpor,
 667         devclrn => devclrn,
 668         datac => VCC,
 669         datad => VCC,
 670         sload => GND,
 671         ena => VCC,
 672         inverta => GND,
 673         aload => GND);
 674 \TOGGLE_COUNTER_SIG_1_\: stratix_lcell generic map (
 675     operation_mode => "arithmetic",
 676     output_mode => "reg_and_comb",
 677     synch_mode => "on",
 678      sum_lutc_input => "datac",
 679     lut_mask => "6688")
 680 port map (
 681 regout => TOGGLE_COUNTER_SIG_59,
 682 cout => TOGGLE_COUNTER_SIG_COUT(1),
 683 clk => clk_pin_c,
 684 dataa => TOGGLE_COUNTER_SIG_58,
 685 datab => TOGGLE_COUNTER_SIG_59,
 686 aclr => un6_dly_counter_0_x,
 687 sclr => TOGGLE_SIG_0_0_0_G1_I,
 688         devpor => devpor,
 689         devclrn => devclrn,
 690         datac => VCC,
 691         datad => VCC,
 692         sload => GND,
 693         ena => VCC,
 694         cin => GND,
 695         inverta => GND,
 696         aload => GND);
 697 \TOGGLE_COUNTER_SIG_0_\: stratix_lcell generic map (
 698     operation_mode => "normal",
 699     output_mode => "reg_only",
 700     synch_mode => "on",
 701      sum_lutc_input => "datac",
 702     lut_mask => "5555")
 703 port map (
 704 regout => TOGGLE_COUNTER_SIG_58,
 705 clk => clk_pin_c,
 706 dataa => TOGGLE_COUNTER_SIG_58,
 707 aclr => un6_dly_counter_0_x,
 708 sclr => TOGGLE_SIG_0_0_0_G1_I,
 709         devpor => devpor,
 710         devclrn => devclrn,
 711         datab => VCC,
 712         datac => VCC,
 713         datad => VCC,
 714         sload => GND,
 715         ena => VCC,
 716         cin => GND,
 717         inverta => GND,
 718         aload => GND);
 719 TOGGLE_SIG_Z146: stratix_lcell generic map (
 720     operation_mode => "normal",
 721     output_mode => "reg_only",
 722     synch_mode => "off",
 723      sum_lutc_input => "datac",
 724     lut_mask => "9999")
 725 port map (
 726 regout => TOGGLE_SIG_83,
 727 clk => clk_pin_c,
 728 dataa => TOGGLE_SIG_83,
 729 datab => TOGGLE_SIG_0_0_0_G1,
 730 aclr => un6_dly_counter_0_x,
 731         devpor => devpor,
 732         devclrn => devclrn,
 733         datac => VCC,
 734         datad => VCC,
 735         sclr => GND,
 736         sload => GND,
 737         ena => VCC,
 738         cin => GND,
 739         inverta => GND,
 740         aload => GND);
 741 R_Z147: stratix_lcell generic map (
 742     operation_mode => "normal",
 743     output_mode => "reg_only",
 744     synch_mode => "off",
 745      sum_lutc_input => "datac",
 746     lut_mask => "8000")
 747 port map (
 748 regout => r,
 749 clk => clk_pin_c,
 750 dataa => TOGGLE_SIG_83,
 751 datab => v_enable_sig,
 752 datac => B_NEXT_0_SQMUXA_7_4,
 753 datad => B_NEXT_0_SQMUXA_7_5,
 754 aclr => un6_dly_counter_0_x,
 755         devpor => devpor,
 756         devclrn => devclrn,
 757         sclr => GND,
 758         sload => GND,
 759         ena => VCC,
 760         cin => GND,
 761         inverta => GND,
 762         aload => GND);
 763 B_Z148: stratix_lcell generic map (
 764     operation_mode => "normal",
 765     output_mode => "reg_only",
 766     synch_mode => "off",
 767      sum_lutc_input => "datac",
 768     lut_mask => "4000")
 769 port map (
 770 regout => b,
 771 clk => clk_pin_c,
 772 dataa => TOGGLE_SIG_83,
 773 datab => v_enable_sig,
 774 datac => B_NEXT_0_SQMUXA_7_4,
 775 datad => B_NEXT_0_SQMUXA_7_5,
 776 aclr => un6_dly_counter_0_x,
 777         devpor => devpor,
 778         devclrn => devclrn,
 779         sclr => GND,
 780         sload => GND,
 781         ena => VCC,
 782         cin => GND,
 783         inverta => GND,
 784         aload => GND);
 785 G_Z149: stratix_lcell generic map (
 786     operation_mode => "normal",
 787     output_mode => "reg_only",
 788     synch_mode => "off",
 789      sum_lutc_input => "datac",
 790     lut_mask => "ff00")
 791 port map (
 792 regout => g,
 793 clk => clk_pin_c,
 794 datad => GND,
 795 aclr => un6_dly_counter_0_x,
 796         devpor => devpor,
 797         devclrn => devclrn,
 798         dataa => VCC,
 799         datab => VCC,
 800         datac => VCC,
 801         sclr => GND,
 802         sload => GND,
 803         ena => VCC,
 804         cin => GND,
 805         inverta => GND,
 806         aload => GND);
 807 TOGGLE_SIG_0_0_0_G1_Z150: stratix_lcell generic map (
 808     operation_mode => "normal",
 809     output_mode => "comb_only",
 810     synch_mode => "off",
 811      sum_lutc_input => "datac",
 812     lut_mask => "0703")
 813 port map (
 814 combout => TOGGLE_SIG_0_0_0_G1,
 815 dataa => TOGGLE_COUNTER_SIG_77,
 816 datab => TOGGLE_COUNTER_SIG_78,
 817 datac => TOGGLE_SIG_0_0_0_G1_2,
 818 datad => UN1_TOGGLE_COUNTER_SIGLTO18,
 819         devpor => devpor,
 820         devclrn => devclrn,
 821         clk => GND,
 822         aclr => GND,
 823         sclr => GND,
 824         sload => GND,
 825         ena => VCC,
 826         cin => GND,
 827         inverta => GND,
 828         aload => GND);
 829 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO18: stratix_lcell generic map (
 830     operation_mode => "normal",
 831     output_mode => "comb_only",
 832     synch_mode => "off",
 833      sum_lutc_input => "datac",
 834     lut_mask => "7f77")
 835 port map (
 836 combout => UN1_TOGGLE_COUNTER_SIGLTO18,
 837 dataa => TOGGLE_COUNTER_SIG_75,
 838 datab => TOGGLE_COUNTER_SIG_76,
 839 datac => TOGGLE_COUNTER_SIG_74,
 840 datad => UN1_TOGGLE_COUNTER_SIGLTO15,
 841         devpor => devpor,
 842         devclrn => devclrn,
 843         clk => GND,
 844         aclr => GND,
 845         sclr => GND,
 846         sload => GND,
 847         ena => VCC,
 848         cin => GND,
 849         inverta => GND,
 850         aload => GND);
 851 B_NEXT_0_SQMUXA_7_5_Z152: stratix_lcell generic map (
 852     operation_mode => "normal",
 853     output_mode => "comb_only",
 854     synch_mode => "off",
 855      sum_lutc_input => "datac",
 856     lut_mask => "7f00")
 857 port map (
 858 combout => B_NEXT_0_SQMUXA_7_5,
 859 dataa => column_counter_sig_6,
 860 datab => column_counter_sig_7,
 861 datac => UN5_V_ENABLELTO5,
 862 datad => B_NEXT_0_SQMUXA_7_3,
 863         devpor => devpor,
 864         devclrn => devclrn,
 865         clk => GND,
 866         aclr => GND,
 867         sclr => GND,
 868         sload => GND,
 869         ena => VCC,
 870         cin => GND,
 871         inverta => GND,
 872         aload => GND);
 873 B_NEXT_0_SQMUXA_7_4_Z153: stratix_lcell generic map (
 874     operation_mode => "normal",
 875     output_mode => "comb_only",
 876     synch_mode => "off",
 877      sum_lutc_input => "datac",
 878     lut_mask => "ef23")
 879 port map (
 880 combout => B_NEXT_0_SQMUXA_7_4,
 881 dataa => line_counter_sig_8,
 882 datab => line_counter_sig_7,
 883 datac => UN13_V_ENABLELTO6,
 884 datad => B_NEXT_0_SQMUXA_7_4_A,
 885         devpor => devpor,
 886         devclrn => devclrn,
 887         clk => GND,
 888         aclr => GND,
 889         sclr => GND,
 890         sload => GND,
 891         ena => VCC,
 892         cin => GND,
 893         inverta => GND,
 894         aload => GND);
 895 B_NEXT_0_SQMUXA_7_4_A_Z154: stratix_lcell generic map (
 896     operation_mode => "normal",
 897     output_mode => "comb_only",
 898     synch_mode => "off",
 899      sum_lutc_input => "datac",
 900     lut_mask => "0f1f")
 901 port map (
 902 combout => B_NEXT_0_SQMUXA_7_4_A,
 903 dataa => line_counter_sig_4,
 904 datab => line_counter_sig_5,
 905 datac => line_counter_sig_6,
 906 datad => UN17_V_ENABLELTO3,
 907         devpor => devpor,
 908         devclrn => devclrn,
 909         clk => GND,
 910         aclr => GND,
 911         sclr => GND,
 912         sload => GND,
 913         ena => VCC,
 914         cin => GND,
 915         inverta => GND,
 916         aload => GND);
 917 B_NEXT_0_SQMUXA_7_3_Z155: stratix_lcell generic map (
 918     operation_mode => "normal",
 919     output_mode => "comb_only",
 920     synch_mode => "off",
 921      sum_lutc_input => "datac",
 922     lut_mask => "e0f0")
 923 port map (
 924 combout => B_NEXT_0_SQMUXA_7_3,
 925 dataa => column_counter_sig_7,
 926 datab => column_counter_sig_9,
 927 datac => B_NEXT_0_SQMUXA_7_2,
 928 datad => UN9_V_ENABLELTO6,
 929         devpor => devpor,
 930         devclrn => devclrn,
 931         clk => GND,
 932         aclr => GND,
 933         sclr => GND,
 934         sload => GND,
 935         ena => VCC,
 936         cin => GND,
 937         inverta => GND,
 938         aload => GND);
 939 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO15: stratix_lcell generic map (
 940     operation_mode => "normal",
 941     output_mode => "comb_only",
 942     synch_mode => "off",
 943      sum_lutc_input => "datac",
 944     lut_mask => "ff7f")
 945 port map (
 946 combout => UN1_TOGGLE_COUNTER_SIGLTO15,
 947 dataa => TOGGLE_COUNTER_SIG_71,
 948 datab => TOGGLE_COUNTER_SIG_72,
 949 datac => TOGGLE_COUNTER_SIG_73,
 950 datad => UN1_TOGGLE_COUNTER_SIGLTO12,
 951         devpor => devpor,
 952         devclrn => devclrn,
 953         clk => GND,
 954         aclr => GND,
 955         sclr => GND,
 956         sload => GND,
 957         ena => VCC,
 958         cin => GND,
 959         inverta => GND,
 960         aload => GND);
 961 DRAW_SQUARE_NEXT_UN5_V_ENABLELTO5: stratix_lcell generic map (
 962     operation_mode => "normal",
 963     output_mode => "comb_only",
 964     synch_mode => "off",
 965      sum_lutc_input => "datac",
 966     lut_mask => "feee")
 967 port map (
 968 combout => UN5_V_ENABLELTO5,
 969 dataa => column_counter_sig_4,
 970 datab => column_counter_sig_5,
 971 datac => column_counter_sig_3,
 972 datad => UN5_V_ENABLELT2,
 973         devpor => devpor,
 974         devclrn => devclrn,
 975         clk => GND,
 976         aclr => GND,
 977         sclr => GND,
 978         sload => GND,
 979         ena => VCC,
 980         cin => GND,
 981         inverta => GND,
 982         aload => GND);
 983 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO12: stratix_lcell generic map (
 984     operation_mode => "normal",
 985     output_mode => "comb_only",
 986     synch_mode => "off",
 987      sum_lutc_input => "datac",
 988     lut_mask => "0100")
 989 port map (
 990 combout => UN1_TOGGLE_COUNTER_SIGLTO12,
 991 dataa => TOGGLE_COUNTER_SIG_68,
 992 datab => TOGGLE_COUNTER_SIG_69,
 993 datac => TOGGLE_COUNTER_SIG_70,
 994 datad => UN1_TOGGLE_COUNTER_SIGLTO9,
 995         devpor => devpor,
 996         devclrn => devclrn,
 997         clk => GND,
 998         aclr => GND,
 999         sclr => GND,
1000         sload => GND,
1001         ena => VCC,
1002         cin => GND,
1003         inverta => GND,
1004         aload => GND);
1005 DRAW_SQUARE_NEXT_UN13_V_ENABLELTO6: stratix_lcell generic map (
1006     operation_mode => "normal",
1007     output_mode => "comb_only",
1008     synch_mode => "off",
1009      sum_lutc_input => "datac",
1010     lut_mask => "7f77")
1011 port map (
1012 combout => UN13_V_ENABLELTO6,
1013 dataa => line_counter_sig_5,
1014 datab => line_counter_sig_6,
1015 datac => line_counter_sig_3,
1016 datad => UN13_V_ENABLELTO4_0,
1017         devpor => devpor,
1018         devclrn => devclrn,
1019         clk => GND,
1020         aclr => GND,
1021         sclr => GND,
1022         sload => GND,
1023         ena => VCC,
1024         cin => GND,
1025         inverta => GND,
1026         aload => GND);
1027 DRAW_SQUARE_NEXT_UN9_V_ENABLELTO6: stratix_lcell generic map (
1028     operation_mode => "normal",
1029     output_mode => "comb_only",
1030     synch_mode => "off",
1031      sum_lutc_input => "datac",
1032     lut_mask => "f7f7")
1033 port map (
1034 combout => UN9_V_ENABLELTO6,
1035 dataa => column_counter_sig_5,
1036 datab => column_counter_sig_6,
1037 datac => UN9_V_ENABLELTO4,
1038         devpor => devpor,
1039         devclrn => devclrn,
1040         clk => GND,
1041         datad => VCC,
1042         aclr => GND,
1043         sclr => GND,
1044         sload => GND,
1045         ena => VCC,
1046         cin => GND,
1047         inverta => GND,
1048         aload => GND);
1049 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO9: stratix_lcell generic map (
1050     operation_mode => "normal",
1051     output_mode => "comb_only",
1052     synch_mode => "off",
1053      sum_lutc_input => "datac",
1054     lut_mask => "7f77")
1055 port map (
1056 combout => UN1_TOGGLE_COUNTER_SIGLTO9,
1057 dataa => TOGGLE_COUNTER_SIG_66,
1058 datab => TOGGLE_COUNTER_SIG_67,
1059 datac => TOGGLE_COUNTER_SIG_65,
1060 datad => UN1_TOGGLE_COUNTER_SIGLT6,
1061         devpor => devpor,
1062         devclrn => devclrn,
1063         clk => GND,
1064         aclr => GND,
1065         sclr => GND,
1066         sload => GND,
1067         ena => VCC,
1068         cin => GND,
1069         inverta => GND,
1070         aload => GND);
1071 DRAW_SQUARE_NEXT_UN17_V_ENABLELTO3: stratix_lcell generic map (
1072     operation_mode => "normal",
1073     output_mode => "comb_only",
1074     synch_mode => "off",
1075      sum_lutc_input => "datac",
1076     lut_mask => "fe00")
1077 port map (
1078 combout => UN17_V_ENABLELTO3,
1079 dataa => line_counter_sig_1,
1080 datab => line_counter_sig_2,
1081 datac => line_counter_sig_0,
1082 datad => line_counter_sig_3,
1083         devpor => devpor,
1084         devclrn => devclrn,
1085         clk => GND,
1086         aclr => GND,
1087         sclr => GND,
1088         sload => GND,
1089         ena => VCC,
1090         cin => GND,
1091         inverta => GND,
1092         aload => GND);
1093 TOGGLE_SIG_0_0_0_G1_2_Z163: stratix_lcell generic map (
1094     operation_mode => "normal",
1095     output_mode => "comb_only",
1096     synch_mode => "off",
1097      sum_lutc_input => "datac",
1098     lut_mask => "fffe")
1099 port map (
1100 combout => TOGGLE_SIG_0_0_0_G1_2,
1101 dataa => TOGGLE_COUNTER_SIG_81,
1102 datab => TOGGLE_COUNTER_SIG_82,
1103 datac => TOGGLE_COUNTER_SIG_79,
1104 datad => TOGGLE_COUNTER_SIG_80,
1105         devpor => devpor,
1106         devclrn => devclrn,
1107         clk => GND,
1108         aclr => GND,
1109         sclr => GND,
1110         sload => GND,
1111         ena => VCC,
1112         cin => GND,
1113         inverta => GND,
1114         aload => GND);
1115 B_NEXT_0_SQMUXA_7_2_Z164: stratix_lcell generic map (
1116     operation_mode => "normal",
1117     output_mode => "comb_only",
1118     synch_mode => "off",
1119      sum_lutc_input => "datac",
1120     lut_mask => "0004")
1121 port map (
1122 combout => B_NEXT_0_SQMUXA_7_2,
1123 dataa => column_counter_sig_8,
1124 datab => h_enable_sig,
1125 datac => column_counter_sig_9,
1126 datad => line_counter_sig_8,
1127         devpor => devpor,
1128         devclrn => devclrn,
1129         clk => GND,
1130         aclr => GND,
1131         sclr => GND,
1132         sload => GND,
1133         ena => VCC,
1134         cin => GND,
1135         inverta => GND,
1136         aload => GND);
1137 DRAW_SQUARE_NEXT_UN9_V_ENABLELTO4: stratix_lcell generic map (
1138     operation_mode => "normal",
1139     output_mode => "comb_only",
1140     synch_mode => "off",
1141      sum_lutc_input => "datac",
1142     lut_mask => "0101")
1143 port map (
1144 combout => UN9_V_ENABLELTO4,
1145 dataa => column_counter_sig_3,
1146 datab => column_counter_sig_4,
1147 datac => column_counter_sig_2,
1148         devpor => devpor,
1149         devclrn => devclrn,
1150         clk => GND,
1151         datad => VCC,
1152         aclr => GND,
1153         sclr => GND,
1154         sload => GND,
1155         ena => VCC,
1156         cin => GND,
1157         inverta => GND,
1158         aload => GND);
1159 DRAW_SQUARE_NEXT_UN5_V_ENABLELT2: stratix_lcell generic map (
1160     operation_mode => "normal",
1161     output_mode => "comb_only",
1162     synch_mode => "off",
1163      sum_lutc_input => "datac",
1164     lut_mask => "fefe")
1165 port map (
1166 combout => UN5_V_ENABLELT2,
1167 dataa => column_counter_sig_1,
1168 datab => column_counter_sig_2,
1169 datac => column_counter_sig_0,
1170         devpor => devpor,
1171         devclrn => devclrn,
1172         clk => GND,
1173         datad => VCC,
1174         aclr => GND,
1175         sclr => GND,
1176         sload => GND,
1177         ena => VCC,
1178         cin => GND,
1179         inverta => GND,
1180         aload => GND);
1181 DRAW_SQUARE_NEXT_UN13_V_ENABLELTO4_0: stratix_lcell generic map (
1182     operation_mode => "normal",
1183     output_mode => "comb_only",
1184     synch_mode => "off",
1185      sum_lutc_input => "datac",
1186     lut_mask => "1111")
1187 port map (
1188 combout => UN13_V_ENABLELTO4_0,
1189 dataa => line_counter_sig_4,
1190 datab => line_counter_sig_2,
1191         devpor => devpor,
1192         devclrn => devclrn,
1193         clk => GND,
1194         datac => VCC,
1195         datad => VCC,
1196         aclr => GND,
1197         sclr => GND,
1198         sload => GND,
1199         ena => VCC,
1200         cin => GND,
1201         inverta => GND,
1202         aload => GND);
1203 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLT6: stratix_lcell generic map (
1204     operation_mode => "normal",
1205     output_mode => "comb_only",
1206     synch_mode => "off",
1207      sum_lutc_input => "datac",
1208     lut_mask => "7777")
1209 port map (
1210 combout => UN1_TOGGLE_COUNTER_SIGLT6,
1211 dataa => TOGGLE_COUNTER_SIG_64,
1212 datab => TOGGLE_COUNTER_SIG_63,
1213         devpor => devpor,
1214         devclrn => devclrn,
1215         clk => GND,
1216         datac => VCC,
1217         datad => VCC,
1218         aclr => GND,
1219         sclr => GND,
1220         sload => GND,
1221         ena => VCC,
1222         cin => GND,
1223         inverta => GND,
1224         aload => GND);
1225 \UN2_TOGGLE_COUNTER_NEXT_0_\: stratix_lcell generic map (
1226     operation_mode => "arithmetic",
1227     output_mode => "comb_only",
1228     synch_mode => "off",
1229      sum_lutc_input => "datac",
1230     lut_mask => "5588")
1231 port map (
1232 cout => UN2_TOGGLE_COUNTER_NEXT_COUT(0),
1233 dataa => TOGGLE_COUNTER_SIG_58,
1234 datab => TOGGLE_COUNTER_SIG_59,
1235         devpor => devpor,
1236         devclrn => devclrn,
1237         clk => GND,
1238         datac => VCC,
1239         datad => VCC,
1240         aclr => GND,
1241         sclr => GND,
1242         sload => GND,
1243         ena => VCC,
1244         cin => GND,
1245         inverta => GND,
1246         aload => GND);
1247 GND <= '0';
1248 VCC <= '1';
1249 TOGGLE_SIG_0_0_0_G1_I <= not TOGGLE_SIG_0_0_0_G1;
1250 toggle_counter_sig_0 <= TOGGLE_COUNTER_SIG_58;
1251 toggle_counter_sig_1 <= TOGGLE_COUNTER_SIG_59;
1252 toggle_counter_sig_2 <= TOGGLE_COUNTER_SIG_60;
1253 toggle_counter_sig_3 <= TOGGLE_COUNTER_SIG_61;
1254 toggle_counter_sig_4 <= TOGGLE_COUNTER_SIG_62;
1255 toggle_counter_sig_5 <= TOGGLE_COUNTER_SIG_63;
1256 toggle_counter_sig_6 <= TOGGLE_COUNTER_SIG_64;
1257 toggle_counter_sig_7 <= TOGGLE_COUNTER_SIG_65;
1258 toggle_counter_sig_8 <= TOGGLE_COUNTER_SIG_66;
1259 toggle_counter_sig_9 <= TOGGLE_COUNTER_SIG_67;
1260 toggle_counter_sig_10 <= TOGGLE_COUNTER_SIG_68;
1261 toggle_counter_sig_11 <= TOGGLE_COUNTER_SIG_69;
1262 toggle_counter_sig_12 <= TOGGLE_COUNTER_SIG_70;
1263 toggle_counter_sig_13 <= TOGGLE_COUNTER_SIG_71;
1264 toggle_counter_sig_14 <= TOGGLE_COUNTER_SIG_72;
1265 toggle_counter_sig_15 <= TOGGLE_COUNTER_SIG_73;
1266 toggle_counter_sig_16 <= TOGGLE_COUNTER_SIG_74;
1267 toggle_counter_sig_17 <= TOGGLE_COUNTER_SIG_75;
1268 toggle_counter_sig_18 <= TOGGLE_COUNTER_SIG_76;
1269 toggle_counter_sig_19 <= TOGGLE_COUNTER_SIG_77;
1270 toggle_counter_sig_20 <= TOGGLE_COUNTER_SIG_78;
1271 toggle_counter_sig_21 <= TOGGLE_COUNTER_SIG_79;
1272 toggle_counter_sig_22 <= TOGGLE_COUNTER_SIG_80;
1273 toggle_counter_sig_23 <= TOGGLE_COUNTER_SIG_81;
1274 toggle_counter_sig_24 <= TOGGLE_COUNTER_SIG_82;
1275 toggle_sig <= TOGGLE_SIG_83;
1276 end beh;
1277
1278 --
1279 library ieee, stratix;
1280 use ieee.std_logic_1164.all;
1281 use ieee.numeric_std.all;
1282 library synplify;
1283 use synplify.components.all;
1284 use stratix.stratix_components.all;
1285
1286 entity vga_driver is
1287 port(
1288 line_counter_sig_0 :  out std_logic;
1289 line_counter_sig_1 :  out std_logic;
1290 line_counter_sig_2 :  out std_logic;
1291 line_counter_sig_3 :  out std_logic;
1292 line_counter_sig_4 :  out std_logic;
1293 line_counter_sig_5 :  out std_logic;
1294 line_counter_sig_6 :  out std_logic;
1295 line_counter_sig_7 :  out std_logic;
1296 line_counter_sig_8 :  out std_logic;
1297 dly_counter_1 :  in std_logic;
1298 dly_counter_0 :  in std_logic;
1299 vsync_state_2 :  out std_logic;
1300 vsync_state_5 :  out std_logic;
1301 vsync_state_3 :  out std_logic;
1302 vsync_state_6 :  out std_logic;
1303 vsync_state_4 :  out std_logic;
1304 vsync_state_1 :  out std_logic;
1305 vsync_state_0 :  out std_logic;
1306 hsync_state_2 :  out std_logic;
1307 hsync_state_4 :  out std_logic;
1308 hsync_state_0 :  out std_logic;
1309 hsync_state_5 :  out std_logic;
1310 hsync_state_1 :  out std_logic;
1311 hsync_state_3 :  out std_logic;
1312 hsync_state_6 :  out std_logic;
1313 column_counter_sig_0 :  out std_logic;
1314 column_counter_sig_1 :  out std_logic;
1315 column_counter_sig_2 :  out std_logic;
1316 column_counter_sig_3 :  out std_logic;
1317 column_counter_sig_4 :  out std_logic;
1318 column_counter_sig_5 :  out std_logic;
1319 column_counter_sig_6 :  out std_logic;
1320 column_counter_sig_7 :  out std_logic;
1321 column_counter_sig_8 :  out std_logic;
1322 column_counter_sig_9 :  out std_logic;
1323 vsync_counter_9 :  out std_logic;
1324 vsync_counter_8 :  out std_logic;
1325 vsync_counter_7 :  out std_logic;
1326 vsync_counter_6 :  out std_logic;
1327 vsync_counter_5 :  out std_logic;
1328 vsync_counter_4 :  out std_logic;
1329 vsync_counter_3 :  out std_logic;
1330 vsync_counter_2 :  out std_logic;
1331 vsync_counter_1 :  out std_logic;
1332 vsync_counter_0 :  out std_logic;
1333 hsync_counter_9 :  out std_logic;
1334 hsync_counter_8 :  out std_logic;
1335 hsync_counter_7 :  out std_logic;
1336 hsync_counter_6 :  out std_logic;
1337 hsync_counter_5 :  out std_logic;
1338 hsync_counter_4 :  out std_logic;
1339 hsync_counter_3 :  out std_logic;
1340 hsync_counter_2 :  out std_logic;
1341 hsync_counter_1 :  out std_logic;
1342 hsync_counter_0 :  out std_logic;
1343 d_set_vsync_counter :  out std_logic;
1344 v_sync :  out std_logic;
1345 h_sync :  out std_logic;
1346 h_enable_sig :  out std_logic;
1347 v_enable_sig :  out std_logic;
1348 reset_pin_c :  in std_logic;
1349 un6_dly_counter_0_x :  out std_logic;
1350 d_set_hsync_counter :  out std_logic;
1351 clk_pin_c :  in std_logic);
1352 end vga_driver;
1353
1354 architecture beh of vga_driver is
1355 signal devclrn : std_logic := '1';
1356 signal devpor : std_logic := '1';
1357 signal devoe : std_logic := '0';
1358 signal HSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
1359 signal VSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
1360 signal UN2_COLUMN_COUNTER_NEXT_COMBOUT : std_logic_vector(9 downto 1);
1361 signal UN1_LINE_COUNTER_SIG_COMBOUT : std_logic_vector(9 downto 1);
1362 signal UN1_LINE_COUNTER_SIG_COUT : std_logic_vector(7 downto 1);
1363 signal UN1_LINE_COUNTER_SIG_A_COUT : std_logic_vector(1 to 1);
1364 signal UN2_COLUMN_COUNTER_NEXT_COUT : std_logic_vector(7 downto 0);
1365 signal HSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
1366 signal G_2_I : std_logic ;
1367 signal UN9_HSYNC_COUNTERLT9 : std_logic ;
1368 signal VSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
1369 signal G_16_I : std_logic ;
1370 signal UN9_VSYNC_COUNTERLT9 : std_logic ;
1371 signal UN10_COLUMN_COUNTER_SIGLTO9 : std_logic ;
1372 signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
1373 signal \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\ : std_logic ;
1374 signal UN6_DLY_COUNTER_0_X_56 : std_logic ;
1375 signal VSYNC_STATE_NEXT_2_SQMUXA : std_logic ;
1376 signal UN12_VSYNC_COUNTER_7 : std_logic ;
1377 signal UN13_VSYNC_COUNTER_4 : std_logic ;
1378 signal UN10_LINE_COUNTER_SIGLTO8 : std_logic ;
1379 signal LINE_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
1380 signal V_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
1381 signal H_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
1382 signal H_SYNC_1_0_0_0_G1 : std_logic ;
1383 signal V_SYNC_1_0_0_0_G1 : std_logic ;
1384 signal UN14_VSYNC_COUNTER_8 : std_logic ;
1385 signal \HSYNC_STATE_3_0_0_0__G0_0\ : std_logic ;
1386 signal UN10_HSYNC_COUNTER_3 : std_logic ;
1387 signal UN10_HSYNC_COUNTER_1 : std_logic ;
1388 signal UN10_HSYNC_COUNTER_4 : std_logic ;
1389 signal UN12_HSYNC_COUNTER : std_logic ;
1390 signal UN11_HSYNC_COUNTER_2 : std_logic ;
1391 signal UN11_HSYNC_COUNTER_3 : std_logic ;
1392 signal UN13_HSYNC_COUNTER : std_logic ;
1393 signal VSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
1394 signal VSYNC_STATE_NEXT_1_SQMUXA_3 : std_logic ;
1395 signal UN1_VSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
1396 signal HSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
1397 signal HSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
1398 signal UN1_HSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
1399 signal UN12_VSYNC_COUNTER_6 : std_logic ;
1400 signal UN15_VSYNC_COUNTER_4 : std_logic ;
1401 signal VSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
1402 signal UN10_LINE_COUNTER_SIGLTO5 : std_logic ;
1403 signal UN10_COLUMN_COUNTER_SIGLT6 : std_logic ;
1404 signal UN13_HSYNC_COUNTER_2 : std_logic ;
1405 signal UN13_HSYNC_COUNTER_7 : std_logic ;
1406 signal UN9_HSYNC_COUNTERLT9_3 : std_logic ;
1407 signal UN9_VSYNC_COUNTERLT9_5 : std_logic ;
1408 signal UN9_VSYNC_COUNTERLT9_6 : std_logic ;
1409 signal UN12_HSYNC_COUNTER_3 : std_logic ;
1410 signal UN12_HSYNC_COUNTER_4 : std_logic ;
1411 signal UN10_LINE_COUNTER_SIGLT4_2 : std_logic ;
1412 signal UN15_VSYNC_COUNTER_3 : std_logic ;
1413 signal UN13_VSYNC_COUNTER_3 : std_logic ;
1414 signal UN10_COLUMN_COUNTER_SIGLT6_4 : std_logic ;
1415 signal D_SET_HSYNC_COUNTER_57 : std_logic ;
1416 signal V_SYNC_54 : std_logic ;
1417 signal UN1_VSYNC_STATE_2_0 : std_logic ;
1418 signal H_SYNC_55 : std_logic ;
1419 signal UN1_HSYNC_STATE_3_0 : std_logic ;
1420 signal D_SET_VSYNC_COUNTER_53 : std_logic ;
1421 signal VCC : std_logic ;
1422 signal LINE_COUNTER_SIG_0_0 : std_logic ;
1423 signal LINE_COUNTER_SIG_1_0 : std_logic ;
1424 signal LINE_COUNTER_SIG_2_0 : std_logic ;
1425 signal LINE_COUNTER_SIG_3_0 : std_logic ;
1426 signal LINE_COUNTER_SIG_4_0 : std_logic ;
1427 signal LINE_COUNTER_SIG_5_0 : std_logic ;
1428 signal LINE_COUNTER_SIG_6_0 : std_logic ;
1429 signal LINE_COUNTER_SIG_7_0 : std_logic ;
1430 signal LINE_COUNTER_SIG_8_0 : std_logic ;
1431 signal VSYNC_STATE_9 : std_logic ;
1432 signal VSYNC_STATE_10 : std_logic ;
1433 signal VSYNC_STATE_11 : std_logic ;
1434 signal VSYNC_STATE_12 : std_logic ;
1435 signal VSYNC_STATE_13 : std_logic ;
1436 signal VSYNC_STATE_14 : std_logic ;
1437 signal VSYNC_STATE_15 : std_logic ;
1438 signal HSYNC_STATE_16 : std_logic ;
1439 signal HSYNC_STATE_17 : std_logic ;
1440 signal HSYNC_STATE_18 : std_logic ;
1441 signal HSYNC_STATE_19 : std_logic ;
1442 signal HSYNC_STATE_20 : std_logic ;
1443 signal HSYNC_STATE_21 : std_logic ;
1444 signal HSYNC_STATE_22 : std_logic ;
1445 signal COLUMN_COUNTER_SIG_23 : std_logic ;
1446 signal COLUMN_COUNTER_SIG_24 : std_logic ;
1447 signal COLUMN_COUNTER_SIG_25 : std_logic ;
1448 signal COLUMN_COUNTER_SIG_26 : std_logic ;
1449 signal COLUMN_COUNTER_SIG_27 : std_logic ;
1450 signal COLUMN_COUNTER_SIG_28 : std_logic ;
1451 signal COLUMN_COUNTER_SIG_29 : std_logic ;
1452 signal COLUMN_COUNTER_SIG_30 : std_logic ;
1453 signal COLUMN_COUNTER_SIG_31 : std_logic ;
1454 signal COLUMN_COUNTER_SIG_32 : std_logic ;
1455 signal VSYNC_COUNTER_33 : std_logic ;
1456 signal VSYNC_COUNTER_34 : std_logic ;
1457 signal VSYNC_COUNTER_35 : std_logic ;
1458 signal VSYNC_COUNTER_36 : std_logic ;
1459 signal VSYNC_COUNTER_37 : std_logic ;
1460 signal VSYNC_COUNTER_38 : std_logic ;
1461 signal VSYNC_COUNTER_39 : std_logic ;
1462 signal VSYNC_COUNTER_40 : std_logic ;
1463 signal VSYNC_COUNTER_41 : std_logic ;
1464 signal VSYNC_COUNTER_42 : std_logic ;
1465 signal HSYNC_COUNTER_43 : std_logic ;
1466 signal HSYNC_COUNTER_44 : std_logic ;
1467 signal HSYNC_COUNTER_45 : std_logic ;
1468 signal HSYNC_COUNTER_46 : std_logic ;
1469 signal HSYNC_COUNTER_47 : std_logic ;
1470 signal HSYNC_COUNTER_48 : std_logic ;
1471 signal HSYNC_COUNTER_49 : std_logic ;
1472 signal HSYNC_COUNTER_50 : std_logic ;
1473 signal HSYNC_COUNTER_51 : std_logic ;
1474 signal HSYNC_COUNTER_52 : std_logic ;
1475 signal GND : std_logic ;
1476 signal LINE_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
1477 signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
1478 signal G_16_I_I : std_logic ;
1479 signal UN9_VSYNC_COUNTERLT9_I : std_logic ;
1480 signal G_2_I_I : std_logic ;
1481 signal UN9_HSYNC_COUNTERLT9_I : std_logic ;
1482 begin
1483 \HSYNC_COUNTER_0_\: stratix_lcell generic map (
1484     operation_mode => "arithmetic",
1485     output_mode => "reg_and_comb",
1486     synch_mode => "on",
1487      sum_lutc_input => "datac",
1488     lut_mask => "55aa")
1489 port map (
1490 regout => HSYNC_COUNTER_52,
1491 cout => HSYNC_COUNTER_COUT(0),
1492 clk => clk_pin_c,
1493 dataa => HSYNC_COUNTER_52,
1494 datab => VCC,
1495 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1496 sclr => G_2_I_I,
1497 sload => UN9_HSYNC_COUNTERLT9_I,
1498         devpor => devpor,
1499         devclrn => devclrn,
1500         datad => VCC,
1501         aclr => GND,
1502         ena => VCC,
1503         cin => GND,
1504         inverta => GND,
1505         aload => GND);
1506 \HSYNC_COUNTER_1_\: stratix_lcell generic map (
1507     operation_mode => "arithmetic",
1508     output_mode => "reg_and_comb",
1509     synch_mode => "on",
1510      sum_lutc_input => "cin",
1511      cin_used => "true",
1512     lut_mask => "5aa0")
1513 port map (
1514 regout => HSYNC_COUNTER_51,
1515 cout => HSYNC_COUNTER_COUT(1),
1516 clk => clk_pin_c,
1517 dataa => HSYNC_COUNTER_51,
1518 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1519 sclr => G_2_I_I,
1520 sload => UN9_HSYNC_COUNTERLT9_I,
1521 cin => HSYNC_COUNTER_COUT(0),
1522         devpor => devpor,
1523         devclrn => devclrn,
1524         datab => VCC,
1525         datad => VCC,
1526         aclr => GND,
1527         ena => VCC,
1528         inverta => GND,
1529         aload => GND);
1530 \HSYNC_COUNTER_2_\: stratix_lcell generic map (
1531     operation_mode => "arithmetic",
1532     output_mode => "reg_and_comb",
1533     synch_mode => "on",
1534      sum_lutc_input => "cin",
1535      cin_used => "true",
1536     lut_mask => "5aa0")
1537 port map (
1538 regout => HSYNC_COUNTER_50,
1539 cout => HSYNC_COUNTER_COUT(2),
1540 clk => clk_pin_c,
1541 dataa => HSYNC_COUNTER_50,
1542 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1543 sclr => G_2_I_I,
1544 sload => UN9_HSYNC_COUNTERLT9_I,
1545 cin => HSYNC_COUNTER_COUT(1),
1546         devpor => devpor,
1547         devclrn => devclrn,
1548         datab => VCC,
1549         datad => VCC,
1550         aclr => GND,
1551         ena => VCC,
1552         inverta => GND,
1553         aload => GND);
1554 \HSYNC_COUNTER_3_\: stratix_lcell generic map (
1555     operation_mode => "arithmetic",
1556     output_mode => "reg_and_comb",
1557     synch_mode => "on",
1558      sum_lutc_input => "cin",
1559      cin_used => "true",
1560     lut_mask => "5aa0")
1561 port map (
1562 regout => HSYNC_COUNTER_49,
1563 cout => HSYNC_COUNTER_COUT(3),
1564 clk => clk_pin_c,
1565 dataa => HSYNC_COUNTER_49,
1566 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1567 sclr => G_2_I_I,
1568 sload => UN9_HSYNC_COUNTERLT9_I,
1569 cin => HSYNC_COUNTER_COUT(2),
1570         devpor => devpor,
1571         devclrn => devclrn,
1572         datab => VCC,
1573         datad => VCC,
1574         aclr => GND,
1575         ena => VCC,
1576         inverta => GND,
1577         aload => GND);
1578 \HSYNC_COUNTER_4_\: stratix_lcell generic map (
1579     operation_mode => "arithmetic",
1580     output_mode => "reg_and_comb",
1581     synch_mode => "on",
1582      sum_lutc_input => "cin",
1583      cin_used => "true",
1584     lut_mask => "5aa0")
1585 port map (
1586 regout => HSYNC_COUNTER_48,
1587 cout => HSYNC_COUNTER_COUT(4),
1588 clk => clk_pin_c,
1589 dataa => HSYNC_COUNTER_48,
1590 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1591 sclr => G_2_I_I,
1592 sload => UN9_HSYNC_COUNTERLT9_I,
1593 cin => HSYNC_COUNTER_COUT(3),
1594         devpor => devpor,
1595         devclrn => devclrn,
1596         datab => VCC,
1597         datad => VCC,
1598         aclr => GND,
1599         ena => VCC,
1600         inverta => GND,
1601         aload => GND);
1602 \HSYNC_COUNTER_5_\: stratix_lcell generic map (
1603     operation_mode => "arithmetic",
1604     output_mode => "reg_and_comb",
1605     synch_mode => "on",
1606      sum_lutc_input => "cin",
1607      cin_used => "true",
1608     lut_mask => "5aa0")
1609 port map (
1610 regout => HSYNC_COUNTER_47,
1611 cout => HSYNC_COUNTER_COUT(5),
1612 clk => clk_pin_c,
1613 dataa => HSYNC_COUNTER_47,
1614 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1615 sclr => G_2_I_I,
1616 sload => UN9_HSYNC_COUNTERLT9_I,
1617 cin => HSYNC_COUNTER_COUT(4),
1618         devpor => devpor,
1619         devclrn => devclrn,
1620         datab => VCC,
1621         datad => VCC,
1622         aclr => GND,
1623         ena => VCC,
1624         inverta => GND,
1625         aload => GND);
1626 \HSYNC_COUNTER_6_\: stratix_lcell generic map (
1627     operation_mode => "arithmetic",
1628     output_mode => "reg_and_comb",
1629     synch_mode => "on",
1630      sum_lutc_input => "cin",
1631      cin_used => "true",
1632     lut_mask => "5aa0")
1633 port map (
1634 regout => HSYNC_COUNTER_46,
1635 cout => HSYNC_COUNTER_COUT(6),
1636 clk => clk_pin_c,
1637 dataa => HSYNC_COUNTER_46,
1638 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1639 sclr => G_2_I_I,
1640 sload => UN9_HSYNC_COUNTERLT9_I,
1641 cin => HSYNC_COUNTER_COUT(5),
1642         devpor => devpor,
1643         devclrn => devclrn,
1644         datab => VCC,
1645         datad => VCC,
1646         aclr => GND,
1647         ena => VCC,
1648         inverta => GND,
1649         aload => GND);
1650 \HSYNC_COUNTER_7_\: stratix_lcell generic map (
1651     operation_mode => "arithmetic",
1652     output_mode => "reg_and_comb",
1653     synch_mode => "on",
1654      sum_lutc_input => "cin",
1655      cin_used => "true",
1656     lut_mask => "5aa0")
1657 port map (
1658 regout => HSYNC_COUNTER_45,
1659 cout => HSYNC_COUNTER_COUT(7),
1660 clk => clk_pin_c,
1661 dataa => HSYNC_COUNTER_45,
1662 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1663 sclr => G_2_I_I,
1664 sload => UN9_HSYNC_COUNTERLT9_I,
1665 cin => HSYNC_COUNTER_COUT(6),
1666         devpor => devpor,
1667         devclrn => devclrn,
1668         datab => VCC,
1669         datad => VCC,
1670         aclr => GND,
1671         ena => VCC,
1672         inverta => GND,
1673         aload => GND);
1674 \HSYNC_COUNTER_8_\: stratix_lcell generic map (
1675     operation_mode => "arithmetic",
1676     output_mode => "reg_and_comb",
1677     synch_mode => "on",
1678      sum_lutc_input => "cin",
1679      cin_used => "true",
1680     lut_mask => "5aa0")
1681 port map (
1682 regout => HSYNC_COUNTER_44,
1683 cout => HSYNC_COUNTER_COUT(8),
1684 clk => clk_pin_c,
1685 dataa => HSYNC_COUNTER_44,
1686 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1687 sclr => G_2_I_I,
1688 sload => UN9_HSYNC_COUNTERLT9_I,
1689 cin => HSYNC_COUNTER_COUT(7),
1690         devpor => devpor,
1691         devclrn => devclrn,
1692         datab => VCC,
1693         datad => VCC,
1694         aclr => GND,
1695         ena => VCC,
1696         inverta => GND,
1697         aload => GND);
1698 \HSYNC_COUNTER_9_\: stratix_lcell generic map (
1699     operation_mode => "normal",
1700     output_mode => "reg_only",
1701     synch_mode => "on",
1702      sum_lutc_input => "cin",
1703      cin_used => "true",
1704     lut_mask => "5a5a")
1705 port map (
1706 regout => HSYNC_COUNTER_43,
1707 clk => clk_pin_c,
1708 dataa => HSYNC_COUNTER_43,
1709 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1710 sclr => G_2_I_I,
1711 sload => UN9_HSYNC_COUNTERLT9_I,
1712 cin => HSYNC_COUNTER_COUT(8),
1713         devpor => devpor,
1714         devclrn => devclrn,
1715         datab => VCC,
1716         datad => VCC,
1717         aclr => GND,
1718         ena => VCC,
1719         inverta => GND,
1720         aload => GND);
1721 \VSYNC_COUNTER_0_\: stratix_lcell generic map (
1722     operation_mode => "arithmetic",
1723     output_mode => "reg_and_comb",
1724     synch_mode => "on",
1725      sum_lutc_input => "datac",
1726     lut_mask => "6688")
1727 port map (
1728 regout => VSYNC_COUNTER_42,
1729 cout => VSYNC_COUNTER_COUT(0),
1730 clk => clk_pin_c,
1731 dataa => VSYNC_COUNTER_42,
1732 datab => D_SET_HSYNC_COUNTER_57,
1733 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1734 sclr => G_16_I_I,
1735 sload => UN9_VSYNC_COUNTERLT9_I,
1736         devpor => devpor,
1737         devclrn => devclrn,
1738         datad => VCC,
1739         aclr => GND,
1740         ena => VCC,
1741         cin => GND,
1742         inverta => GND,
1743         aload => GND);
1744 \VSYNC_COUNTER_1_\: stratix_lcell generic map (
1745     operation_mode => "arithmetic",
1746     output_mode => "reg_and_comb",
1747     synch_mode => "on",
1748      sum_lutc_input => "cin",
1749      cin_used => "true",
1750     lut_mask => "5aa0")
1751 port map (
1752 regout => VSYNC_COUNTER_41,
1753 cout => VSYNC_COUNTER_COUT(1),
1754 clk => clk_pin_c,
1755 dataa => VSYNC_COUNTER_41,
1756 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1757 sclr => G_16_I_I,
1758 sload => UN9_VSYNC_COUNTERLT9_I,
1759 cin => VSYNC_COUNTER_COUT(0),
1760         devpor => devpor,
1761         devclrn => devclrn,
1762         datab => VCC,
1763         datad => VCC,
1764         aclr => GND,
1765         ena => VCC,
1766         inverta => GND,
1767         aload => GND);
1768 \VSYNC_COUNTER_2_\: stratix_lcell generic map (
1769     operation_mode => "arithmetic",
1770     output_mode => "reg_and_comb",
1771     synch_mode => "on",
1772      sum_lutc_input => "cin",
1773      cin_used => "true",
1774     lut_mask => "5aa0")
1775 port map (
1776 regout => VSYNC_COUNTER_40,
1777 cout => VSYNC_COUNTER_COUT(2),
1778 clk => clk_pin_c,
1779 dataa => VSYNC_COUNTER_40,
1780 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1781 sclr => G_16_I_I,
1782 sload => UN9_VSYNC_COUNTERLT9_I,
1783 cin => VSYNC_COUNTER_COUT(1),
1784         devpor => devpor,
1785         devclrn => devclrn,
1786         datab => VCC,
1787         datad => VCC,
1788         aclr => GND,
1789         ena => VCC,
1790         inverta => GND,
1791         aload => GND);
1792 \VSYNC_COUNTER_3_\: stratix_lcell generic map (
1793     operation_mode => "arithmetic",
1794     output_mode => "reg_and_comb",
1795     synch_mode => "on",
1796      sum_lutc_input => "cin",
1797      cin_used => "true",
1798     lut_mask => "5aa0")
1799 port map (
1800 regout => VSYNC_COUNTER_39,
1801 cout => VSYNC_COUNTER_COUT(3),
1802 clk => clk_pin_c,
1803 dataa => VSYNC_COUNTER_39,
1804 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1805 sclr => G_16_I_I,
1806 sload => UN9_VSYNC_COUNTERLT9_I,
1807 cin => VSYNC_COUNTER_COUT(2),
1808         devpor => devpor,
1809         devclrn => devclrn,
1810         datab => VCC,
1811         datad => VCC,
1812         aclr => GND,
1813         ena => VCC,
1814         inverta => GND,
1815         aload => GND);
1816 \VSYNC_COUNTER_4_\: stratix_lcell generic map (
1817     operation_mode => "arithmetic",
1818     output_mode => "reg_and_comb",
1819     synch_mode => "on",
1820      sum_lutc_input => "cin",
1821      cin_used => "true",
1822     lut_mask => "5aa0")
1823 port map (
1824 regout => VSYNC_COUNTER_38,
1825 cout => VSYNC_COUNTER_COUT(4),
1826 clk => clk_pin_c,
1827 dataa => VSYNC_COUNTER_38,
1828 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1829 sclr => G_16_I_I,
1830 sload => UN9_VSYNC_COUNTERLT9_I,
1831 cin => VSYNC_COUNTER_COUT(3),
1832         devpor => devpor,
1833         devclrn => devclrn,
1834         datab => VCC,
1835         datad => VCC,
1836         aclr => GND,
1837         ena => VCC,
1838         inverta => GND,
1839         aload => GND);
1840 \VSYNC_COUNTER_5_\: stratix_lcell generic map (
1841     operation_mode => "arithmetic",
1842     output_mode => "reg_and_comb",
1843     synch_mode => "on",
1844      sum_lutc_input => "cin",
1845      cin_used => "true",
1846     lut_mask => "5aa0")
1847 port map (
1848 regout => VSYNC_COUNTER_37,
1849 cout => VSYNC_COUNTER_COUT(5),
1850 clk => clk_pin_c,
1851 dataa => VSYNC_COUNTER_37,
1852 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1853 sclr => G_16_I_I,
1854 sload => UN9_VSYNC_COUNTERLT9_I,
1855 cin => VSYNC_COUNTER_COUT(4),
1856         devpor => devpor,
1857         devclrn => devclrn,
1858         datab => VCC,
1859         datad => VCC,
1860         aclr => GND,
1861         ena => VCC,
1862         inverta => GND,
1863         aload => GND);
1864 \VSYNC_COUNTER_6_\: stratix_lcell generic map (
1865     operation_mode => "arithmetic",
1866     output_mode => "reg_and_comb",
1867     synch_mode => "on",
1868      sum_lutc_input => "cin",
1869      cin_used => "true",
1870     lut_mask => "5aa0")
1871 port map (
1872 regout => VSYNC_COUNTER_36,
1873 cout => VSYNC_COUNTER_COUT(6),
1874 clk => clk_pin_c,
1875 dataa => VSYNC_COUNTER_36,
1876 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1877 sclr => G_16_I_I,
1878 sload => UN9_VSYNC_COUNTERLT9_I,
1879 cin => VSYNC_COUNTER_COUT(5),
1880         devpor => devpor,
1881         devclrn => devclrn,
1882         datab => VCC,
1883         datad => VCC,
1884         aclr => GND,
1885         ena => VCC,
1886         inverta => GND,
1887         aload => GND);
1888 \VSYNC_COUNTER_7_\: stratix_lcell generic map (
1889     operation_mode => "arithmetic",
1890     output_mode => "reg_and_comb",
1891     synch_mode => "on",
1892      sum_lutc_input => "cin",
1893      cin_used => "true",
1894     lut_mask => "5aa0")
1895 port map (
1896 regout => VSYNC_COUNTER_35,
1897 cout => VSYNC_COUNTER_COUT(7),
1898 clk => clk_pin_c,
1899 dataa => VSYNC_COUNTER_35,
1900 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1901 sclr => G_16_I_I,
1902 sload => UN9_VSYNC_COUNTERLT9_I,
1903 cin => VSYNC_COUNTER_COUT(6),
1904         devpor => devpor,
1905         devclrn => devclrn,
1906         datab => VCC,
1907         datad => VCC,
1908         aclr => GND,
1909         ena => VCC,
1910         inverta => GND,
1911         aload => GND);
1912 \VSYNC_COUNTER_8_\: stratix_lcell generic map (
1913     operation_mode => "arithmetic",
1914     output_mode => "reg_and_comb",
1915     synch_mode => "on",
1916      sum_lutc_input => "cin",
1917      cin_used => "true",
1918     lut_mask => "5aa0")
1919 port map (
1920 regout => VSYNC_COUNTER_34,
1921 cout => VSYNC_COUNTER_COUT(8),
1922 clk => clk_pin_c,
1923 dataa => VSYNC_COUNTER_34,
1924 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1925 sclr => G_16_I_I,
1926 sload => UN9_VSYNC_COUNTERLT9_I,
1927 cin => VSYNC_COUNTER_COUT(7),
1928         devpor => devpor,
1929         devclrn => devclrn,
1930         datab => VCC,
1931         datad => VCC,
1932         aclr => GND,
1933         ena => VCC,
1934         inverta => GND,
1935         aload => GND);
1936 \VSYNC_COUNTER_9_\: stratix_lcell generic map (
1937     operation_mode => "normal",
1938     output_mode => "reg_only",
1939     synch_mode => "on",
1940      sum_lutc_input => "cin",
1941      cin_used => "true",
1942     lut_mask => "5a5a")
1943 port map (
1944 regout => VSYNC_COUNTER_33,
1945 clk => clk_pin_c,
1946 dataa => VSYNC_COUNTER_33,
1947 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1948 sclr => G_16_I_I,
1949 sload => UN9_VSYNC_COUNTERLT9_I,
1950 cin => VSYNC_COUNTER_COUT(8),
1951         devpor => devpor,
1952         devclrn => devclrn,
1953         datab => VCC,
1954         datad => VCC,
1955         aclr => GND,
1956         ena => VCC,
1957         inverta => GND,
1958         aload => GND);
1959 \COLUMN_COUNTER_SIG_9_\: stratix_lcell generic map (
1960     operation_mode => "normal",
1961     output_mode => "reg_only",
1962     synch_mode => "on",
1963      sum_lutc_input => "datac",
1964     lut_mask => "bbbb")
1965 port map (
1966 regout => COLUMN_COUNTER_SIG_32,
1967 clk => clk_pin_c,
1968 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
1969 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1970 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1971         devpor => devpor,
1972         devclrn => devclrn,
1973         datac => VCC,
1974         datad => VCC,
1975         aclr => GND,
1976         sload => GND,
1977         ena => VCC,
1978         cin => GND,
1979         inverta => GND,
1980         aload => GND);
1981 \COLUMN_COUNTER_SIG_8_\: stratix_lcell generic map (
1982     operation_mode => "normal",
1983     output_mode => "reg_only",
1984     synch_mode => "off",
1985      sum_lutc_input => "datac",
1986     lut_mask => "8080")
1987 port map (
1988 regout => COLUMN_COUNTER_SIG_31,
1989 clk => clk_pin_c,
1990 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
1991 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1992 datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
1993         devpor => devpor,
1994         devclrn => devclrn,
1995         datad => VCC,
1996         aclr => GND,
1997         sclr => GND,
1998         sload => GND,
1999         ena => VCC,
2000         cin => GND,
2001         inverta => GND,
2002         aload => GND);
2003 \COLUMN_COUNTER_SIG_7_\: stratix_lcell generic map (
2004     operation_mode => "normal",
2005     output_mode => "reg_only",
2006     synch_mode => "off",
2007      sum_lutc_input => "datac",
2008     lut_mask => "8080")
2009 port map (
2010 regout => COLUMN_COUNTER_SIG_30,
2011 clk => clk_pin_c,
2012 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
2013 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2014 datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
2015         devpor => devpor,
2016         devclrn => devclrn,
2017         datad => VCC,
2018         aclr => GND,
2019         sclr => GND,
2020         sload => GND,
2021         ena => VCC,
2022         cin => GND,
2023         inverta => GND,
2024         aload => GND);
2025 \COLUMN_COUNTER_SIG_6_\: stratix_lcell generic map (
2026     operation_mode => "normal",
2027     output_mode => "reg_only",
2028     synch_mode => "on",
2029      sum_lutc_input => "datac",
2030     lut_mask => "bbbb")
2031 port map (
2032 regout => COLUMN_COUNTER_SIG_29,
2033 clk => clk_pin_c,
2034 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
2035 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2036 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2037         devpor => devpor,
2038         devclrn => devclrn,
2039         datac => VCC,
2040         datad => VCC,
2041         aclr => GND,
2042         sload => GND,
2043         ena => VCC,
2044         cin => GND,
2045         inverta => GND,
2046         aload => GND);
2047 \COLUMN_COUNTER_SIG_5_\: stratix_lcell generic map (
2048     operation_mode => "normal",
2049     output_mode => "reg_only",
2050     synch_mode => "on",
2051      sum_lutc_input => "datac",
2052     lut_mask => "bbbb")
2053 port map (
2054 regout => COLUMN_COUNTER_SIG_28,
2055 clk => clk_pin_c,
2056 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
2057 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2058 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2059         devpor => devpor,
2060         devclrn => devclrn,
2061         datac => VCC,
2062         datad => VCC,
2063         aclr => GND,
2064         sload => GND,
2065         ena => VCC,
2066         cin => GND,
2067         inverta => GND,
2068         aload => GND);
2069 \COLUMN_COUNTER_SIG_4_\: stratix_lcell generic map (
2070     operation_mode => "normal",
2071     output_mode => "reg_only",
2072     synch_mode => "on",
2073      sum_lutc_input => "datac",
2074     lut_mask => "bbbb")
2075 port map (
2076 regout => COLUMN_COUNTER_SIG_27,
2077 clk => clk_pin_c,
2078 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
2079 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2080 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2081         devpor => devpor,
2082         devclrn => devclrn,
2083         datac => VCC,
2084         datad => VCC,
2085         aclr => GND,
2086         sload => GND,
2087         ena => VCC,
2088         cin => GND,
2089         inverta => GND,
2090         aload => GND);
2091 \COLUMN_COUNTER_SIG_3_\: stratix_lcell generic map (
2092     operation_mode => "normal",
2093     output_mode => "reg_only",
2094     synch_mode => "on",
2095      sum_lutc_input => "datac",
2096     lut_mask => "bbbb")
2097 port map (
2098 regout => COLUMN_COUNTER_SIG_26,
2099 clk => clk_pin_c,
2100 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
2101 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2102 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2103         devpor => devpor,
2104         devclrn => devclrn,
2105         datac => VCC,
2106         datad => VCC,
2107         aclr => GND,
2108         sload => GND,
2109         ena => VCC,
2110         cin => GND,
2111         inverta => GND,
2112         aload => GND);
2113 \COLUMN_COUNTER_SIG_2_\: stratix_lcell generic map (
2114     operation_mode => "normal",
2115     output_mode => "reg_only",
2116     synch_mode => "on",
2117      sum_lutc_input => "datac",
2118     lut_mask => "bbbb")
2119 port map (
2120 regout => COLUMN_COUNTER_SIG_25,
2121 clk => clk_pin_c,
2122 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
2123 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2124 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2125         devpor => devpor,
2126         devclrn => devclrn,
2127         datac => VCC,
2128         datad => VCC,
2129         aclr => GND,
2130         sload => GND,
2131         ena => VCC,
2132         cin => GND,
2133         inverta => GND,
2134         aload => GND);
2135 \COLUMN_COUNTER_SIG_1_\: stratix_lcell generic map (
2136     operation_mode => "normal",
2137     output_mode => "reg_only",
2138     synch_mode => "on",
2139      sum_lutc_input => "datac",
2140     lut_mask => "bbbb")
2141 port map (
2142 regout => COLUMN_COUNTER_SIG_24,
2143 clk => clk_pin_c,
2144 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
2145 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2146 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2147         devpor => devpor,
2148         devclrn => devclrn,
2149         datac => VCC,
2150         datad => VCC,
2151         aclr => GND,
2152         sload => GND,
2153         ena => VCC,
2154         cin => GND,
2155         inverta => GND,
2156         aload => GND);
2157 \COLUMN_COUNTER_SIG_0_\: stratix_lcell generic map (
2158     operation_mode => "normal",
2159     output_mode => "reg_only",
2160     synch_mode => "on",
2161      sum_lutc_input => "datac",
2162     lut_mask => "7777")
2163 port map (
2164 regout => COLUMN_COUNTER_SIG_23,
2165 clk => clk_pin_c,
2166 dataa => COLUMN_COUNTER_SIG_23,
2167 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2168 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2169         devpor => devpor,
2170         devclrn => devclrn,
2171         datac => VCC,
2172         datad => VCC,
2173         aclr => GND,
2174         sload => GND,
2175         ena => VCC,
2176         cin => GND,
2177         inverta => GND,
2178         aload => GND);
2179 \HSYNC_STATE_6_\: stratix_lcell generic map (
2180     operation_mode => "normal",
2181     output_mode => "reg_only",
2182     synch_mode => "off",
2183      sum_lutc_input => "datac",
2184     lut_mask => "ff00")
2185 port map (
2186 regout => HSYNC_STATE_22,
2187 clk => clk_pin_c,
2188 datad => UN6_DLY_COUNTER_0_X_56,
2189         devpor => devpor,
2190         devclrn => devclrn,
2191         dataa => VCC,
2192         datab => VCC,
2193         datac => VCC,
2194         aclr => GND,
2195         sclr => GND,
2196         sload => GND,
2197         ena => VCC,
2198         cin => GND,
2199         inverta => GND,
2200         aload => GND);
2201 \VSYNC_STATE_0_\: stratix_lcell generic map (
2202     operation_mode => "normal",
2203     output_mode => "reg_only",
2204     synch_mode => "off",
2205      sum_lutc_input => "datac",
2206     lut_mask => "0cae")
2207 port map (
2208 regout => VSYNC_STATE_15,
2209 clk => clk_pin_c,
2210 dataa => VSYNC_STATE_15,
2211 datab => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
2212 datac => UN6_DLY_COUNTER_0_X_56,
2213 datad => VSYNC_STATE_NEXT_2_SQMUXA,
2214         devpor => devpor,
2215         devclrn => devclrn,
2216         aclr => GND,
2217         sclr => GND,
2218         sload => GND,
2219         ena => VCC,
2220         cin => GND,
2221         inverta => GND,
2222         aload => GND);
2223 \VSYNC_STATE_1_\: stratix_lcell generic map (
2224     operation_mode => "normal",
2225     output_mode => "reg_only",
2226     synch_mode => "off",
2227      sum_lutc_input => "datac",
2228     lut_mask => "0080")
2229 port map (
2230 regout => VSYNC_STATE_14,
2231 clk => clk_pin_c,
2232 dataa => VSYNC_STATE_13,
2233 datab => UN12_VSYNC_COUNTER_7,
2234 datac => UN13_VSYNC_COUNTER_4,
2235 datad => UN6_DLY_COUNTER_0_X_56,
2236         devpor => devpor,
2237         devclrn => devclrn,
2238         aclr => GND,
2239         sclr => GND,
2240         sload => GND,
2241         ena => VCC,
2242         cin => GND,
2243         inverta => GND,
2244         aload => GND);
2245 \VSYNC_STATE_6_\: stratix_lcell generic map (
2246     operation_mode => "normal",
2247     output_mode => "reg_and_comb",
2248     synch_mode => "off",
2249      sum_lutc_input => "datac",
2250     lut_mask => "7f7f")
2251 port map (
2252 combout => UN6_DLY_COUNTER_0_X_56,
2253 regout => VSYNC_STATE_12,
2254 clk => clk_pin_c,
2255 dataa => reset_pin_c,
2256 datab => dly_counter_0,
2257 datac => dly_counter_1,
2258         devpor => devpor,
2259         devclrn => devclrn,
2260         datad => VCC,
2261         aclr => GND,
2262         sclr => GND,
2263         sload => GND,
2264         ena => VCC,
2265         cin => GND,
2266         inverta => GND,
2267         aload => GND);
2268 \LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
2269     operation_mode => "normal",
2270     output_mode => "reg_only",
2271     synch_mode => "on",
2272      sum_lutc_input => "datac",
2273     lut_mask => "dddd")
2274 port map (
2275 regout => LINE_COUNTER_SIG_8_0,
2276 clk => clk_pin_c,
2277 dataa => UN10_LINE_COUNTER_SIGLTO8,
2278 datab => UN1_LINE_COUNTER_SIG_COMBOUT(9),
2279 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2280         devpor => devpor,
2281         devclrn => devclrn,
2282         datac => VCC,
2283         datad => VCC,
2284         aclr => GND,
2285         sload => GND,
2286         ena => VCC,
2287         cin => GND,
2288         inverta => GND,
2289         aload => GND);
2290 \LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
2291     operation_mode => "normal",
2292     output_mode => "reg_only",
2293     synch_mode => "on",
2294      sum_lutc_input => "datac",
2295     lut_mask => "dddd")
2296 port map (
2297 regout => LINE_COUNTER_SIG_7_0,
2298 clk => clk_pin_c,
2299 dataa => UN10_LINE_COUNTER_SIGLTO8,
2300 datab => UN1_LINE_COUNTER_SIG_COMBOUT(8),
2301 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2302         devpor => devpor,
2303         devclrn => devclrn,
2304         datac => VCC,
2305         datad => VCC,
2306         aclr => GND,
2307         sload => GND,
2308         ena => VCC,
2309         cin => GND,
2310         inverta => GND,
2311         aload => GND);
2312 \LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
2313     operation_mode => "normal",
2314     output_mode => "reg_only",
2315     synch_mode => "on",
2316      sum_lutc_input => "datac",
2317     lut_mask => "dddd")
2318 port map (
2319 regout => LINE_COUNTER_SIG_6_0,
2320 clk => clk_pin_c,
2321 dataa => UN10_LINE_COUNTER_SIGLTO8,
2322 datab => UN1_LINE_COUNTER_SIG_COMBOUT(7),
2323 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2324         devpor => devpor,
2325         devclrn => devclrn,
2326         datac => VCC,
2327         datad => VCC,
2328         aclr => GND,
2329         sload => GND,
2330         ena => VCC,
2331         cin => GND,
2332         inverta => GND,
2333         aload => GND);
2334 \LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
2335     operation_mode => "normal",
2336     output_mode => "reg_only",
2337     synch_mode => "off",
2338      sum_lutc_input => "datac",
2339     lut_mask => "8080")
2340 port map (
2341 regout => LINE_COUNTER_SIG_5_0,
2342 clk => clk_pin_c,
2343 dataa => UN10_LINE_COUNTER_SIGLTO8,
2344 datab => UN1_LINE_COUNTER_SIG_COMBOUT(6),
2345 datac => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
2346         devpor => devpor,
2347         devclrn => devclrn,
2348         datad => VCC,
2349         aclr => GND,
2350         sclr => GND,
2351         sload => GND,
2352         ena => VCC,
2353         cin => GND,
2354         inverta => GND,
2355         aload => GND);
2356 \LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
2357     operation_mode => "normal",
2358     output_mode => "reg_only",
2359     synch_mode => "on",
2360      sum_lutc_input => "datac",
2361     lut_mask => "dddd")
2362 port map (
2363 regout => LINE_COUNTER_SIG_4_0,
2364 clk => clk_pin_c,
2365 dataa => UN10_LINE_COUNTER_SIGLTO8,
2366 datab => UN1_LINE_COUNTER_SIG_COMBOUT(5),
2367 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2368         devpor => devpor,
2369         devclrn => devclrn,
2370         datac => VCC,
2371         datad => VCC,
2372         aclr => GND,
2373         sload => GND,
2374         ena => VCC,
2375         cin => GND,
2376         inverta => GND,
2377         aload => GND);
2378 \LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
2379     operation_mode => "normal",
2380     output_mode => "reg_only",
2381     synch_mode => "on",
2382      sum_lutc_input => "datac",
2383     lut_mask => "dddd")
2384 port map (
2385 regout => LINE_COUNTER_SIG_3_0,
2386 clk => clk_pin_c,
2387 dataa => UN10_LINE_COUNTER_SIGLTO8,
2388 datab => UN1_LINE_COUNTER_SIG_COMBOUT(4),
2389 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2390         devpor => devpor,
2391         devclrn => devclrn,
2392         datac => VCC,
2393         datad => VCC,
2394         aclr => GND,
2395         sload => GND,
2396         ena => VCC,
2397         cin => GND,
2398         inverta => GND,
2399         aload => GND);
2400 \LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
2401     operation_mode => "normal",
2402     output_mode => "reg_only",
2403     synch_mode => "on",
2404      sum_lutc_input => "datac",
2405     lut_mask => "dddd")
2406 port map (
2407 regout => LINE_COUNTER_SIG_2_0,
2408 clk => clk_pin_c,
2409 dataa => UN10_LINE_COUNTER_SIGLTO8,
2410 datab => UN1_LINE_COUNTER_SIG_COMBOUT(3),
2411 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2412         devpor => devpor,
2413         devclrn => devclrn,
2414         datac => VCC,
2415         datad => VCC,
2416         aclr => GND,
2417         sload => GND,
2418         ena => VCC,
2419         cin => GND,
2420         inverta => GND,
2421         aload => GND);
2422 \LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
2423     operation_mode => "normal",
2424     output_mode => "reg_only",
2425     synch_mode => "on",
2426      sum_lutc_input => "datac",
2427     lut_mask => "dddd")
2428 port map (
2429 regout => LINE_COUNTER_SIG_1_0,
2430 clk => clk_pin_c,
2431 dataa => UN10_LINE_COUNTER_SIGLTO8,
2432 datab => UN1_LINE_COUNTER_SIG_COMBOUT(2),
2433 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2434         devpor => devpor,
2435         devclrn => devclrn,
2436         datac => VCC,
2437         datad => VCC,
2438         aclr => GND,
2439         sload => GND,
2440         ena => VCC,
2441         cin => GND,
2442         inverta => GND,
2443         aload => GND);
2444 \LINE_COUNTER_SIG_0_\: stratix_lcell generic map (
2445     operation_mode => "normal",
2446     output_mode => "reg_only",
2447     synch_mode => "on",
2448      sum_lutc_input => "datac",
2449     lut_mask => "bbbb")
2450 port map (
2451 regout => LINE_COUNTER_SIG_0_0,
2452 clk => clk_pin_c,
2453 dataa => UN1_LINE_COUNTER_SIG_COMBOUT(1),
2454 datab => UN10_LINE_COUNTER_SIGLTO8,
2455 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2456         devpor => devpor,
2457         devclrn => devclrn,
2458         datac => VCC,
2459         datad => VCC,
2460         aclr => GND,
2461         sload => GND,
2462         ena => VCC,
2463         cin => GND,
2464         inverta => GND,
2465         aload => GND);
2466 V_ENABLE_SIG_Z283: stratix_lcell generic map (
2467     operation_mode => "normal",
2468     output_mode => "reg_only",
2469     synch_mode => "on",
2470      sum_lutc_input => "datac",
2471     lut_mask => "eeee")
2472 port map (
2473 regout => v_enable_sig,
2474 clk => clk_pin_c,
2475 dataa => HSYNC_STATE_21,
2476 datab => HSYNC_STATE_20,
2477 sclr => UN6_DLY_COUNTER_0_X_56,
2478 ena => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
2479         devpor => devpor,
2480         devclrn => devclrn,
2481         datac => VCC,
2482         datad => VCC,
2483         aclr => GND,
2484         sload => GND,
2485         cin => GND,
2486         inverta => GND,
2487         aload => GND);
2488 H_ENABLE_SIG_Z284: stratix_lcell generic map (
2489     operation_mode => "normal",
2490     output_mode => "reg_only",
2491     synch_mode => "on",
2492      sum_lutc_input => "datac",
2493     lut_mask => "eeee")
2494 port map (
2495 regout => h_enable_sig,
2496 clk => clk_pin_c,
2497 dataa => VSYNC_STATE_11,
2498 datab => VSYNC_STATE_14,
2499 sclr => UN6_DLY_COUNTER_0_X_56,
2500 ena => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
2501         devpor => devpor,
2502         devclrn => devclrn,
2503         datac => VCC,
2504         datad => VCC,
2505         aclr => GND,
2506         sload => GND,
2507         cin => GND,
2508         inverta => GND,
2509         aload => GND);
2510 H_SYNC_Z285: stratix_lcell generic map (
2511     operation_mode => "normal",
2512     output_mode => "reg_only",
2513     synch_mode => "off",
2514      sum_lutc_input => "datac",
2515     lut_mask => "ff7f")
2516 port map (
2517 regout => H_SYNC_55,
2518 clk => clk_pin_c,
2519 dataa => reset_pin_c,
2520 datab => dly_counter_0,
2521 datac => dly_counter_1,
2522 datad => H_SYNC_1_0_0_0_G1,
2523         devpor => devpor,
2524         devclrn => devclrn,
2525         aclr => GND,
2526         sclr => GND,
2527         sload => GND,
2528         ena => VCC,
2529         cin => GND,
2530         inverta => GND,
2531         aload => GND);
2532 V_SYNC_Z286: stratix_lcell generic map (
2533     operation_mode => "normal",
2534     output_mode => "reg_only",
2535     synch_mode => "off",
2536      sum_lutc_input => "datac",
2537     lut_mask => "ff7f")
2538 port map (
2539 regout => V_SYNC_54,
2540 clk => clk_pin_c,
2541 dataa => reset_pin_c,
2542 datab => dly_counter_0,
2543 datac => dly_counter_1,
2544 datad => V_SYNC_1_0_0_0_G1,
2545         devpor => devpor,
2546         devclrn => devclrn,
2547         aclr => GND,
2548         sclr => GND,
2549         sload => GND,
2550         ena => VCC,
2551         cin => GND,
2552         inverta => GND,
2553         aload => GND);
2554 \VSYNC_STATE_5_\: stratix_lcell generic map (
2555     operation_mode => "normal",
2556     output_mode => "reg_only",
2557     synch_mode => "on",
2558      sum_lutc_input => "datac",
2559     lut_mask => "eeee")
2560 port map (
2561 regout => VSYNC_STATE_10,
2562 clk => clk_pin_c,
2563 dataa => VSYNC_STATE_12,
2564 datab => VSYNC_STATE_15,
2565 sclr => UN6_DLY_COUNTER_0_X_56,
2566 ena => VSYNC_STATE_NEXT_2_SQMUXA,
2567         devpor => devpor,
2568         devclrn => devclrn,
2569         datac => VCC,
2570         datad => VCC,
2571         aclr => GND,
2572         sload => GND,
2573         cin => GND,
2574         inverta => GND,
2575         aload => GND);
2576 \VSYNC_STATE_4_\: stratix_lcell generic map (
2577     operation_mode => "normal",
2578     output_mode => "reg_only",
2579     synch_mode => "on",
2580      sum_lutc_input => "datac",
2581     lut_mask => "2000")
2582 port map (
2583 regout => VSYNC_STATE_13,
2584 clk => clk_pin_c,
2585 dataa => VSYNC_COUNTER_42,
2586 datab => VSYNC_COUNTER_33,
2587 datac => VSYNC_STATE_10,
2588 datad => UN14_VSYNC_COUNTER_8,
2589 sclr => UN6_DLY_COUNTER_0_X_56,
2590 ena => VSYNC_STATE_NEXT_2_SQMUXA,
2591         devpor => devpor,
2592         devclrn => devclrn,
2593         aclr => GND,
2594         sload => GND,
2595         cin => GND,
2596         inverta => GND,
2597         aload => GND);
2598 \VSYNC_STATE_3_\: stratix_lcell generic map (
2599     operation_mode => "normal",
2600     output_mode => "reg_only",
2601     synch_mode => "on",
2602      sum_lutc_input => "datac",
2603     lut_mask => "aaaa")
2604 port map (
2605 regout => VSYNC_STATE_11,
2606 clk => clk_pin_c,
2607 dataa => VSYNC_STATE_14,
2608 sclr => UN6_DLY_COUNTER_0_X_56,
2609 ena => VSYNC_STATE_NEXT_2_SQMUXA,
2610         devpor => devpor,
2611         devclrn => devclrn,
2612         datab => VCC,
2613         datac => VCC,
2614         datad => VCC,
2615         aclr => GND,
2616         sload => GND,
2617         cin => GND,
2618         inverta => GND,
2619         aload => GND);
2620 \VSYNC_STATE_2_\: stratix_lcell generic map (
2621     operation_mode => "normal",
2622     output_mode => "reg_only",
2623     synch_mode => "on",
2624      sum_lutc_input => "datac",
2625     lut_mask => "8000")
2626 port map (
2627 regout => VSYNC_STATE_9,
2628 clk => clk_pin_c,
2629 dataa => VSYNC_COUNTER_42,
2630 datab => VSYNC_COUNTER_33,
2631 datac => VSYNC_STATE_11,
2632 datad => UN14_VSYNC_COUNTER_8,
2633 sclr => UN6_DLY_COUNTER_0_X_56,
2634 ena => VSYNC_STATE_NEXT_2_SQMUXA,
2635         devpor => devpor,
2636         devclrn => devclrn,
2637         aclr => GND,
2638         sload => GND,
2639         cin => GND,
2640         inverta => GND,
2641         aload => GND);
2642 \HSYNC_STATE_5_\: stratix_lcell generic map (
2643     operation_mode => "normal",
2644     output_mode => "reg_only",
2645     synch_mode => "on",
2646      sum_lutc_input => "datac",
2647     lut_mask => "eeee")
2648 port map (
2649 regout => HSYNC_STATE_19,
2650 clk => clk_pin_c,
2651 dataa => HSYNC_STATE_22,
2652 datab => HSYNC_STATE_18,
2653 sclr => UN6_DLY_COUNTER_0_X_56,
2654 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2655         devpor => devpor,
2656         devclrn => devclrn,
2657         datac => VCC,
2658         datad => VCC,
2659         aclr => GND,
2660         sload => GND,
2661         cin => GND,
2662         inverta => GND,
2663         aload => GND);
2664 \HSYNC_STATE_4_\: stratix_lcell generic map (
2665     operation_mode => "normal",
2666     output_mode => "reg_only",
2667     synch_mode => "on",
2668      sum_lutc_input => "datac",
2669     lut_mask => "8000")
2670 port map (
2671 regout => HSYNC_STATE_17,
2672 clk => clk_pin_c,
2673 dataa => HSYNC_STATE_19,
2674 datab => UN10_HSYNC_COUNTER_3,
2675 datac => UN10_HSYNC_COUNTER_1,
2676 datad => UN10_HSYNC_COUNTER_4,
2677 sclr => UN6_DLY_COUNTER_0_X_56,
2678 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2679         devpor => devpor,
2680         devclrn => devclrn,
2681         aclr => GND,
2682         sload => GND,
2683         cin => GND,
2684         inverta => GND,
2685         aload => GND);
2686 \HSYNC_STATE_3_\: stratix_lcell generic map (
2687     operation_mode => "normal",
2688     output_mode => "reg_only",
2689     synch_mode => "on",
2690      sum_lutc_input => "datac",
2691     lut_mask => "aaaa")
2692 port map (
2693 regout => HSYNC_STATE_21,
2694 clk => clk_pin_c,
2695 dataa => HSYNC_STATE_20,
2696 sclr => UN6_DLY_COUNTER_0_X_56,
2697 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2698         devpor => devpor,
2699         devclrn => devclrn,
2700         datab => VCC,
2701         datac => VCC,
2702         datad => VCC,
2703         aclr => GND,
2704         sload => GND,
2705         cin => GND,
2706         inverta => GND,
2707         aload => GND);
2708 \HSYNC_STATE_2_\: stratix_lcell generic map (
2709     operation_mode => "normal",
2710     output_mode => "reg_only",
2711     synch_mode => "on",
2712      sum_lutc_input => "datac",
2713     lut_mask => "8888")
2714 port map (
2715 regout => HSYNC_STATE_16,
2716 clk => clk_pin_c,
2717 dataa => HSYNC_STATE_21,
2718 datab => UN12_HSYNC_COUNTER,
2719 sclr => UN6_DLY_COUNTER_0_X_56,
2720 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2721         devpor => devpor,
2722         devclrn => devclrn,
2723         datac => VCC,
2724         datad => VCC,
2725         aclr => GND,
2726         sload => GND,
2727         cin => GND,
2728         inverta => GND,
2729         aload => GND);
2730 \HSYNC_STATE_1_\: stratix_lcell generic map (
2731     operation_mode => "normal",
2732     output_mode => "reg_only",
2733     synch_mode => "on",
2734      sum_lutc_input => "datac",
2735     lut_mask => "8000")
2736 port map (
2737 regout => HSYNC_STATE_20,
2738 clk => clk_pin_c,
2739 dataa => HSYNC_STATE_17,
2740 datab => UN11_HSYNC_COUNTER_2,
2741 datac => UN10_HSYNC_COUNTER_1,
2742 datad => UN11_HSYNC_COUNTER_3,
2743 sclr => UN6_DLY_COUNTER_0_X_56,
2744 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2745         devpor => devpor,
2746         devclrn => devclrn,
2747         aclr => GND,
2748         sload => GND,
2749         cin => GND,
2750         inverta => GND,
2751         aload => GND);
2752 \HSYNC_STATE_0_\: stratix_lcell generic map (
2753     operation_mode => "normal",
2754     output_mode => "reg_only",
2755     synch_mode => "on",
2756      sum_lutc_input => "datac",
2757     lut_mask => "8888")
2758 port map (
2759 regout => HSYNC_STATE_18,
2760 clk => clk_pin_c,
2761 dataa => HSYNC_STATE_16,
2762 datab => UN13_HSYNC_COUNTER,
2763 sclr => UN6_DLY_COUNTER_0_X_56,
2764 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2765         devpor => devpor,
2766         devclrn => devclrn,
2767         datac => VCC,
2768         datad => VCC,
2769         aclr => GND,
2770         sload => GND,
2771         cin => GND,
2772         inverta => GND,
2773         aload => GND);
2774 VSYNC_STATE_NEXT_2_SQMUXA_Z297: stratix_lcell generic map (
2775     operation_mode => "normal",
2776     output_mode => "comb_only",
2777     synch_mode => "off",
2778      sum_lutc_input => "datac",
2779     lut_mask => "aaab")
2780 port map (
2781 combout => VSYNC_STATE_NEXT_2_SQMUXA,
2782 dataa => UN6_DLY_COUNTER_0_X_56,
2783 datab => VSYNC_STATE_NEXT_1_SQMUXA_1,
2784 datac => VSYNC_STATE_NEXT_1_SQMUXA_3,
2785 datad => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
2786         devpor => devpor,
2787         devclrn => devclrn,
2788         clk => GND,
2789         aclr => GND,
2790         sclr => GND,
2791         sload => GND,
2792         ena => VCC,
2793         cin => GND,
2794         inverta => GND,
2795         aload => GND);
2796 \HSYNC_STATE_3_0_0_0__G0_0_Z298\: stratix_lcell generic map (
2797     operation_mode => "normal",
2798     output_mode => "comb_only",
2799     synch_mode => "off",
2800      sum_lutc_input => "datac",
2801     lut_mask => "f0f1")
2802 port map (
2803 combout => \HSYNC_STATE_3_0_0_0__G0_0\,
2804 dataa => HSYNC_STATE_NEXT_1_SQMUXA_1,
2805 datab => HSYNC_STATE_NEXT_1_SQMUXA_2,
2806 datac => UN6_DLY_COUNTER_0_X_56,
2807 datad => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
2808         devpor => devpor,
2809         devclrn => devclrn,
2810         clk => GND,
2811         aclr => GND,
2812         sclr => GND,
2813         sload => GND,
2814         ena => VCC,
2815         cin => GND,
2816         inverta => GND,
2817         aload => GND);
2818 UN1_HSYNC_STATE_NEXT_1_SQMUXA_0_Z299: stratix_lcell generic map (
2819     operation_mode => "normal",
2820     output_mode => "comb_only",
2821     synch_mode => "off",
2822      sum_lutc_input => "datac",
2823     lut_mask => "0ace")
2824 port map (
2825 combout => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
2826 dataa => HSYNC_STATE_16,
2827 datab => HSYNC_STATE_21,
2828 datac => UN13_HSYNC_COUNTER,
2829 datad => UN12_HSYNC_COUNTER,
2830         devpor => devpor,
2831         devclrn => devclrn,
2832         clk => GND,
2833         aclr => GND,
2834         sclr => GND,
2835         sload => GND,
2836         ena => VCC,
2837         cin => GND,
2838         inverta => GND,
2839         aload => GND);
2840 UN1_VSYNC_STATE_NEXT_1_SQMUXA_0_Z300: stratix_lcell generic map (
2841     operation_mode => "normal",
2842     output_mode => "comb_only",
2843     synch_mode => "off",
2844      sum_lutc_input => "datac",
2845     lut_mask => "ff2a")
2846 port map (
2847 combout => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
2848 dataa => VSYNC_STATE_9,
2849 datab => UN12_VSYNC_COUNTER_6,
2850 datac => UN15_VSYNC_COUNTER_4,
2851 datad => VSYNC_STATE_NEXT_1_SQMUXA_2,
2852         devpor => devpor,
2853         devclrn => devclrn,
2854         clk => GND,
2855         aclr => GND,
2856         sclr => GND,
2857         sload => GND,
2858         ena => VCC,
2859         cin => GND,
2860         inverta => GND,
2861         aload => GND);
2862 \VSYNC_STATE_3_IV_0_0__G0_0_A3_0_Z301\: stratix_lcell generic map (
2863     operation_mode => "normal",
2864     output_mode => "comb_only",
2865     synch_mode => "off",
2866      sum_lutc_input => "datac",
2867     lut_mask => "8080")
2868 port map (
2869 combout => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
2870 dataa => VSYNC_STATE_9,
2871 datab => UN12_VSYNC_COUNTER_6,
2872 datac => UN15_VSYNC_COUNTER_4,
2873         devpor => devpor,
2874         devclrn => devclrn,
2875         clk => GND,
2876         datad => VCC,
2877         aclr => GND,
2878         sclr => GND,
2879         sload => GND,
2880         ena => VCC,
2881         cin => GND,
2882         inverta => GND,
2883         aload => GND);
2884 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO8: stratix_lcell generic map (
2885     operation_mode => "normal",
2886     output_mode => "comb_only",
2887     synch_mode => "off",
2888      sum_lutc_input => "datac",
2889     lut_mask => "ff7f")
2890 port map (
2891 combout => UN10_LINE_COUNTER_SIGLTO8,
2892 dataa => LINE_COUNTER_SIG_6_0,
2893 datab => LINE_COUNTER_SIG_7_0,
2894 datac => LINE_COUNTER_SIG_8_0,
2895 datad => UN10_LINE_COUNTER_SIGLTO5,
2896         devpor => devpor,
2897         devclrn => devclrn,
2898         clk => GND,
2899         aclr => GND,
2900         sclr => GND,
2901         sload => GND,
2902         ena => VCC,
2903         cin => GND,
2904         inverta => GND,
2905         aload => GND);
2906 G_2: stratix_lcell generic map (
2907     operation_mode => "normal",
2908     output_mode => "comb_only",
2909     synch_mode => "off",
2910      sum_lutc_input => "datac",
2911     lut_mask => "0f1f")
2912 port map (
2913 combout => G_2_I,
2914 dataa => HSYNC_STATE_18,
2915 datab => HSYNC_STATE_22,
2916 datac => UN9_HSYNC_COUNTERLT9,
2917 datad => UN6_DLY_COUNTER_0_X_56,
2918         devpor => devpor,
2919         devclrn => devclrn,
2920         clk => GND,
2921         aclr => GND,
2922         sclr => GND,
2923         sload => GND,
2924         ena => VCC,
2925         cin => GND,
2926         inverta => GND,
2927         aload => GND);
2928 VSYNC_STATE_NEXT_1_SQMUXA_1_Z304: stratix_lcell generic map (
2929     operation_mode => "normal",
2930     output_mode => "comb_only",
2931     synch_mode => "off",
2932      sum_lutc_input => "datac",
2933     lut_mask => "d0f0")
2934 port map (
2935 combout => VSYNC_STATE_NEXT_1_SQMUXA_1,
2936 dataa => VSYNC_COUNTER_42,
2937 datab => VSYNC_COUNTER_33,
2938 datac => VSYNC_STATE_10,
2939 datad => UN14_VSYNC_COUNTER_8,
2940         devpor => devpor,
2941         devclrn => devclrn,
2942         clk => GND,
2943         aclr => GND,
2944         sclr => GND,
2945         sload => GND,
2946         ena => VCC,
2947         cin => GND,
2948         inverta => GND,
2949         aload => GND);
2950 VSYNC_STATE_NEXT_1_SQMUXA_2_Z305: stratix_lcell generic map (
2951     operation_mode => "normal",
2952     output_mode => "comb_only",
2953     synch_mode => "off",
2954      sum_lutc_input => "datac",
2955     lut_mask => "2a2a")
2956 port map (
2957 combout => VSYNC_STATE_NEXT_1_SQMUXA_2,
2958 dataa => VSYNC_STATE_13,
2959 datab => UN12_VSYNC_COUNTER_7,
2960 datac => UN13_VSYNC_COUNTER_4,
2961         devpor => devpor,
2962         devclrn => devclrn,
2963         clk => GND,
2964         datad => VCC,
2965         aclr => GND,
2966         sclr => GND,
2967         sload => GND,
2968         ena => VCC,
2969         cin => GND,
2970         inverta => GND,
2971         aload => GND);
2972 VSYNC_STATE_NEXT_1_SQMUXA_3_Z306: stratix_lcell generic map (
2973     operation_mode => "normal",
2974     output_mode => "comb_only",
2975     synch_mode => "off",
2976      sum_lutc_input => "datac",
2977     lut_mask => "70f0")
2978 port map (
2979 combout => VSYNC_STATE_NEXT_1_SQMUXA_3,
2980 dataa => VSYNC_COUNTER_42,
2981 datab => VSYNC_COUNTER_33,
2982 datac => VSYNC_STATE_11,
2983 datad => UN14_VSYNC_COUNTER_8,
2984         devpor => devpor,
2985         devclrn => devclrn,
2986         clk => GND,
2987         aclr => GND,
2988         sclr => GND,
2989         sload => GND,
2990         ena => VCC,
2991         cin => GND,
2992         inverta => GND,
2993         aload => GND);
2994 G_16: stratix_lcell generic map (
2995     operation_mode => "normal",
2996     output_mode => "comb_only",
2997     synch_mode => "off",
2998      sum_lutc_input => "datac",
2999     lut_mask => "0f1f")
3000 port map (
3001 combout => G_16_I,
3002 dataa => VSYNC_STATE_15,
3003 datab => VSYNC_STATE_12,
3004 datac => UN9_VSYNC_COUNTERLT9,
3005 datad => UN6_DLY_COUNTER_0_X_56,
3006         devpor => devpor,
3007         devclrn => devclrn,
3008         clk => GND,
3009         aclr => GND,
3010         sclr => GND,
3011         sload => GND,
3012         ena => VCC,
3013         cin => GND,
3014         inverta => GND,
3015         aload => GND);
3016 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLTO9: stratix_lcell generic map (
3017     operation_mode => "normal",
3018     output_mode => "comb_only",
3019     synch_mode => "off",
3020      sum_lutc_input => "datac",
3021     lut_mask => "1f0f")
3022 port map (
3023 combout => UN10_COLUMN_COUNTER_SIGLTO9,
3024 dataa => COLUMN_COUNTER_SIG_30,
3025 datab => COLUMN_COUNTER_SIG_31,
3026 datac => COLUMN_COUNTER_SIG_32,
3027 datad => UN10_COLUMN_COUNTER_SIGLT6,
3028         devpor => devpor,
3029         devclrn => devclrn,
3030         clk => GND,
3031         aclr => GND,
3032         sclr => GND,
3033         sload => GND,
3034         ena => VCC,
3035         cin => GND,
3036         inverta => GND,
3037         aload => GND);
3038 HSYNC_STATE_NEXT_1_SQMUXA_2_Z309: stratix_lcell generic map (
3039     operation_mode => "normal",
3040     output_mode => "comb_only",
3041     synch_mode => "off",
3042      sum_lutc_input => "datac",
3043     lut_mask => "2aaa")
3044 port map (
3045 combout => HSYNC_STATE_NEXT_1_SQMUXA_2,
3046 dataa => HSYNC_STATE_17,
3047 datab => UN11_HSYNC_COUNTER_2,
3048 datac => UN10_HSYNC_COUNTER_1,
3049 datad => UN11_HSYNC_COUNTER_3,
3050         devpor => devpor,
3051         devclrn => devclrn,
3052         clk => GND,
3053         aclr => GND,
3054         sclr => GND,
3055         sload => GND,
3056         ena => VCC,
3057         cin => GND,
3058         inverta => GND,
3059         aload => GND);
3060 HSYNC_STATE_NEXT_1_SQMUXA_1_Z310: stratix_lcell generic map (
3061     operation_mode => "normal",
3062     output_mode => "comb_only",
3063     synch_mode => "off",
3064      sum_lutc_input => "datac",
3065     lut_mask => "2aaa")
3066 port map (
3067 combout => HSYNC_STATE_NEXT_1_SQMUXA_1,
3068 dataa => HSYNC_STATE_19,
3069 datab => UN10_HSYNC_COUNTER_3,
3070 datac => UN10_HSYNC_COUNTER_1,
3071 datad => UN10_HSYNC_COUNTER_4,
3072         devpor => devpor,
3073         devclrn => devclrn,
3074         clk => GND,
3075         aclr => GND,
3076         sclr => GND,
3077         sload => GND,
3078         ena => VCC,
3079         cin => GND,
3080         inverta => GND,
3081         aload => GND);
3082 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER: stratix_lcell generic map (
3083     operation_mode => "normal",
3084     output_mode => "comb_only",
3085     synch_mode => "off",
3086      sum_lutc_input => "datac",
3087     lut_mask => "1000")
3088 port map (
3089 combout => UN13_HSYNC_COUNTER,
3090 dataa => HSYNC_COUNTER_46,
3091 datab => HSYNC_COUNTER_45,
3092 datac => UN13_HSYNC_COUNTER_2,
3093 datad => UN13_HSYNC_COUNTER_7,
3094         devpor => devpor,
3095         devclrn => devclrn,
3096         clk => GND,
3097         aclr => GND,
3098         sclr => GND,
3099         sload => GND,
3100         ena => VCC,
3101         cin => GND,
3102         inverta => GND,
3103         aload => GND);
3104 HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9: stratix_lcell generic map (
3105     operation_mode => "normal",
3106     output_mode => "comb_only",
3107     synch_mode => "off",
3108      sum_lutc_input => "datac",
3109     lut_mask => "f7ff")
3110 port map (
3111 combout => UN9_HSYNC_COUNTERLT9,
3112 dataa => HSYNC_COUNTER_44,
3113 datab => HSYNC_COUNTER_43,
3114 datac => UN9_HSYNC_COUNTERLT9_3,
3115 datad => UN13_HSYNC_COUNTER_7,
3116         devpor => devpor,
3117         devclrn => devclrn,
3118         clk => GND,
3119         aclr => GND,
3120         sclr => GND,
3121         sload => GND,
3122         ena => VCC,
3123         cin => GND,
3124         inverta => GND,
3125         aload => GND);
3126 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9: stratix_lcell generic map (
3127     operation_mode => "normal",
3128     output_mode => "comb_only",
3129     synch_mode => "off",
3130      sum_lutc_input => "datac",
3131     lut_mask => "fff7")
3132 port map (
3133 combout => UN9_VSYNC_COUNTERLT9,
3134 dataa => VSYNC_COUNTER_38,
3135 datab => VSYNC_COUNTER_37,
3136 datac => UN9_VSYNC_COUNTERLT9_5,
3137 datad => UN9_VSYNC_COUNTERLT9_6,
3138         devpor => devpor,
3139         devclrn => devclrn,
3140         clk => GND,
3141         aclr => GND,
3142         sclr => GND,
3143         sload => GND,
3144         ena => VCC,
3145         cin => GND,
3146         inverta => GND,
3147         aload => GND);
3148 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER: stratix_lcell generic map (
3149     operation_mode => "normal",
3150     output_mode => "comb_only",
3151     synch_mode => "off",
3152      sum_lutc_input => "datac",
3153     lut_mask => "8000")
3154 port map (
3155 combout => UN12_HSYNC_COUNTER,
3156 dataa => HSYNC_COUNTER_52,
3157 datab => HSYNC_COUNTER_51,
3158 datac => UN12_HSYNC_COUNTER_3,
3159 datad => UN12_HSYNC_COUNTER_4,
3160         devpor => devpor,
3161         devclrn => devclrn,
3162         clk => GND,
3163         aclr => GND,
3164         sclr => GND,
3165         sload => GND,
3166         ena => VCC,
3167         cin => GND,
3168         inverta => GND,
3169         aload => GND);
3170 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO5: stratix_lcell generic map (
3171     operation_mode => "normal",
3172     output_mode => "comb_only",
3173     synch_mode => "off",
3174      sum_lutc_input => "datac",
3175     lut_mask => "0f07")
3176 port map (
3177 combout => UN10_LINE_COUNTER_SIGLTO5,
3178 dataa => LINE_COUNTER_SIG_1_0,
3179 datab => LINE_COUNTER_SIG_2_0,
3180 datac => LINE_COUNTER_SIG_5_0,
3181 datad => UN10_LINE_COUNTER_SIGLT4_2,
3182         devpor => devpor,
3183         devclrn => devclrn,
3184         clk => GND,
3185         aclr => GND,
3186         sclr => GND,
3187         sload => GND,
3188         ena => VCC,
3189         cin => GND,
3190         inverta => GND,
3191         aload => GND);
3192 VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_4: stratix_lcell generic map (
3193     operation_mode => "normal",
3194     output_mode => "comb_only",
3195     synch_mode => "off",
3196      sum_lutc_input => "datac",
3197     lut_mask => "1010")
3198 port map (
3199 combout => UN15_VSYNC_COUNTER_4,
3200 dataa => VSYNC_COUNTER_41,
3201 datab => VSYNC_COUNTER_38,
3202 datac => UN15_VSYNC_COUNTER_3,
3203         devpor => devpor,
3204         devclrn => devclrn,
3205         clk => GND,
3206         datad => VCC,
3207         aclr => GND,
3208         sclr => GND,
3209         sload => GND,
3210         ena => VCC,
3211         cin => GND,
3212         inverta => GND,
3213         aload => GND);
3214 VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_4: stratix_lcell generic map (
3215     operation_mode => "normal",
3216     output_mode => "comb_only",
3217     synch_mode => "off",
3218      sum_lutc_input => "datac",
3219     lut_mask => "8080")
3220 port map (
3221 combout => UN13_VSYNC_COUNTER_4,
3222 dataa => VSYNC_COUNTER_42,
3223 datab => VSYNC_COUNTER_37,
3224 datac => UN13_VSYNC_COUNTER_3,
3225         devpor => devpor,
3226         devclrn => devclrn,
3227         clk => GND,
3228         datad => VCC,
3229         aclr => GND,
3230         sclr => GND,
3231         sload => GND,
3232         ena => VCC,
3233         cin => GND,
3234         inverta => GND,
3235         aload => GND);
3236 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6: stratix_lcell generic map (
3237     operation_mode => "normal",
3238     output_mode => "comb_only",
3239     synch_mode => "off",
3240      sum_lutc_input => "datac",
3241     lut_mask => "ff7f")
3242 port map (
3243 combout => UN10_COLUMN_COUNTER_SIGLT6,
3244 dataa => COLUMN_COUNTER_SIG_27,
3245 datab => COLUMN_COUNTER_SIG_29,
3246 datac => COLUMN_COUNTER_SIG_28,
3247 datad => UN10_COLUMN_COUNTER_SIGLT6_4,
3248         devpor => devpor,
3249         devclrn => devclrn,
3250         clk => GND,
3251         aclr => GND,
3252         sclr => GND,
3253         sload => GND,
3254         ena => VCC,
3255         cin => GND,
3256         inverta => GND,
3257         aload => GND);
3258 HSYNC_COUNTER_NEXT_1_SQMUXA_Z319: stratix_lcell generic map (
3259     operation_mode => "normal",
3260     output_mode => "comb_only",
3261     synch_mode => "off",
3262      sum_lutc_input => "datac",
3263     lut_mask => "0080")
3264 port map (
3265 combout => HSYNC_COUNTER_NEXT_1_SQMUXA,
3266 dataa => reset_pin_c,
3267 datab => dly_counter_0,
3268 datac => dly_counter_1,
3269 datad => D_SET_HSYNC_COUNTER_57,
3270         devpor => devpor,
3271         devclrn => devclrn,
3272         clk => GND,
3273         aclr => GND,
3274         sclr => GND,
3275         sload => GND,
3276         ena => VCC,
3277         cin => GND,
3278         inverta => GND,
3279         aload => GND);
3280 VSYNC_FSM_NEXT_UN14_VSYNC_COUNTER_8: stratix_lcell generic map (
3281     operation_mode => "normal",
3282     output_mode => "comb_only",
3283     synch_mode => "off",
3284      sum_lutc_input => "datac",
3285     lut_mask => "8888")
3286 port map (
3287 combout => UN14_VSYNC_COUNTER_8,
3288 dataa => UN12_VSYNC_COUNTER_6,
3289 datab => UN12_VSYNC_COUNTER_7,
3290         devpor => devpor,
3291         devclrn => devclrn,
3292         clk => GND,
3293         datac => VCC,
3294         datad => VCC,
3295         aclr => GND,
3296         sclr => GND,
3297         sload => GND,
3298         ena => VCC,
3299         cin => GND,
3300         inverta => GND,
3301         aload => GND);
3302 LINE_COUNTER_NEXT_0_SQMUXA_1_1_Z321: stratix_lcell generic map (
3303     operation_mode => "normal",
3304     output_mode => "comb_only",
3305     synch_mode => "off",
3306      sum_lutc_input => "datac",
3307     lut_mask => "0080")
3308 port map (
3309 combout => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
3310 dataa => reset_pin_c,
3311 datab => dly_counter_0,
3312 datac => dly_counter_1,
3313 datad => VSYNC_STATE_14,
3314         devpor => devpor,
3315         devclrn => devclrn,
3316         clk => GND,
3317         aclr => GND,
3318         sclr => GND,
3319         sload => GND,
3320         ena => VCC,
3321         cin => GND,
3322         inverta => GND,
3323         aload => GND);
3324 V_SYNC_1_0_0_0_G1_Z322: stratix_lcell generic map (
3325     operation_mode => "normal",
3326     output_mode => "comb_only",
3327     synch_mode => "off",
3328      sum_lutc_input => "datac",
3329     lut_mask => "ccd8")
3330 port map (
3331 combout => V_SYNC_1_0_0_0_G1,
3332 dataa => VSYNC_STATE_9,
3333 datab => V_SYNC_54,
3334 datac => VSYNC_STATE_13,
3335 datad => UN1_VSYNC_STATE_2_0,
3336         devpor => devpor,
3337         devclrn => devclrn,
3338         clk => GND,
3339         aclr => GND,
3340         sclr => GND,
3341         sload => GND,
3342         ena => VCC,
3343         cin => GND,
3344         inverta => GND,
3345         aload => GND);
3346 H_ENABLE_SIG_1_0_0_0_G0_I_O4_Z323: stratix_lcell generic map (
3347     operation_mode => "normal",
3348     output_mode => "comb_only",
3349     synch_mode => "off",
3350      sum_lutc_input => "datac",
3351     lut_mask => "f1f1")
3352 port map (
3353 combout => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
3354 dataa => VSYNC_STATE_13,
3355 datab => VSYNC_STATE_10,
3356 datac => UN6_DLY_COUNTER_0_X_56,
3357         devpor => devpor,
3358         devclrn => devclrn,
3359         clk => GND,
3360         datad => VCC,
3361         aclr => GND,
3362         sclr => GND,
3363         sload => GND,
3364         ena => VCC,
3365         cin => GND,
3366         inverta => GND,
3367         aload => GND);
3368 VSYNC_COUNTER_NEXT_1_SQMUXA_Z324: stratix_lcell generic map (
3369     operation_mode => "normal",
3370     output_mode => "comb_only",
3371     synch_mode => "off",
3372      sum_lutc_input => "datac",
3373     lut_mask => "0080")
3374 port map (
3375 combout => VSYNC_COUNTER_NEXT_1_SQMUXA,
3376 dataa => reset_pin_c,
3377 datab => dly_counter_0,
3378 datac => dly_counter_1,
3379 datad => D_SET_VSYNC_COUNTER_53,
3380         devpor => devpor,
3381         devclrn => devclrn,
3382         clk => GND,
3383         aclr => GND,
3384         sclr => GND,
3385         sload => GND,
3386         ena => VCC,
3387         cin => GND,
3388         inverta => GND,
3389         aload => GND);
3390 V_ENABLE_SIG_1_0_0_0_G0_I_O4_Z325: stratix_lcell generic map (
3391     operation_mode => "normal",
3392     output_mode => "comb_only",
3393     synch_mode => "off",
3394      sum_lutc_input => "datac",
3395     lut_mask => "f1f1")
3396 port map (
3397 combout => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
3398 dataa => HSYNC_STATE_17,
3399 datab => HSYNC_STATE_19,
3400 datac => UN6_DLY_COUNTER_0_X_56,
3401         devpor => devpor,
3402         devclrn => devclrn,
3403         clk => GND,
3404         datad => VCC,
3405         aclr => GND,
3406         sclr => GND,
3407         sload => GND,
3408         ena => VCC,
3409         cin => GND,
3410         inverta => GND,
3411         aload => GND);
3412 H_SYNC_1_0_0_0_G1_Z326: stratix_lcell generic map (
3413     operation_mode => "normal",
3414     output_mode => "comb_only",
3415     synch_mode => "off",
3416      sum_lutc_input => "datac",
3417     lut_mask => "ccd8")
3418 port map (
3419 combout => H_SYNC_1_0_0_0_G1,
3420 dataa => HSYNC_STATE_16,
3421 datab => H_SYNC_55,
3422 datac => HSYNC_STATE_17,
3423 datad => UN1_HSYNC_STATE_3_0,
3424         devpor => devpor,
3425         devclrn => devclrn,
3426         clk => GND,
3427         aclr => GND,
3428         sclr => GND,
3429         sload => GND,
3430         ena => VCC,
3431         cin => GND,
3432         inverta => GND,
3433         aload => GND);
3434 COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_Z327: stratix_lcell generic map (
3435     operation_mode => "normal",
3436     output_mode => "comb_only",
3437     synch_mode => "off",
3438      sum_lutc_input => "datac",
3439     lut_mask => "0080")
3440 port map (
3441 combout => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
3442 dataa => reset_pin_c,
3443 datab => dly_counter_0,
3444 datac => dly_counter_1,
3445 datad => HSYNC_STATE_20,
3446         devpor => devpor,
3447         devclrn => devclrn,
3448         clk => GND,
3449         aclr => GND,
3450         sclr => GND,
3451         sload => GND,
3452         ena => VCC,
3453         cin => GND,
3454         inverta => GND,
3455         aload => GND);
3456 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_4: stratix_lcell generic map (
3457     operation_mode => "normal",
3458     output_mode => "comb_only",
3459     synch_mode => "off",
3460      sum_lutc_input => "datac",
3461     lut_mask => "0010")
3462 port map (
3463 combout => UN12_HSYNC_COUNTER_4,
3464 dataa => HSYNC_COUNTER_46,
3465 datab => HSYNC_COUNTER_45,
3466 datac => HSYNC_COUNTER_43,
3467 datad => HSYNC_COUNTER_49,
3468         devpor => devpor,
3469         devclrn => devclrn,
3470         clk => GND,
3471         aclr => GND,
3472         sclr => GND,
3473         sload => GND,
3474         ena => VCC,
3475         cin => GND,
3476         inverta => GND,
3477         aload => GND);
3478 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_3: stratix_lcell generic map (
3479     operation_mode => "normal",
3480     output_mode => "comb_only",
3481     synch_mode => "off",
3482      sum_lutc_input => "datac",
3483     lut_mask => "0008")
3484 port map (
3485 combout => UN12_HSYNC_COUNTER_3,
3486 dataa => HSYNC_COUNTER_50,
3487 datab => HSYNC_COUNTER_44,
3488 datac => HSYNC_COUNTER_48,
3489 datad => HSYNC_COUNTER_47,
3490         devpor => devpor,
3491         devclrn => devclrn,
3492         clk => GND,
3493         aclr => GND,
3494         sclr => GND,
3495         sload => GND,
3496         ena => VCC,
3497         cin => GND,
3498         inverta => GND,
3499         aload => GND);
3500 HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_3: stratix_lcell generic map (
3501     operation_mode => "normal",
3502     output_mode => "comb_only",
3503     synch_mode => "off",
3504      sum_lutc_input => "datac",
3505     lut_mask => "0008")
3506 port map (
3507 combout => UN11_HSYNC_COUNTER_3,
3508 dataa => HSYNC_COUNTER_52,
3509 datab => HSYNC_COUNTER_51,
3510 datac => HSYNC_COUNTER_49,
3511 datad => HSYNC_COUNTER_48,
3512         devpor => devpor,
3513         devclrn => devclrn,
3514         clk => GND,
3515         aclr => GND,
3516         sclr => GND,
3517         sload => GND,
3518         ena => VCC,
3519         cin => GND,
3520         inverta => GND,
3521         aload => GND);
3522 HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_2: stratix_lcell generic map (
3523     operation_mode => "normal",
3524     output_mode => "comb_only",
3525     synch_mode => "off",
3526      sum_lutc_input => "datac",
3527     lut_mask => "0808")
3528 port map (
3529 combout => UN11_HSYNC_COUNTER_2,
3530 dataa => HSYNC_COUNTER_50,
3531 datab => HSYNC_COUNTER_45,
3532 datac => HSYNC_COUNTER_46,
3533         devpor => devpor,
3534         devclrn => devclrn,
3535         clk => GND,
3536         datad => VCC,
3537         aclr => GND,
3538         sclr => GND,
3539         sload => GND,
3540         ena => VCC,
3541         cin => GND,
3542         inverta => GND,
3543         aload => GND);
3544 HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9_3: stratix_lcell generic map (
3545     operation_mode => "normal",
3546     output_mode => "comb_only",
3547     synch_mode => "off",
3548      sum_lutc_input => "datac",
3549     lut_mask => "7fff")
3550 port map (
3551 combout => UN9_HSYNC_COUNTERLT9_3,
3552 dataa => HSYNC_COUNTER_46,
3553 datab => HSYNC_COUNTER_45,
3554 datac => HSYNC_COUNTER_48,
3555 datad => HSYNC_COUNTER_47,
3556         devpor => devpor,
3557         devclrn => devclrn,
3558         clk => GND,
3559         aclr => GND,
3560         sclr => GND,
3561         sload => GND,
3562         ena => VCC,
3563         cin => GND,
3564         inverta => GND,
3565         aload => GND);
3566 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_2: stratix_lcell generic map (
3567     operation_mode => "normal",
3568     output_mode => "comb_only",
3569     synch_mode => "off",
3570      sum_lutc_input => "datac",
3571     lut_mask => "0080")
3572 port map (
3573 combout => UN13_HSYNC_COUNTER_2,
3574 dataa => HSYNC_COUNTER_44,
3575 datab => HSYNC_COUNTER_43,
3576 datac => HSYNC_COUNTER_48,
3577 datad => HSYNC_COUNTER_47,
3578         devpor => devpor,
3579         devclrn => devclrn,
3580         clk => GND,
3581         aclr => GND,
3582         sclr => GND,
3583         sload => GND,
3584         ena => VCC,
3585         cin => GND,
3586         inverta => GND,
3587         aload => GND);
3588 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_6: stratix_lcell generic map (
3589     operation_mode => "normal",
3590     output_mode => "comb_only",
3591     synch_mode => "off",
3592      sum_lutc_input => "datac",
3593     lut_mask => "7fff")
3594 port map (
3595 combout => UN9_VSYNC_COUNTERLT9_6,
3596 dataa => VSYNC_COUNTER_40,
3597 datab => VSYNC_COUNTER_39,
3598 datac => VSYNC_COUNTER_42,
3599 datad => VSYNC_COUNTER_41,
3600         devpor => devpor,
3601         devclrn => devclrn,
3602         clk => GND,
3603         aclr => GND,
3604         sclr => GND,
3605         sload => GND,
3606         ena => VCC,
3607         cin => GND,
3608         inverta => GND,
3609         aload => GND);
3610 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_5: stratix_lcell generic map (
3611     operation_mode => "normal",
3612     output_mode => "comb_only",
3613     synch_mode => "off",
3614      sum_lutc_input => "datac",
3615     lut_mask => "7fff")
3616 port map (
3617 combout => UN9_VSYNC_COUNTERLT9_5,
3618 dataa => VSYNC_COUNTER_34,
3619 datab => VSYNC_COUNTER_33,
3620 datac => VSYNC_COUNTER_36,
3621 datad => VSYNC_COUNTER_35,
3622         devpor => devpor,
3623         devclrn => devclrn,
3624         clk => GND,
3625         aclr => GND,
3626         sclr => GND,
3627         sload => GND,
3628         ena => VCC,
3629         cin => GND,
3630         inverta => GND,
3631         aload => GND);
3632 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_4: stratix_lcell generic map (
3633     operation_mode => "normal",
3634     output_mode => "comb_only",
3635     synch_mode => "off",
3636      sum_lutc_input => "datac",
3637     lut_mask => "8000")
3638 port map (
3639 combout => UN10_HSYNC_COUNTER_4,
3640 dataa => HSYNC_COUNTER_48,
3641 datab => HSYNC_COUNTER_46,
3642 datac => HSYNC_COUNTER_51,
3643 datad => HSYNC_COUNTER_49,
3644         devpor => devpor,
3645         devclrn => devclrn,
3646         clk => GND,
3647         aclr => GND,
3648         sclr => GND,
3649         sload => GND,
3650         ena => VCC,
3651         cin => GND,
3652         inverta => GND,
3653         aload => GND);
3654 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_3: stratix_lcell generic map (
3655     operation_mode => "normal",
3656     output_mode => "comb_only",
3657     synch_mode => "off",
3658      sum_lutc_input => "datac",
3659     lut_mask => "0101")
3660 port map (
3661 combout => UN10_HSYNC_COUNTER_3,
3662 dataa => HSYNC_COUNTER_52,
3663 datab => HSYNC_COUNTER_45,
3664 datac => HSYNC_COUNTER_50,
3665         devpor => devpor,
3666         devclrn => devclrn,
3667         clk => GND,
3668         datad => VCC,
3669         aclr => GND,
3670         sclr => GND,
3671         sload => GND,
3672         ena => VCC,
3673         cin => GND,
3674         inverta => GND,
3675         aload => GND);
3676 VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_3: stratix_lcell generic map (
3677     operation_mode => "normal",
3678     output_mode => "comb_only",
3679     synch_mode => "off",
3680      sum_lutc_input => "datac",
3681     lut_mask => "0020")
3682 port map (
3683 combout => UN15_VSYNC_COUNTER_3,
3684 dataa => VSYNC_COUNTER_33,
3685 datab => VSYNC_COUNTER_40,
3686 datac => VSYNC_COUNTER_39,
3687 datad => VSYNC_COUNTER_42,
3688         devpor => devpor,
3689         devclrn => devclrn,
3690         clk => GND,
3691         aclr => GND,
3692         sclr => GND,
3693         sload => GND,
3694         ena => VCC,
3695         cin => GND,
3696         inverta => GND,
3697         aload => GND);
3698 VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_3: stratix_lcell generic map (
3699     operation_mode => "normal",
3700     output_mode => "comb_only",
3701     synch_mode => "off",
3702      sum_lutc_input => "datac",
3703     lut_mask => "0001")
3704 port map (
3705 combout => UN13_VSYNC_COUNTER_3,
3706 dataa => VSYNC_COUNTER_36,
3707 datab => VSYNC_COUNTER_35,
3708 datac => VSYNC_COUNTER_34,
3709 datad => VSYNC_COUNTER_33,
3710         devpor => devpor,
3711         devclrn => devclrn,
3712         clk => GND,
3713         aclr => GND,
3714         sclr => GND,
3715         sload => GND,
3716         ena => VCC,
3717         cin => GND,
3718         inverta => GND,
3719         aload => GND);
3720 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6_4: stratix_lcell generic map (
3721     operation_mode => "normal",
3722     output_mode => "comb_only",
3723     synch_mode => "off",
3724      sum_lutc_input => "datac",
3725     lut_mask => "7fff")
3726 port map (
3727 combout => UN10_COLUMN_COUNTER_SIGLT6_4,
3728 dataa => COLUMN_COUNTER_SIG_25,
3729 datab => COLUMN_COUNTER_SIG_26,
3730 datac => COLUMN_COUNTER_SIG_23,
3731 datad => COLUMN_COUNTER_SIG_24,
3732         devpor => devpor,
3733         devclrn => devclrn,
3734         clk => GND,
3735         aclr => GND,
3736         sclr => GND,
3737         sload => GND,
3738         ena => VCC,
3739         cin => GND,
3740         inverta => GND,
3741         aload => GND);
3742 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLT4_2: stratix_lcell generic map (
3743     operation_mode => "normal",
3744     output_mode => "comb_only",
3745     synch_mode => "off",
3746      sum_lutc_input => "datac",
3747     lut_mask => "7f7f")
3748 port map (
3749 combout => UN10_LINE_COUNTER_SIGLT4_2,
3750 dataa => LINE_COUNTER_SIG_3_0,
3751 datab => LINE_COUNTER_SIG_4_0,
3752 datac => LINE_COUNTER_SIG_0_0,
3753         devpor => devpor,
3754         devclrn => devclrn,
3755         clk => GND,
3756         datad => VCC,
3757         aclr => GND,
3758         sclr => GND,
3759         sload => GND,
3760         ena => VCC,
3761         cin => GND,
3762         inverta => GND,
3763         aload => GND);
3764 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_1: stratix_lcell generic map (
3765     operation_mode => "normal",
3766     output_mode => "comb_only",
3767     synch_mode => "off",
3768      sum_lutc_input => "datac",
3769     lut_mask => "0101")
3770 port map (
3771 combout => UN10_HSYNC_COUNTER_1,
3772 dataa => HSYNC_COUNTER_47,
3773 datab => HSYNC_COUNTER_44,
3774 datac => HSYNC_COUNTER_43,
3775         devpor => devpor,
3776         devclrn => devclrn,
3777         clk => GND,
3778         datad => VCC,
3779         aclr => GND,
3780         sclr => GND,
3781         sload => GND,
3782         ena => VCC,
3783         cin => GND,
3784         inverta => GND,
3785         aload => GND);
3786 VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_6: stratix_lcell generic map (
3787     operation_mode => "normal",
3788     output_mode => "comb_only",
3789     synch_mode => "off",
3790      sum_lutc_input => "datac",
3791     lut_mask => "0001")
3792 port map (
3793 combout => UN12_VSYNC_COUNTER_6,
3794 dataa => VSYNC_COUNTER_35,
3795 datab => VSYNC_COUNTER_34,
3796 datac => VSYNC_COUNTER_37,
3797 datad => VSYNC_COUNTER_36,
3798         devpor => devpor,
3799         devclrn => devclrn,
3800         clk => GND,
3801         aclr => GND,
3802         sclr => GND,
3803         sload => GND,
3804         ena => VCC,
3805         cin => GND,
3806         inverta => GND,
3807         aload => GND);
3808 VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_7: stratix_lcell generic map (
3809     operation_mode => "normal",
3810     output_mode => "comb_only",
3811     synch_mode => "off",
3812      sum_lutc_input => "datac",
3813     lut_mask => "0001")
3814 port map (
3815 combout => UN12_VSYNC_COUNTER_7,
3816 dataa => VSYNC_COUNTER_39,
3817 datab => VSYNC_COUNTER_38,
3818 datac => VSYNC_COUNTER_41,
3819 datad => VSYNC_COUNTER_40,
3820         devpor => devpor,
3821         devclrn => devclrn,
3822         clk => GND,
3823         aclr => GND,
3824         sclr => GND,
3825         sload => GND,
3826         ena => VCC,
3827         cin => GND,
3828         inverta => GND,
3829         aload => GND);
3830 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_7: stratix_lcell generic map (
3831     operation_mode => "normal",
3832     output_mode => "comb_only",
3833     synch_mode => "off",
3834      sum_lutc_input => "datac",
3835     lut_mask => "8000")
3836 port map (
3837 combout => UN13_HSYNC_COUNTER_7,
3838 dataa => HSYNC_COUNTER_50,
3839 datab => HSYNC_COUNTER_49,
3840 datac => HSYNC_COUNTER_52,
3841 datad => HSYNC_COUNTER_51,
3842         devpor => devpor,
3843         devclrn => devclrn,
3844         clk => GND,
3845         aclr => GND,
3846         sclr => GND,
3847         sload => GND,
3848         ena => VCC,
3849         cin => GND,
3850         inverta => GND,
3851         aload => GND);
3852 UN1_HSYNC_STATE_3_0_Z346: stratix_lcell generic map (
3853     operation_mode => "normal",
3854     output_mode => "comb_only",
3855     synch_mode => "off",
3856      sum_lutc_input => "datac",
3857     lut_mask => "eeee")
3858 port map (
3859 combout => UN1_HSYNC_STATE_3_0,
3860 dataa => HSYNC_STATE_21,
3861 datab => HSYNC_STATE_20,
3862         devpor => devpor,
3863         devclrn => devclrn,
3864         clk => GND,
3865         datac => VCC,
3866         datad => VCC,
3867         aclr => GND,
3868         sclr => GND,
3869         sload => GND,
3870         ena => VCC,
3871         cin => GND,
3872         inverta => GND,
3873         aload => GND);
3874 UN1_VSYNC_STATE_2_0_Z347: stratix_lcell generic map (
3875     operation_mode => "normal",
3876     output_mode => "comb_only",
3877     synch_mode => "off",
3878      sum_lutc_input => "datac",
3879     lut_mask => "eeee")
3880 port map (
3881 combout => UN1_VSYNC_STATE_2_0,
3882 dataa => VSYNC_STATE_11,
3883 datab => VSYNC_STATE_14,
3884         devpor => devpor,
3885         devclrn => devclrn,
3886         clk => GND,
3887         datac => VCC,
3888         datad => VCC,
3889         aclr => GND,
3890         sclr => GND,
3891         sload => GND,
3892         ena => VCC,
3893         cin => GND,
3894         inverta => GND,
3895         aload => GND);
3896 D_SET_HSYNC_COUNTER_Z348: stratix_lcell generic map (
3897     operation_mode => "normal",
3898     output_mode => "comb_only",
3899     synch_mode => "off",
3900      sum_lutc_input => "datac",
3901     lut_mask => "eeee")
3902 port map (
3903 combout => D_SET_HSYNC_COUNTER_57,
3904 dataa => HSYNC_STATE_22,
3905 datab => HSYNC_STATE_18,
3906         devpor => devpor,
3907         devclrn => devclrn,
3908         clk => GND,
3909         datac => VCC,
3910         datad => VCC,
3911         aclr => GND,
3912         sclr => GND,
3913         sload => GND,
3914         ena => VCC,
3915         cin => GND,
3916         inverta => GND,
3917         aload => GND);
3918 D_SET_VSYNC_COUNTER_Z349: stratix_lcell generic map (
3919     operation_mode => "normal",
3920     output_mode => "comb_only",
3921     synch_mode => "off",
3922      sum_lutc_input => "datac",
3923     lut_mask => "eeee")
3924 port map (
3925 combout => D_SET_VSYNC_COUNTER_53,
3926 dataa => VSYNC_STATE_12,
3927 datab => VSYNC_STATE_15,
3928         devpor => devpor,
3929         devclrn => devclrn,
3930         clk => GND,
3931         datac => VCC,
3932         datad => VCC,
3933         aclr => GND,
3934         sclr => GND,
3935         sload => GND,
3936         ena => VCC,
3937         cin => GND,
3938         inverta => GND,
3939         aload => GND);
3940 \UN1_LINE_COUNTER_SIG_9_\: stratix_lcell generic map (
3941     operation_mode => "normal",
3942     output_mode => "comb_only",
3943     synch_mode => "off",
3944      sum_lutc_input => "cin",
3945      cin_used => "true",
3946     lut_mask => "6c6c")
3947 port map (
3948 combout => UN1_LINE_COUNTER_SIG_COMBOUT(9),
3949 dataa => LINE_COUNTER_SIG_7_0,
3950 datab => LINE_COUNTER_SIG_8_0,
3951 cin => UN1_LINE_COUNTER_SIG_COUT(7),
3952         devpor => devpor,
3953         devclrn => devclrn,
3954         clk => GND,
3955         datac => VCC,
3956         datad => VCC,
3957         aclr => GND,
3958         sclr => GND,
3959         sload => GND,
3960         ena => VCC,
3961         inverta => GND,
3962         aload => GND);
3963 \UN1_LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
3964     operation_mode => "normal",
3965     output_mode => "comb_only",
3966     synch_mode => "off",
3967      sum_lutc_input => "cin",
3968      cin_used => "true",
3969     lut_mask => "5a5a")
3970 port map (
3971 combout => UN1_LINE_COUNTER_SIG_COMBOUT(8),
3972 dataa => LINE_COUNTER_SIG_7_0,
3973 cin => UN1_LINE_COUNTER_SIG_COUT(6),
3974         devpor => devpor,
3975         devclrn => devclrn,
3976         clk => GND,
3977         datab => VCC,
3978         datac => VCC,
3979         datad => VCC,
3980         aclr => GND,
3981         sclr => GND,
3982         sload => GND,
3983         ena => VCC,
3984         inverta => GND,
3985         aload => GND);
3986 \UN1_LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
3987     operation_mode => "arithmetic",
3988     output_mode => "comb_only",
3989     synch_mode => "off",
3990      sum_lutc_input => "cin",
3991      cin_used => "true",
3992     lut_mask => "6c80")
3993 port map (
3994 combout => UN1_LINE_COUNTER_SIG_COMBOUT(7),
3995 cout => UN1_LINE_COUNTER_SIG_COUT(7),
3996 dataa => LINE_COUNTER_SIG_5_0,
3997 datab => LINE_COUNTER_SIG_6_0,
3998 cin => UN1_LINE_COUNTER_SIG_COUT(5),
3999         devpor => devpor,
4000         devclrn => devclrn,
4001         clk => GND,
4002         datac => VCC,
4003         datad => VCC,
4004         aclr => GND,
4005         sclr => GND,
4006         sload => GND,
4007         ena => VCC,
4008         inverta => GND,
4009         aload => GND);
4010 \UN1_LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
4011     operation_mode => "arithmetic",
4012     output_mode => "comb_only",
4013     synch_mode => "off",
4014      sum_lutc_input => "cin",
4015      cin_used => "true",
4016     lut_mask => "5a80")
4017 port map (
4018 combout => UN1_LINE_COUNTER_SIG_COMBOUT(6),
4019 cout => UN1_LINE_COUNTER_SIG_COUT(6),
4020 dataa => LINE_COUNTER_SIG_5_0,
4021 datab => LINE_COUNTER_SIG_6_0,
4022 cin => UN1_LINE_COUNTER_SIG_COUT(4),
4023         devpor => devpor,
4024         devclrn => devclrn,
4025         clk => GND,
4026         datac => VCC,
4027         datad => VCC,
4028         aclr => GND,
4029         sclr => GND,
4030         sload => GND,
4031         ena => VCC,
4032         inverta => GND,
4033         aload => GND);
4034 \UN1_LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
4035     operation_mode => "arithmetic",
4036     output_mode => "comb_only",
4037     synch_mode => "off",
4038      sum_lutc_input => "cin",
4039      cin_used => "true",
4040     lut_mask => "6c80")
4041 port map (
4042 combout => UN1_LINE_COUNTER_SIG_COMBOUT(5),
4043 cout => UN1_LINE_COUNTER_SIG_COUT(5),
4044 dataa => LINE_COUNTER_SIG_3_0,
4045 datab => LINE_COUNTER_SIG_4_0,
4046 cin => UN1_LINE_COUNTER_SIG_COUT(3),
4047         devpor => devpor,
4048         devclrn => devclrn,
4049         clk => GND,
4050         datac => VCC,
4051         datad => VCC,
4052         aclr => GND,
4053         sclr => GND,
4054         sload => GND,
4055         ena => VCC,
4056         inverta => GND,
4057         aload => GND);
4058 \UN1_LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
4059     operation_mode => "arithmetic",
4060     output_mode => "comb_only",
4061     synch_mode => "off",
4062      sum_lutc_input => "cin",
4063      cin_used => "true",
4064     lut_mask => "5a80")
4065 port map (
4066 combout => UN1_LINE_COUNTER_SIG_COMBOUT(4),
4067 cout => UN1_LINE_COUNTER_SIG_COUT(4),
4068 dataa => LINE_COUNTER_SIG_3_0,
4069 datab => LINE_COUNTER_SIG_4_0,
4070 cin => UN1_LINE_COUNTER_SIG_COUT(2),
4071         devpor => devpor,
4072         devclrn => devclrn,
4073         clk => GND,
4074         datac => VCC,
4075         datad => VCC,
4076         aclr => GND,
4077         sclr => GND,
4078         sload => GND,
4079         ena => VCC,
4080         inverta => GND,
4081         aload => GND);
4082 \UN1_LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
4083     operation_mode => "arithmetic",
4084     output_mode => "comb_only",
4085     synch_mode => "off",
4086      sum_lutc_input => "cin",
4087      cin_used => "true",
4088     lut_mask => "6c80")
4089 port map (
4090 combout => UN1_LINE_COUNTER_SIG_COMBOUT(3),
4091 cout => UN1_LINE_COUNTER_SIG_COUT(3),
4092 dataa => LINE_COUNTER_SIG_1_0,
4093 datab => LINE_COUNTER_SIG_2_0,
4094 cin => UN1_LINE_COUNTER_SIG_COUT(1),
4095         devpor => devpor,
4096         devclrn => devclrn,
4097         clk => GND,
4098         datac => VCC,
4099         datad => VCC,
4100         aclr => GND,
4101         sclr => GND,
4102         sload => GND,
4103         ena => VCC,
4104         inverta => GND,
4105         aload => GND);
4106 \UN1_LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
4107     operation_mode => "arithmetic",
4108     output_mode => "comb_only",
4109     synch_mode => "off",
4110      sum_lutc_input => "cin",
4111      cin_used => "true",
4112     lut_mask => "5a80")
4113 port map (
4114 combout => UN1_LINE_COUNTER_SIG_COMBOUT(2),
4115 cout => UN1_LINE_COUNTER_SIG_COUT(2),
4116 dataa => LINE_COUNTER_SIG_1_0,
4117 datab => LINE_COUNTER_SIG_2_0,
4118 cin => UN1_LINE_COUNTER_SIG_A_COUT(1),
4119         devpor => devpor,
4120         devclrn => devclrn,
4121         clk => GND,
4122         datac => VCC,
4123         datad => VCC,
4124         aclr => GND,
4125         sclr => GND,
4126         sload => GND,
4127         ena => VCC,
4128         inverta => GND,
4129         aload => GND);
4130 \UN1_LINE_COUNTER_SIG_A_1_\: stratix_lcell generic map (
4131     operation_mode => "arithmetic",
4132     output_mode => "comb_only",
4133     synch_mode => "off",
4134      sum_lutc_input => "datac",
4135     lut_mask => "0088")
4136 port map (
4137 cout => UN1_LINE_COUNTER_SIG_A_COUT(1),
4138 dataa => D_SET_HSYNC_COUNTER_57,
4139 datab => LINE_COUNTER_SIG_0_0,
4140         devpor => devpor,
4141         devclrn => devclrn,
4142         clk => GND,
4143         datac => VCC,
4144         datad => VCC,
4145         aclr => GND,
4146         sclr => GND,
4147         sload => GND,
4148         ena => VCC,
4149         cin => GND,
4150         inverta => GND,
4151         aload => GND);
4152 \UN1_LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
4153     operation_mode => "arithmetic",
4154     output_mode => "comb_only",
4155     synch_mode => "off",
4156      sum_lutc_input => "datac",
4157     lut_mask => "6688")
4158 port map (
4159 combout => UN1_LINE_COUNTER_SIG_COMBOUT(1),
4160 cout => UN1_LINE_COUNTER_SIG_COUT(1),
4161 dataa => D_SET_HSYNC_COUNTER_57,
4162 datab => LINE_COUNTER_SIG_0_0,
4163         devpor => devpor,
4164         devclrn => devclrn,
4165         clk => GND,
4166         datac => VCC,
4167         datad => VCC,
4168         aclr => GND,
4169         sclr => GND,
4170         sload => GND,
4171         ena => VCC,
4172         cin => GND,
4173         inverta => GND,
4174         aload => GND);
4175 \UN2_COLUMN_COUNTER_NEXT_9_\: stratix_lcell generic map (
4176     operation_mode => "normal",
4177     output_mode => "comb_only",
4178     synch_mode => "off",
4179      sum_lutc_input => "cin",
4180      cin_used => "true",
4181     lut_mask => "6c6c")
4182 port map (
4183 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
4184 dataa => COLUMN_COUNTER_SIG_31,
4185 datab => COLUMN_COUNTER_SIG_32,
4186 cin => UN2_COLUMN_COUNTER_NEXT_COUT(7),
4187         devpor => devpor,
4188         devclrn => devclrn,
4189         clk => GND,
4190         datac => VCC,
4191         datad => VCC,
4192         aclr => GND,
4193         sclr => GND,
4194         sload => GND,
4195         ena => VCC,
4196         inverta => GND,
4197         aload => GND);
4198 \UN2_COLUMN_COUNTER_NEXT_8_\: stratix_lcell generic map (
4199     operation_mode => "normal",
4200     output_mode => "comb_only",
4201     synch_mode => "off",
4202      sum_lutc_input => "cin",
4203      cin_used => "true",
4204     lut_mask => "5a5a")
4205 port map (
4206 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
4207 dataa => COLUMN_COUNTER_SIG_31,
4208 cin => UN2_COLUMN_COUNTER_NEXT_COUT(6),
4209         devpor => devpor,
4210         devclrn => devclrn,
4211         clk => GND,
4212         datab => VCC,
4213         datac => VCC,
4214         datad => VCC,
4215         aclr => GND,
4216         sclr => GND,
4217         sload => GND,
4218         ena => VCC,
4219         inverta => GND,
4220         aload => GND);
4221 \UN2_COLUMN_COUNTER_NEXT_7_\: stratix_lcell generic map (
4222     operation_mode => "arithmetic",
4223     output_mode => "comb_only",
4224     synch_mode => "off",
4225      sum_lutc_input => "cin",
4226      cin_used => "true",
4227     lut_mask => "6c80")
4228 port map (
4229 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
4230 cout => UN2_COLUMN_COUNTER_NEXT_COUT(7),
4231 dataa => COLUMN_COUNTER_SIG_29,
4232 datab => COLUMN_COUNTER_SIG_30,
4233 cin => UN2_COLUMN_COUNTER_NEXT_COUT(5),
4234         devpor => devpor,
4235         devclrn => devclrn,
4236         clk => GND,
4237         datac => VCC,
4238         datad => VCC,
4239         aclr => GND,
4240         sclr => GND,
4241         sload => GND,
4242         ena => VCC,
4243         inverta => GND,
4244         aload => GND);
4245 \UN2_COLUMN_COUNTER_NEXT_6_\: stratix_lcell generic map (
4246     operation_mode => "arithmetic",
4247     output_mode => "comb_only",
4248     synch_mode => "off",
4249      sum_lutc_input => "cin",
4250      cin_used => "true",
4251     lut_mask => "5a80")
4252 port map (
4253 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
4254 cout => UN2_COLUMN_COUNTER_NEXT_COUT(6),
4255 dataa => COLUMN_COUNTER_SIG_29,
4256 datab => COLUMN_COUNTER_SIG_30,
4257 cin => UN2_COLUMN_COUNTER_NEXT_COUT(4),
4258         devpor => devpor,
4259         devclrn => devclrn,
4260         clk => GND,
4261         datac => VCC,
4262         datad => VCC,
4263         aclr => GND,
4264         sclr => GND,
4265         sload => GND,
4266         ena => VCC,
4267         inverta => GND,
4268         aload => GND);
4269 \UN2_COLUMN_COUNTER_NEXT_5_\: stratix_lcell generic map (
4270     operation_mode => "arithmetic",
4271     output_mode => "comb_only",
4272     synch_mode => "off",
4273      sum_lutc_input => "cin",
4274      cin_used => "true",
4275     lut_mask => "6c80")
4276 port map (
4277 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
4278 cout => UN2_COLUMN_COUNTER_NEXT_COUT(5),
4279 dataa => COLUMN_COUNTER_SIG_27,
4280 datab => COLUMN_COUNTER_SIG_28,
4281 cin => UN2_COLUMN_COUNTER_NEXT_COUT(3),
4282         devpor => devpor,
4283         devclrn => devclrn,
4284         clk => GND,
4285         datac => VCC,
4286         datad => VCC,
4287         aclr => GND,
4288         sclr => GND,
4289         sload => GND,
4290         ena => VCC,
4291         inverta => GND,
4292         aload => GND);
4293 \UN2_COLUMN_COUNTER_NEXT_4_\: stratix_lcell generic map (
4294     operation_mode => "arithmetic",
4295     output_mode => "comb_only",
4296     synch_mode => "off",
4297      sum_lutc_input => "cin",
4298      cin_used => "true",
4299     lut_mask => "5a80")
4300 port map (
4301 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
4302 cout => UN2_COLUMN_COUNTER_NEXT_COUT(4),
4303 dataa => COLUMN_COUNTER_SIG_27,
4304 datab => COLUMN_COUNTER_SIG_28,
4305 cin => UN2_COLUMN_COUNTER_NEXT_COUT(2),
4306         devpor => devpor,
4307         devclrn => devclrn,
4308         clk => GND,
4309         datac => VCC,
4310         datad => VCC,
4311         aclr => GND,
4312         sclr => GND,
4313         sload => GND,
4314         ena => VCC,
4315         inverta => GND,
4316         aload => GND);
4317 \UN2_COLUMN_COUNTER_NEXT_3_\: stratix_lcell generic map (
4318     operation_mode => "arithmetic",
4319     output_mode => "comb_only",
4320     synch_mode => "off",
4321      sum_lutc_input => "cin",
4322      cin_used => "true",
4323     lut_mask => "6c80")
4324 port map (
4325 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
4326 cout => UN2_COLUMN_COUNTER_NEXT_COUT(3),
4327 dataa => COLUMN_COUNTER_SIG_25,
4328 datab => COLUMN_COUNTER_SIG_26,
4329 cin => UN2_COLUMN_COUNTER_NEXT_COUT(1),
4330         devpor => devpor,
4331         devclrn => devclrn,
4332         clk => GND,
4333         datac => VCC,
4334         datad => VCC,
4335         aclr => GND,
4336         sclr => GND,
4337         sload => GND,
4338         ena => VCC,
4339         inverta => GND,
4340         aload => GND);
4341 \UN2_COLUMN_COUNTER_NEXT_2_\: stratix_lcell generic map (
4342     operation_mode => "arithmetic",
4343     output_mode => "comb_only",
4344     synch_mode => "off",
4345      sum_lutc_input => "cin",
4346      cin_used => "true",
4347     lut_mask => "5a80")
4348 port map (
4349 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
4350 cout => UN2_COLUMN_COUNTER_NEXT_COUT(2),
4351 dataa => COLUMN_COUNTER_SIG_25,
4352 datab => COLUMN_COUNTER_SIG_26,
4353 cin => UN2_COLUMN_COUNTER_NEXT_COUT(0),
4354         devpor => devpor,
4355         devclrn => devclrn,
4356         clk => GND,
4357         datac => VCC,
4358         datad => VCC,
4359         aclr => GND,
4360         sclr => GND,
4361         sload => GND,
4362         ena => VCC,
4363         inverta => GND,
4364         aload => GND);
4365 \UN2_COLUMN_COUNTER_NEXT_1_\: stratix_lcell generic map (
4366     operation_mode => "arithmetic",
4367     output_mode => "comb_only",
4368     synch_mode => "off",
4369      sum_lutc_input => "datac",
4370     lut_mask => "6688")
4371 port map (
4372 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
4373 cout => UN2_COLUMN_COUNTER_NEXT_COUT(1),
4374 dataa => COLUMN_COUNTER_SIG_23,
4375 datab => COLUMN_COUNTER_SIG_24,
4376         devpor => devpor,
4377         devclrn => devclrn,
4378         clk => GND,
4379         datac => VCC,
4380         datad => VCC,
4381         aclr => GND,
4382         sclr => GND,
4383         sload => GND,
4384         ena => VCC,
4385         cin => GND,
4386         inverta => GND,
4387         aload => GND);
4388 \UN2_COLUMN_COUNTER_NEXT_0_\: stratix_lcell generic map (
4389     operation_mode => "arithmetic",
4390     output_mode => "comb_only",
4391     synch_mode => "off",
4392      sum_lutc_input => "datac",
4393     lut_mask => "5588")
4394 port map (
4395 cout => UN2_COLUMN_COUNTER_NEXT_COUT(0),
4396 dataa => COLUMN_COUNTER_SIG_23,
4397 datab => COLUMN_COUNTER_SIG_24,
4398         devpor => devpor,
4399         devclrn => devclrn,
4400         clk => GND,
4401         datac => VCC,
4402         datad => VCC,
4403         aclr => GND,
4404         sclr => GND,
4405         sload => GND,
4406         ena => VCC,
4407         cin => GND,
4408         inverta => GND,
4409         aload => GND);
4410 VCC <= '1';
4411 GND <= '0';
4412 LINE_COUNTER_NEXT_0_SQMUXA_1_1_I <= not LINE_COUNTER_NEXT_0_SQMUXA_1_1;
4413 COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I <= not COLUMN_COUNTER_NEXT_0_SQMUXA_1_1;
4414 G_16_I_I <= not G_16_I;
4415 UN9_VSYNC_COUNTERLT9_I <= not UN9_VSYNC_COUNTERLT9;
4416 G_2_I_I <= not G_2_I;
4417 UN9_HSYNC_COUNTERLT9_I <= not UN9_HSYNC_COUNTERLT9;
4418 line_counter_sig_0 <= LINE_COUNTER_SIG_0_0;
4419 line_counter_sig_1 <= LINE_COUNTER_SIG_1_0;
4420 line_counter_sig_2 <= LINE_COUNTER_SIG_2_0;
4421 line_counter_sig_3 <= LINE_COUNTER_SIG_3_0;
4422 line_counter_sig_4 <= LINE_COUNTER_SIG_4_0;
4423 line_counter_sig_5 <= LINE_COUNTER_SIG_5_0;
4424 line_counter_sig_6 <= LINE_COUNTER_SIG_6_0;
4425 line_counter_sig_7 <= LINE_COUNTER_SIG_7_0;
4426 line_counter_sig_8 <= LINE_COUNTER_SIG_8_0;
4427 vsync_state_2 <= VSYNC_STATE_9;
4428 vsync_state_5 <= VSYNC_STATE_10;
4429 vsync_state_3 <= VSYNC_STATE_11;
4430 vsync_state_6 <= VSYNC_STATE_12;
4431 vsync_state_4 <= VSYNC_STATE_13;
4432 vsync_state_1 <= VSYNC_STATE_14;
4433 vsync_state_0 <= VSYNC_STATE_15;
4434 hsync_state_2 <= HSYNC_STATE_16;
4435 hsync_state_4 <= HSYNC_STATE_17;
4436 hsync_state_0 <= HSYNC_STATE_18;
4437 hsync_state_5 <= HSYNC_STATE_19;
4438 hsync_state_1 <= HSYNC_STATE_20;
4439 hsync_state_3 <= HSYNC_STATE_21;
4440 hsync_state_6 <= HSYNC_STATE_22;
4441 column_counter_sig_0 <= COLUMN_COUNTER_SIG_23;
4442 column_counter_sig_1 <= COLUMN_COUNTER_SIG_24;
4443 column_counter_sig_2 <= COLUMN_COUNTER_SIG_25;
4444 column_counter_sig_3 <= COLUMN_COUNTER_SIG_26;
4445 column_counter_sig_4 <= COLUMN_COUNTER_SIG_27;
4446 column_counter_sig_5 <= COLUMN_COUNTER_SIG_28;
4447 column_counter_sig_6 <= COLUMN_COUNTER_SIG_29;
4448 column_counter_sig_7 <= COLUMN_COUNTER_SIG_30;
4449 column_counter_sig_8 <= COLUMN_COUNTER_SIG_31;
4450 column_counter_sig_9 <= COLUMN_COUNTER_SIG_32;
4451 vsync_counter_9 <= VSYNC_COUNTER_33;
4452 vsync_counter_8 <= VSYNC_COUNTER_34;
4453 vsync_counter_7 <= VSYNC_COUNTER_35;
4454 vsync_counter_6 <= VSYNC_COUNTER_36;
4455 vsync_counter_5 <= VSYNC_COUNTER_37;
4456 vsync_counter_4 <= VSYNC_COUNTER_38;
4457 vsync_counter_3 <= VSYNC_COUNTER_39;
4458 vsync_counter_2 <= VSYNC_COUNTER_40;
4459 vsync_counter_1 <= VSYNC_COUNTER_41;
4460 vsync_counter_0 <= VSYNC_COUNTER_42;
4461 hsync_counter_9 <= HSYNC_COUNTER_43;
4462 hsync_counter_8 <= HSYNC_COUNTER_44;
4463 hsync_counter_7 <= HSYNC_COUNTER_45;
4464 hsync_counter_6 <= HSYNC_COUNTER_46;
4465 hsync_counter_5 <= HSYNC_COUNTER_47;
4466 hsync_counter_4 <= HSYNC_COUNTER_48;
4467 hsync_counter_3 <= HSYNC_COUNTER_49;
4468 hsync_counter_2 <= HSYNC_COUNTER_50;
4469 hsync_counter_1 <= HSYNC_COUNTER_51;
4470 hsync_counter_0 <= HSYNC_COUNTER_52;
4471 d_set_vsync_counter <= D_SET_VSYNC_COUNTER_53;
4472 v_sync <= V_SYNC_54;
4473 h_sync <= H_SYNC_55;
4474 un6_dly_counter_0_x <= UN6_DLY_COUNTER_0_X_56;
4475 d_set_hsync_counter <= D_SET_HSYNC_COUNTER_57;
4476 end beh;
4477
4478 --
4479 library ieee, stratix;
4480 use ieee.std_logic_1164.all;
4481 use ieee.numeric_std.all;
4482 library synplify;
4483 use synplify.components.all;
4484 use stratix.stratix_components.all;
4485
4486 entity vga is
4487 port(
4488 clk_pin :  in std_logic;
4489 reset_pin :  in std_logic;
4490 r0_pin :  out std_logic;
4491 r1_pin :  out std_logic;
4492 r2_pin :  out std_logic;
4493 g0_pin :  out std_logic;
4494 g1_pin :  out std_logic;
4495 g2_pin :  out std_logic;
4496 b0_pin :  out std_logic;
4497 b1_pin :  out std_logic;
4498 hsync_pin :  out std_logic;
4499 vsync_pin :  out std_logic;
4500 seven_seg_pin : out std_logic_vector(13 downto 0);
4501 d_hsync :  out std_logic;
4502 d_vsync :  out std_logic;
4503 d_column_counter : out std_logic_vector(9 downto 0);
4504 d_line_counter : out std_logic_vector(8 downto 0);
4505 d_set_column_counter :  out std_logic;
4506 d_set_line_counter :  out std_logic;
4507 d_hsync_counter : out std_logic_vector(9 downto 0);
4508 d_vsync_counter : out std_logic_vector(9 downto 0);
4509 d_set_hsync_counter :  out std_logic;
4510 d_set_vsync_counter :  out std_logic;
4511 d_h_enable :  out std_logic;
4512 d_v_enable :  out std_logic;
4513 d_r :  out std_logic;
4514 d_g :  out std_logic;
4515 d_b :  out std_logic;
4516 d_hsync_state : out std_logic_vector(0 to 6);
4517 d_vsync_state : out std_logic_vector(0 to 6);
4518 d_state_clk :  out std_logic;
4519 d_toggle :  out std_logic;
4520 d_toggle_counter : out std_logic_vector(24 downto 0));
4521 end vga;
4522
4523 architecture beh of vga is
4524 signal devclrn : std_logic := '1';
4525 signal devpor : std_logic := '1';
4526 signal devoe : std_logic := '0';
4527 signal DLY_COUNTER : std_logic_vector(1 downto 0);
4528 signal \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\ : std_logic_vector(9 downto 0);
4529 signal \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\ : std_logic_vector(8 downto 0);
4530 signal \VGA_DRIVER_UNIT.HSYNC_COUNTER\ : std_logic_vector(9 downto 0);
4531 signal \VGA_DRIVER_UNIT.VSYNC_COUNTER\ : std_logic_vector(9 downto 0);
4532 signal \VGA_DRIVER_UNIT.HSYNC_STATE\ : std_logic_vector(6 downto 0);
4533 signal \VGA_DRIVER_UNIT.VSYNC_STATE\ : std_logic_vector(6 downto 0);
4534 signal \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\ : std_logic_vector(24 downto 0);
4535 signal SEVEN_SEG_PINZ : std_logic_vector(13 downto 0);
4536 signal D_COLUMN_COUNTERZ : std_logic_vector(9 downto 0);
4537 signal D_LINE_COUNTERZ : std_logic_vector(8 downto 0);
4538 signal D_HSYNC_COUNTERZ : std_logic_vector(9 downto 0);
4539 signal D_VSYNC_COUNTERZ : std_logic_vector(9 downto 0);
4540 signal D_HSYNC_STATEZ : std_logic_vector(6 downto 0);
4541 signal D_VSYNC_STATEZ : std_logic_vector(6 downto 0);
4542 signal D_TOGGLE_COUNTERZ : std_logic_vector(24 downto 0);
4543 signal VCC : std_logic ;
4544 signal GND : std_logic ;
4545 signal \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\ : std_logic ;
4546 signal \VGA_DRIVER_UNIT.H_SYNC\ : std_logic ;
4547 signal \VGA_DRIVER_UNIT.V_SYNC\ : std_logic ;
4548 signal \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\ : std_logic ;
4549 signal \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\ : std_logic ;
4550 signal \VGA_DRIVER_UNIT.H_ENABLE_SIG\ : std_logic ;
4551 signal \VGA_DRIVER_UNIT.V_ENABLE_SIG\ : std_logic ;
4552 signal \VGA_CONTROL_UNIT.R\ : std_logic ;
4553 signal \VGA_CONTROL_UNIT.G\ : std_logic ;
4554 signal \VGA_CONTROL_UNIT.B\ : std_logic ;
4555 signal G_33 : std_logic ;
4556 signal \VGA_CONTROL_UNIT.TOGGLE_SIG\ : std_logic ;
4557 signal CLK_PIN_C : std_logic ;
4558 signal RESET_PIN_C : std_logic ;
4559 signal CLK_PIN_INTERNAL : std_logic ;
4560 signal RESET_PIN_INTERNAL : std_logic ;
4561 signal N_1 : std_logic ;
4562 signal N_2 : std_logic ;
4563 signal N_84_0 : std_logic ;
4564 signal N_85_0 : std_logic ;
4565 signal N_86_0 : std_logic ;
4566 signal N_87_0 : std_logic ;
4567 signal N_88_0 : std_logic ;
4568 signal N_89_0 : std_logic ;
4569 signal N_90_0 : std_logic ;
4570 signal N_91_0 : std_logic ;
4571 signal N_92_0 : std_logic ;
4572 signal N_93_0 : std_logic ;
4573 signal N_94_0 : std_logic ;
4574 signal N_95_0 : std_logic ;
4575 signal N_96_0 : std_logic ;
4576 signal N_97_0 : std_logic ;
4577 signal N_98_0 : std_logic ;
4578 signal N_99_0 : std_logic ;
4579 signal N_100_0 : std_logic ;
4580 signal N_101_0 : std_logic ;
4581 signal N_102_0 : std_logic ;
4582 signal N_103_0 : std_logic ;
4583 signal N_104_0 : std_logic ;
4584 signal N_105_0 : std_logic ;
4585 signal N_106_0 : std_logic ;
4586 signal N_107_0 : std_logic ;
4587 signal N_108_0 : std_logic ;
4588 signal N_109_0 : std_logic ;
4589 signal N_110_0 : std_logic ;
4590 signal N_111_0 : std_logic ;
4591 signal N_112_0 : std_logic ;
4592 signal N_113_0 : std_logic ;
4593 signal N_114_0 : std_logic ;
4594 signal N_115_0 : std_logic ;
4595 signal N_116_0 : std_logic ;
4596 signal N_117_0 : std_logic ;
4597 signal N_118 : std_logic ;
4598 signal N_119 : std_logic ;
4599 signal N_120 : std_logic ;
4600 signal N_121 : std_logic ;
4601 signal N_122 : std_logic ;
4602 signal N_123 : std_logic ;
4603 signal N_124 : std_logic ;
4604 signal N_125 : std_logic ;
4605 signal N_126 : std_logic ;
4606 signal N_127 : std_logic ;
4607 signal N_128 : std_logic ;
4608 signal N_129 : std_logic ;
4609 signal N_130 : std_logic ;
4610 signal N_131 : std_logic ;
4611 signal N_132 : std_logic ;
4612 signal N_133 : std_logic ;
4613 signal N_134 : std_logic ;
4614 signal N_135 : std_logic ;
4615 signal N_136 : std_logic ;
4616 signal N_137 : std_logic ;
4617 signal N_138 : std_logic ;
4618 signal N_139 : std_logic ;
4619 signal N_140 : std_logic ;
4620 signal N_141 : std_logic ;
4621 signal N_142 : std_logic ;
4622 signal N_143 : std_logic ;
4623 signal N_144 : std_logic ;
4624 signal N_145 : std_logic ;
4625 signal N_146 : std_logic ;
4626 signal N_147 : std_logic ;
4627 signal N_148 : std_logic ;
4628 signal N_149 : std_logic ;
4629 signal N_150 : std_logic ;
4630 signal N_151 : std_logic ;
4631 signal N_152 : std_logic ;
4632 signal N_153 : std_logic ;
4633 signal N_154 : std_logic ;
4634 signal N_155 : std_logic ;
4635 signal N_156 : std_logic ;
4636 signal N_157 : std_logic ;
4637 signal N_158 : std_logic ;
4638 signal N_159 : std_logic ;
4639 signal N_160 : std_logic ;
4640 signal N_161 : std_logic ;
4641 signal N_162 : std_logic ;
4642 signal N_163 : std_logic ;
4643 signal N_164 : std_logic ;
4644 signal N_165 : std_logic ;
4645 signal N_166 : std_logic ;
4646 signal N_167 : std_logic ;
4647 signal N_168 : std_logic ;
4648 signal N_169 : std_logic ;
4649 signal N_170 : std_logic ;
4650 signal N_171 : std_logic ;
4651 signal N_172 : std_logic ;
4652 signal N_173 : std_logic ;
4653 signal N_174 : std_logic ;
4654 signal N_175 : std_logic ;
4655 signal N_176 : std_logic ;
4656 signal N_177 : std_logic ;
4657 signal N_178 : std_logic ;
4658 signal N_179 : std_logic ;
4659 signal N_180 : std_logic ;
4660 signal N_181 : std_logic ;
4661 signal N_182 : std_logic ;
4662 signal N_183 : std_logic ;
4663 signal N_184 : std_logic ;
4664 signal N_185 : std_logic ;
4665 signal N_186 : std_logic ;
4666 signal N_187 : std_logic ;
4667 signal N_188 : std_logic ;
4668 signal N_189 : std_logic ;
4669 signal N_190 : std_logic ;
4670 signal N_191 : std_logic ;
4671 signal N_192 : std_logic ;
4672 signal N_193 : std_logic ;
4673 signal N_194 : std_logic ;
4674 signal N_195 : std_logic ;
4675 signal N_196 : std_logic ;
4676 signal N_197 : std_logic ;
4677 signal N_198 : std_logic ;
4678 signal R0_PINZ : std_logic ;
4679 signal R1_PINZ : std_logic ;
4680 signal R2_PINZ : std_logic ;
4681 signal G0_PINZ : std_logic ;
4682 signal G1_PINZ : std_logic ;
4683 signal G2_PINZ : std_logic ;
4684 signal B0_PINZ : std_logic ;
4685 signal B1_PINZ : std_logic ;
4686 signal HSYNC_PINZ : std_logic ;
4687 signal VSYNC_PINZ : std_logic ;
4688 signal D_HSYNCZ : std_logic ;
4689 signal D_VSYNCZ : std_logic ;
4690 signal D_SET_COLUMN_COUNTERZ : std_logic ;
4691 signal D_SET_LINE_COUNTERZ : std_logic ;
4692 signal D_SET_HSYNC_COUNTERZ : std_logic ;
4693 signal D_SET_VSYNC_COUNTERZ : std_logic ;
4694 signal D_H_ENABLEZ : std_logic ;
4695 signal D_V_ENABLEZ : std_logic ;
4696 signal D_RZ : std_logic ;
4697 signal D_GZ : std_logic ;
4698 signal D_BZ : std_logic ;
4699 signal D_STATE_CLKZ : std_logic ;
4700 signal D_TOGGLEZ : std_logic ;
4701 component vga_driver
4702 port(
4703   line_counter_sig_0 :  out std_logic;
4704   line_counter_sig_1 :  out std_logic;
4705   line_counter_sig_2 :  out std_logic;
4706   line_counter_sig_3 :  out std_logic;
4707   line_counter_sig_4 :  out std_logic;
4708   line_counter_sig_5 :  out std_logic;
4709   line_counter_sig_6 :  out std_logic;
4710   line_counter_sig_7 :  out std_logic;
4711   line_counter_sig_8 :  out std_logic;
4712   dly_counter_1 :  in std_logic;
4713   dly_counter_0 :  in std_logic;
4714   vsync_state_2 :  out std_logic;
4715   vsync_state_5 :  out std_logic;
4716   vsync_state_3 :  out std_logic;
4717   vsync_state_6 :  out std_logic;
4718   vsync_state_4 :  out std_logic;
4719   vsync_state_1 :  out std_logic;
4720   vsync_state_0 :  out std_logic;
4721   hsync_state_2 :  out std_logic;
4722   hsync_state_4 :  out std_logic;
4723   hsync_state_0 :  out std_logic;
4724   hsync_state_5 :  out std_logic;
4725   hsync_state_1 :  out std_logic;
4726   hsync_state_3 :  out std_logic;
4727   hsync_state_6 :  out std_logic;
4728   column_counter_sig_0 :  out std_logic;
4729   column_counter_sig_1 :  out std_logic;
4730   column_counter_sig_2 :  out std_logic;
4731   column_counter_sig_3 :  out std_logic;
4732   column_counter_sig_4 :  out std_logic;
4733   column_counter_sig_5 :  out std_logic;
4734   column_counter_sig_6 :  out std_logic;
4735   column_counter_sig_7 :  out std_logic;
4736   column_counter_sig_8 :  out std_logic;
4737   column_counter_sig_9 :  out std_logic;
4738   vsync_counter_9 :  out std_logic;
4739   vsync_counter_8 :  out std_logic;
4740   vsync_counter_7 :  out std_logic;
4741   vsync_counter_6 :  out std_logic;
4742   vsync_counter_5 :  out std_logic;
4743   vsync_counter_4 :  out std_logic;
4744   vsync_counter_3 :  out std_logic;
4745   vsync_counter_2 :  out std_logic;
4746   vsync_counter_1 :  out std_logic;
4747   vsync_counter_0 :  out std_logic;
4748   hsync_counter_9 :  out std_logic;
4749   hsync_counter_8 :  out std_logic;
4750   hsync_counter_7 :  out std_logic;
4751   hsync_counter_6 :  out std_logic;
4752   hsync_counter_5 :  out std_logic;
4753   hsync_counter_4 :  out std_logic;
4754   hsync_counter_3 :  out std_logic;
4755   hsync_counter_2 :  out std_logic;
4756   hsync_counter_1 :  out std_logic;
4757   hsync_counter_0 :  out std_logic;
4758   d_set_vsync_counter :  out std_logic;
4759   v_sync :  out std_logic;
4760   h_sync :  out std_logic;
4761   h_enable_sig :  out std_logic;
4762   v_enable_sig :  out std_logic;
4763   reset_pin_c :  in std_logic;
4764   un6_dly_counter_0_x :  out std_logic;
4765   d_set_hsync_counter :  out std_logic;
4766   clk_pin_c :  in std_logic  );
4767 end component;
4768 component vga_control
4769 port(
4770   line_counter_sig_0 :  in std_logic;
4771   line_counter_sig_2 :  in std_logic;
4772   line_counter_sig_1 :  in std_logic;
4773   line_counter_sig_3 :  in std_logic;
4774   line_counter_sig_6 :  in std_logic;
4775   line_counter_sig_5 :  in std_logic;
4776   line_counter_sig_4 :  in std_logic;
4777   line_counter_sig_7 :  in std_logic;
4778   line_counter_sig_8 :  in std_logic;
4779   column_counter_sig_0 :  in std_logic;
4780   column_counter_sig_1 :  in std_logic;
4781   column_counter_sig_2 :  in std_logic;
4782   column_counter_sig_8 :  in std_logic;
4783   column_counter_sig_3 :  in std_logic;
4784   column_counter_sig_5 :  in std_logic;
4785   column_counter_sig_4 :  in std_logic;
4786   column_counter_sig_9 :  in std_logic;
4787   column_counter_sig_7 :  in std_logic;
4788   column_counter_sig_6 :  in std_logic;
4789   toggle_counter_sig_0 :  out std_logic;
4790   toggle_counter_sig_1 :  out std_logic;
4791   toggle_counter_sig_2 :  out std_logic;
4792   toggle_counter_sig_3 :  out std_logic;
4793   toggle_counter_sig_4 :  out std_logic;
4794   toggle_counter_sig_5 :  out std_logic;
4795   toggle_counter_sig_6 :  out std_logic;
4796   toggle_counter_sig_7 :  out std_logic;
4797   toggle_counter_sig_8 :  out std_logic;
4798   toggle_counter_sig_9 :  out std_logic;
4799   toggle_counter_sig_10 :  out std_logic;
4800   toggle_counter_sig_11 :  out std_logic;
4801   toggle_counter_sig_12 :  out std_logic;
4802   toggle_counter_sig_13 :  out std_logic;
4803   toggle_counter_sig_14 :  out std_logic;
4804   toggle_counter_sig_15 :  out std_logic;
4805   toggle_counter_sig_16 :  out std_logic;
4806   toggle_counter_sig_17 :  out std_logic;
4807   toggle_counter_sig_18 :  out std_logic;
4808   toggle_counter_sig_19 :  out std_logic;
4809   toggle_counter_sig_20 :  out std_logic;
4810   toggle_counter_sig_21 :  out std_logic;
4811   toggle_counter_sig_22 :  out std_logic;
4812   toggle_counter_sig_23 :  out std_logic;
4813   toggle_counter_sig_24 :  out std_logic;
4814   h_enable_sig :  in std_logic;
4815   g :  out std_logic;
4816   b :  out std_logic;
4817   v_enable_sig :  in std_logic;
4818   r :  out std_logic;
4819   toggle_sig :  out std_logic;
4820   un6_dly_counter_0_x :  in std_logic;
4821   clk_pin_c :  in std_logic  );
4822 end component;
4823 begin
4824 VCC <= '1';
4825 GND <= '0';
4826 \DLY_COUNTER_1_\: stratix_lcell generic map (
4827     operation_mode => "normal",
4828     output_mode => "reg_only",
4829     synch_mode => "off",
4830      sum_lutc_input => "datac",
4831     lut_mask => "a8a8")
4832 port map (
4833 regout => DLY_COUNTER(1),
4834 clk => CLK_PIN_C,
4835 dataa => RESET_PIN_C,
4836 datab => DLY_COUNTER(0),
4837 datac => DLY_COUNTER(1),
4838         devpor => devpor,
4839         devclrn => devclrn,
4840         datad => VCC,
4841         aclr => GND,
4842         sclr => GND,
4843         sload => GND,
4844         ena => VCC,
4845         cin => GND,
4846         inverta => GND,
4847         aload => GND);
4848 \DLY_COUNTER_0_\: stratix_lcell generic map (
4849     operation_mode => "normal",
4850     output_mode => "reg_only",
4851     synch_mode => "off",
4852      sum_lutc_input => "datac",
4853     lut_mask => "a2a2")
4854 port map (
4855 regout => DLY_COUNTER(0),
4856 clk => CLK_PIN_C,
4857 dataa => RESET_PIN_C,
4858 datab => DLY_COUNTER(0),
4859 datac => DLY_COUNTER(1),
4860         devpor => devpor,
4861         devclrn => devclrn,
4862         datad => VCC,
4863         aclr => GND,
4864         sclr => GND,
4865         sload => GND,
4866         ena => VCC,
4867         cin => GND,
4868         inverta => GND,
4869         aload => GND);
4870 RESET_PIN_IN: stratix_io generic map (
4871     operation_mode => "input"
4872     )
4873 port map (
4874 padio => N_2,
4875 combout => RESET_PIN_C,
4876 oe => GND,
4877         devpor => devpor,
4878         devclrn => devclrn,
4879         devoe => devoe,
4880         outclkena => VCC,
4881         inclkena => VCC,
4882         areset => GND,
4883         sreset => GND);
4884 CLK_PIN_IN: stratix_io generic map (
4885     operation_mode => "input"
4886     )
4887 port map (
4888 padio => N_1,
4889 combout => CLK_PIN_C,
4890 oe => GND,
4891         devpor => devpor,
4892         devclrn => devclrn,
4893         devoe => devoe,
4894         outclkena => VCC,
4895         inclkena => VCC,
4896         areset => GND,
4897         sreset => GND);
4898 \D_TOGGLE_COUNTER_OUT_24_\: stratix_io generic map (
4899     operation_mode => "output"
4900     )
4901 port map (
4902 padio => D_TOGGLE_COUNTERZ(24),
4903 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24),
4904 oe => VCC,
4905         devpor => devpor,
4906         devclrn => devclrn,
4907         devoe => devoe,
4908         outclkena => VCC,
4909         inclkena => VCC,
4910         areset => GND,
4911         sreset => GND);
4912 \D_TOGGLE_COUNTER_OUT_23_\: stratix_io generic map (
4913     operation_mode => "output"
4914     )
4915 port map (
4916 padio => D_TOGGLE_COUNTERZ(23),
4917 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23),
4918 oe => VCC,
4919         devpor => devpor,
4920         devclrn => devclrn,
4921         devoe => devoe,
4922         outclkena => VCC,
4923         inclkena => VCC,
4924         areset => GND,
4925         sreset => GND);
4926 \D_TOGGLE_COUNTER_OUT_22_\: stratix_io generic map (
4927     operation_mode => "output"
4928     )
4929 port map (
4930 padio => D_TOGGLE_COUNTERZ(22),
4931 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22),
4932 oe => VCC,
4933         devpor => devpor,
4934         devclrn => devclrn,
4935         devoe => devoe,
4936         outclkena => VCC,
4937         inclkena => VCC,
4938         areset => GND,
4939         sreset => GND);
4940 \D_TOGGLE_COUNTER_OUT_21_\: stratix_io generic map (
4941     operation_mode => "output"
4942     )
4943 port map (
4944 padio => D_TOGGLE_COUNTERZ(21),
4945 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21),
4946 oe => VCC,
4947         devpor => devpor,
4948         devclrn => devclrn,
4949         devoe => devoe,
4950         outclkena => VCC,
4951         inclkena => VCC,
4952         areset => GND,
4953         sreset => GND);
4954 \D_TOGGLE_COUNTER_OUT_20_\: stratix_io generic map (
4955     operation_mode => "output"
4956     )
4957 port map (
4958 padio => D_TOGGLE_COUNTERZ(20),
4959 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20),
4960 oe => VCC,
4961         devpor => devpor,
4962         devclrn => devclrn,
4963         devoe => devoe,
4964         outclkena => VCC,
4965         inclkena => VCC,
4966         areset => GND,
4967         sreset => GND);
4968 \D_TOGGLE_COUNTER_OUT_19_\: stratix_io generic map (
4969     operation_mode => "output"
4970     )
4971 port map (
4972 padio => D_TOGGLE_COUNTERZ(19),
4973 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19),
4974 oe => VCC,
4975         devpor => devpor,
4976         devclrn => devclrn,
4977         devoe => devoe,
4978         outclkena => VCC,
4979         inclkena => VCC,
4980         areset => GND,
4981         sreset => GND);
4982 \D_TOGGLE_COUNTER_OUT_18_\: stratix_io generic map (
4983     operation_mode => "output"
4984     )
4985 port map (
4986 padio => D_TOGGLE_COUNTERZ(18),
4987 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18),
4988 oe => VCC,
4989         devpor => devpor,
4990         devclrn => devclrn,
4991         devoe => devoe,
4992         outclkena => VCC,
4993         inclkena => VCC,
4994         areset => GND,
4995         sreset => GND);
4996 \D_TOGGLE_COUNTER_OUT_17_\: stratix_io generic map (
4997     operation_mode => "output"
4998     )
4999 port map (
5000 padio => D_TOGGLE_COUNTERZ(17),
5001 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17),
5002 oe => VCC,
5003         devpor => devpor,
5004         devclrn => devclrn,
5005         devoe => devoe,
5006         outclkena => VCC,
5007         inclkena => VCC,
5008         areset => GND,
5009         sreset => GND);
5010 \D_TOGGLE_COUNTER_OUT_16_\: stratix_io generic map (
5011     operation_mode => "output"
5012     )
5013 port map (
5014 padio => D_TOGGLE_COUNTERZ(16),
5015 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16),
5016 oe => VCC,
5017         devpor => devpor,
5018         devclrn => devclrn,
5019         devoe => devoe,
5020         outclkena => VCC,
5021         inclkena => VCC,
5022         areset => GND,
5023         sreset => GND);
5024 \D_TOGGLE_COUNTER_OUT_15_\: stratix_io generic map (
5025     operation_mode => "output"
5026     )
5027 port map (
5028 padio => D_TOGGLE_COUNTERZ(15),
5029 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15),
5030 oe => VCC,
5031         devpor => devpor,
5032         devclrn => devclrn,
5033         devoe => devoe,
5034         outclkena => VCC,
5035         inclkena => VCC,
5036         areset => GND,
5037         sreset => GND);
5038 \D_TOGGLE_COUNTER_OUT_14_\: stratix_io generic map (
5039     operation_mode => "output"
5040     )
5041 port map (
5042 padio => D_TOGGLE_COUNTERZ(14),
5043 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14),
5044 oe => VCC,
5045         devpor => devpor,
5046         devclrn => devclrn,
5047         devoe => devoe,
5048         outclkena => VCC,
5049         inclkena => VCC,
5050         areset => GND,
5051         sreset => GND);
5052 \D_TOGGLE_COUNTER_OUT_13_\: stratix_io generic map (
5053     operation_mode => "output"
5054     )
5055 port map (
5056 padio => D_TOGGLE_COUNTERZ(13),
5057 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13),
5058 oe => VCC,
5059         devpor => devpor,
5060         devclrn => devclrn,
5061         devoe => devoe,
5062         outclkena => VCC,
5063         inclkena => VCC,
5064         areset => GND,
5065         sreset => GND);
5066 \D_TOGGLE_COUNTER_OUT_12_\: stratix_io generic map (
5067     operation_mode => "output"
5068     )
5069 port map (
5070 padio => D_TOGGLE_COUNTERZ(12),
5071 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12),
5072 oe => VCC,
5073         devpor => devpor,
5074         devclrn => devclrn,
5075         devoe => devoe,
5076         outclkena => VCC,
5077         inclkena => VCC,
5078         areset => GND,
5079         sreset => GND);
5080 \D_TOGGLE_COUNTER_OUT_11_\: stratix_io generic map (
5081     operation_mode => "output"
5082     )
5083 port map (
5084 padio => D_TOGGLE_COUNTERZ(11),
5085 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11),
5086 oe => VCC,
5087         devpor => devpor,
5088         devclrn => devclrn,
5089         devoe => devoe,
5090         outclkena => VCC,
5091         inclkena => VCC,
5092         areset => GND,
5093         sreset => GND);
5094 \D_TOGGLE_COUNTER_OUT_10_\: stratix_io generic map (
5095     operation_mode => "output"
5096     )
5097 port map (
5098 padio => D_TOGGLE_COUNTERZ(10),
5099 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10),
5100 oe => VCC,
5101         devpor => devpor,
5102         devclrn => devclrn,
5103         devoe => devoe,
5104         outclkena => VCC,
5105         inclkena => VCC,
5106         areset => GND,
5107         sreset => GND);
5108 \D_TOGGLE_COUNTER_OUT_9_\: stratix_io generic map (
5109     operation_mode => "output"
5110     )
5111 port map (
5112 padio => D_TOGGLE_COUNTERZ(9),
5113 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9),
5114 oe => VCC,
5115         devpor => devpor,
5116         devclrn => devclrn,
5117         devoe => devoe,
5118         outclkena => VCC,
5119         inclkena => VCC,
5120         areset => GND,
5121         sreset => GND);
5122 \D_TOGGLE_COUNTER_OUT_8_\: stratix_io generic map (
5123     operation_mode => "output"
5124     )
5125 port map (
5126 padio => D_TOGGLE_COUNTERZ(8),
5127 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8),
5128 oe => VCC,
5129         devpor => devpor,
5130         devclrn => devclrn,
5131         devoe => devoe,
5132         outclkena => VCC,
5133         inclkena => VCC,
5134         areset => GND,
5135         sreset => GND);
5136 \D_TOGGLE_COUNTER_OUT_7_\: stratix_io generic map (
5137     operation_mode => "output"
5138     )
5139 port map (
5140 padio => D_TOGGLE_COUNTERZ(7),
5141 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7),
5142 oe => VCC,
5143         devpor => devpor,
5144         devclrn => devclrn,
5145         devoe => devoe,
5146         outclkena => VCC,
5147         inclkena => VCC,
5148         areset => GND,
5149         sreset => GND);
5150 \D_TOGGLE_COUNTER_OUT_6_\: stratix_io generic map (
5151     operation_mode => "output"
5152     )
5153 port map (
5154 padio => D_TOGGLE_COUNTERZ(6),
5155 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6),
5156 oe => VCC,
5157         devpor => devpor,
5158         devclrn => devclrn,
5159         devoe => devoe,
5160         outclkena => VCC,
5161         inclkena => VCC,
5162         areset => GND,
5163         sreset => GND);
5164 \D_TOGGLE_COUNTER_OUT_5_\: stratix_io generic map (
5165     operation_mode => "output"
5166     )
5167 port map (
5168 padio => D_TOGGLE_COUNTERZ(5),
5169 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5),
5170 oe => VCC,
5171         devpor => devpor,
5172         devclrn => devclrn,
5173         devoe => devoe,
5174         outclkena => VCC,
5175         inclkena => VCC,
5176         areset => GND,
5177         sreset => GND);
5178 \D_TOGGLE_COUNTER_OUT_4_\: stratix_io generic map (
5179     operation_mode => "output"
5180     )
5181 port map (
5182 padio => D_TOGGLE_COUNTERZ(4),
5183 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4),
5184 oe => VCC,
5185         devpor => devpor,
5186         devclrn => devclrn,
5187         devoe => devoe,
5188         outclkena => VCC,
5189         inclkena => VCC,
5190         areset => GND,
5191         sreset => GND);
5192 \D_TOGGLE_COUNTER_OUT_3_\: stratix_io generic map (
5193     operation_mode => "output"
5194     )
5195 port map (
5196 padio => D_TOGGLE_COUNTERZ(3),
5197 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3),
5198 oe => VCC,
5199         devpor => devpor,
5200         devclrn => devclrn,
5201         devoe => devoe,
5202         outclkena => VCC,
5203         inclkena => VCC,
5204         areset => GND,
5205         sreset => GND);
5206 \D_TOGGLE_COUNTER_OUT_2_\: stratix_io generic map (
5207     operation_mode => "output"
5208     )
5209 port map (
5210 padio => D_TOGGLE_COUNTERZ(2),
5211 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2),
5212 oe => VCC,
5213         devpor => devpor,
5214         devclrn => devclrn,
5215         devoe => devoe,
5216         outclkena => VCC,
5217         inclkena => VCC,
5218         areset => GND,
5219         sreset => GND);
5220 \D_TOGGLE_COUNTER_OUT_1_\: stratix_io generic map (
5221     operation_mode => "output"
5222     )
5223 port map (
5224 padio => D_TOGGLE_COUNTERZ(1),
5225 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1),
5226 oe => VCC,
5227         devpor => devpor,
5228         devclrn => devclrn,
5229         devoe => devoe,
5230         outclkena => VCC,
5231         inclkena => VCC,
5232         areset => GND,
5233         sreset => GND);
5234 \D_TOGGLE_COUNTER_OUT_0_\: stratix_io generic map (
5235     operation_mode => "output"
5236     )
5237 port map (
5238 padio => D_TOGGLE_COUNTERZ(0),
5239 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0),
5240 oe => VCC,
5241         devpor => devpor,
5242         devclrn => devclrn,
5243         devoe => devoe,
5244         outclkena => VCC,
5245         inclkena => VCC,
5246         areset => GND,
5247         sreset => GND);
5248 D_TOGGLE_OUT: stratix_io generic map (
5249     operation_mode => "output"
5250     )
5251 port map (
5252 padio => D_TOGGLEZ,
5253 datain => \VGA_CONTROL_UNIT.TOGGLE_SIG\,
5254 oe => VCC,
5255         devpor => devpor,
5256         devclrn => devclrn,
5257         devoe => devoe,
5258         outclkena => VCC,
5259         inclkena => VCC,
5260         areset => GND,
5261         sreset => GND);
5262 D_STATE_CLK_OUT: stratix_io generic map (
5263     operation_mode => "output"
5264     )
5265 port map (
5266 padio => D_STATE_CLKZ,
5267 datain => G_33,
5268 oe => VCC,
5269         devpor => devpor,
5270         devclrn => devclrn,
5271         devoe => devoe,
5272         outclkena => VCC,
5273         inclkena => VCC,
5274         areset => GND,
5275         sreset => GND);
5276 \D_VSYNC_STATE_OUT_0_\: stratix_io generic map (
5277     operation_mode => "output"
5278     )
5279 port map (
5280 padio => D_VSYNC_STATEZ(0),
5281 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
5282 oe => VCC,
5283         devpor => devpor,
5284         devclrn => devclrn,
5285         devoe => devoe,
5286         outclkena => VCC,
5287         inclkena => VCC,
5288         areset => GND,
5289         sreset => GND);
5290 \D_VSYNC_STATE_OUT_1_\: stratix_io generic map (
5291     operation_mode => "output"
5292     )
5293 port map (
5294 padio => D_VSYNC_STATEZ(1),
5295 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
5296 oe => VCC,
5297         devpor => devpor,
5298         devclrn => devclrn,
5299         devoe => devoe,
5300         outclkena => VCC,
5301         inclkena => VCC,
5302         areset => GND,
5303         sreset => GND);
5304 \D_VSYNC_STATE_OUT_2_\: stratix_io generic map (
5305     operation_mode => "output"
5306     )
5307 port map (
5308 padio => D_VSYNC_STATEZ(2),
5309 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
5310 oe => VCC,
5311         devpor => devpor,
5312         devclrn => devclrn,
5313         devoe => devoe,
5314         outclkena => VCC,
5315         inclkena => VCC,
5316         areset => GND,
5317         sreset => GND);
5318 \D_VSYNC_STATE_OUT_3_\: stratix_io generic map (
5319     operation_mode => "output"
5320     )
5321 port map (
5322 padio => D_VSYNC_STATEZ(3),
5323 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
5324 oe => VCC,
5325         devpor => devpor,
5326         devclrn => devclrn,
5327         devoe => devoe,
5328         outclkena => VCC,
5329         inclkena => VCC,
5330         areset => GND,
5331         sreset => GND);
5332 \D_VSYNC_STATE_OUT_4_\: stratix_io generic map (
5333     operation_mode => "output"
5334     )
5335 port map (
5336 padio => D_VSYNC_STATEZ(4),
5337 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
5338 oe => VCC,
5339         devpor => devpor,
5340         devclrn => devclrn,
5341         devoe => devoe,
5342         outclkena => VCC,
5343         inclkena => VCC,
5344         areset => GND,
5345         sreset => GND);
5346 \D_VSYNC_STATE_OUT_5_\: stratix_io generic map (
5347     operation_mode => "output"
5348     )
5349 port map (
5350 padio => D_VSYNC_STATEZ(5),
5351 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
5352 oe => VCC,
5353         devpor => devpor,
5354         devclrn => devclrn,
5355         devoe => devoe,
5356         outclkena => VCC,
5357         inclkena => VCC,
5358         areset => GND,
5359         sreset => GND);
5360 \D_VSYNC_STATE_OUT_6_\: stratix_io generic map (
5361     operation_mode => "output"
5362     )
5363 port map (
5364 padio => D_VSYNC_STATEZ(6),
5365 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
5366 oe => VCC,
5367         devpor => devpor,
5368         devclrn => devclrn,
5369         devoe => devoe,
5370         outclkena => VCC,
5371         inclkena => VCC,
5372         areset => GND,
5373         sreset => GND);
5374 \D_HSYNC_STATE_OUT_0_\: stratix_io generic map (
5375     operation_mode => "output"
5376     )
5377 port map (
5378 padio => D_HSYNC_STATEZ(0),
5379 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
5380 oe => VCC,
5381         devpor => devpor,
5382         devclrn => devclrn,
5383         devoe => devoe,
5384         outclkena => VCC,
5385         inclkena => VCC,
5386         areset => GND,
5387         sreset => GND);
5388 \D_HSYNC_STATE_OUT_1_\: stratix_io generic map (
5389     operation_mode => "output"
5390     )
5391 port map (
5392 padio => D_HSYNC_STATEZ(1),
5393 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
5394 oe => VCC,
5395         devpor => devpor,
5396         devclrn => devclrn,
5397         devoe => devoe,
5398         outclkena => VCC,
5399         inclkena => VCC,
5400         areset => GND,
5401         sreset => GND);
5402 \D_HSYNC_STATE_OUT_2_\: stratix_io generic map (
5403     operation_mode => "output"
5404     )
5405 port map (
5406 padio => D_HSYNC_STATEZ(2),
5407 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
5408 oe => VCC,
5409         devpor => devpor,
5410         devclrn => devclrn,
5411         devoe => devoe,
5412         outclkena => VCC,
5413         inclkena => VCC,
5414         areset => GND,
5415         sreset => GND);
5416 \D_HSYNC_STATE_OUT_3_\: stratix_io generic map (
5417     operation_mode => "output"
5418     )
5419 port map (
5420 padio => D_HSYNC_STATEZ(3),
5421 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
5422 oe => VCC,
5423         devpor => devpor,
5424         devclrn => devclrn,
5425         devoe => devoe,
5426         outclkena => VCC,
5427         inclkena => VCC,
5428         areset => GND,
5429         sreset => GND);
5430 \D_HSYNC_STATE_OUT_4_\: stratix_io generic map (
5431     operation_mode => "output"
5432     )
5433 port map (
5434 padio => D_HSYNC_STATEZ(4),
5435 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
5436 oe => VCC,
5437         devpor => devpor,
5438         devclrn => devclrn,
5439         devoe => devoe,
5440         outclkena => VCC,
5441         inclkena => VCC,
5442         areset => GND,
5443         sreset => GND);
5444 \D_HSYNC_STATE_OUT_5_\: stratix_io generic map (
5445     operation_mode => "output"
5446     )
5447 port map (
5448 padio => D_HSYNC_STATEZ(5),
5449 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
5450 oe => VCC,
5451         devpor => devpor,
5452         devclrn => devclrn,
5453         devoe => devoe,
5454         outclkena => VCC,
5455         inclkena => VCC,
5456         areset => GND,
5457         sreset => GND);
5458 \D_HSYNC_STATE_OUT_6_\: stratix_io generic map (
5459     operation_mode => "output"
5460     )
5461 port map (
5462 padio => D_HSYNC_STATEZ(6),
5463 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
5464 oe => VCC,
5465         devpor => devpor,
5466         devclrn => devclrn,
5467         devoe => devoe,
5468         outclkena => VCC,
5469         inclkena => VCC,
5470         areset => GND,
5471         sreset => GND);
5472 D_B_OUT: stratix_io generic map (
5473     operation_mode => "output"
5474     )
5475 port map (
5476 padio => D_BZ,
5477 datain => \VGA_CONTROL_UNIT.B\,
5478 oe => VCC,
5479         devpor => devpor,
5480         devclrn => devclrn,
5481         devoe => devoe,
5482         outclkena => VCC,
5483         inclkena => VCC,
5484         areset => GND,
5485         sreset => GND);
5486 D_G_OUT: stratix_io generic map (
5487     operation_mode => "output"
5488     )
5489 port map (
5490 padio => D_GZ,
5491 datain => \VGA_CONTROL_UNIT.G\,
5492 oe => VCC,
5493         devpor => devpor,
5494         devclrn => devclrn,
5495         devoe => devoe,
5496         outclkena => VCC,
5497         inclkena => VCC,
5498         areset => GND,
5499         sreset => GND);
5500 D_R_OUT: stratix_io generic map (
5501     operation_mode => "output"
5502     )
5503 port map (
5504 padio => D_RZ,
5505 datain => \VGA_CONTROL_UNIT.R\,
5506 oe => VCC,
5507         devpor => devpor,
5508         devclrn => devclrn,
5509         devoe => devoe,
5510         outclkena => VCC,
5511         inclkena => VCC,
5512         areset => GND,
5513         sreset => GND);
5514 D_V_ENABLE_OUT: stratix_io generic map (
5515     operation_mode => "output"
5516     )
5517 port map (
5518 padio => D_V_ENABLEZ,
5519 datain => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
5520 oe => VCC,
5521         devpor => devpor,
5522         devclrn => devclrn,
5523         devoe => devoe,
5524         outclkena => VCC,
5525         inclkena => VCC,
5526         areset => GND,
5527         sreset => GND);
5528 D_H_ENABLE_OUT: stratix_io generic map (
5529     operation_mode => "output"
5530     )
5531 port map (
5532 padio => D_H_ENABLEZ,
5533 datain => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
5534 oe => VCC,
5535         devpor => devpor,
5536         devclrn => devclrn,
5537         devoe => devoe,
5538         outclkena => VCC,
5539         inclkena => VCC,
5540         areset => GND,
5541         sreset => GND);
5542 D_SET_VSYNC_COUNTER_OUT: stratix_io generic map (
5543     operation_mode => "output"
5544     )
5545 port map (
5546 padio => D_SET_VSYNC_COUNTERZ,
5547 datain => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
5548 oe => VCC,
5549         devpor => devpor,
5550         devclrn => devclrn,
5551         devoe => devoe,
5552         outclkena => VCC,
5553         inclkena => VCC,
5554         areset => GND,
5555         sreset => GND);
5556 D_SET_HSYNC_COUNTER_OUT: stratix_io generic map (
5557     operation_mode => "output"
5558     )
5559 port map (
5560 padio => D_SET_HSYNC_COUNTERZ,
5561 datain => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
5562 oe => VCC,
5563         devpor => devpor,
5564         devclrn => devclrn,
5565         devoe => devoe,
5566         outclkena => VCC,
5567         inclkena => VCC,
5568         areset => GND,
5569         sreset => GND);
5570 \D_VSYNC_COUNTER_OUT_9_\: stratix_io generic map (
5571     operation_mode => "output"
5572     )
5573 port map (
5574 padio => D_VSYNC_COUNTERZ(9),
5575 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
5576 oe => VCC,
5577         devpor => devpor,
5578         devclrn => devclrn,
5579         devoe => devoe,
5580         outclkena => VCC,
5581         inclkena => VCC,
5582         areset => GND,
5583         sreset => GND);
5584 \D_VSYNC_COUNTER_OUT_8_\: stratix_io generic map (
5585     operation_mode => "output"
5586     )
5587 port map (
5588 padio => D_VSYNC_COUNTERZ(8),
5589 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
5590 oe => VCC,
5591         devpor => devpor,
5592         devclrn => devclrn,
5593         devoe => devoe,
5594         outclkena => VCC,
5595         inclkena => VCC,
5596         areset => GND,
5597         sreset => GND);
5598 \D_VSYNC_COUNTER_OUT_7_\: stratix_io generic map (
5599     operation_mode => "output"
5600     )
5601 port map (
5602 padio => D_VSYNC_COUNTERZ(7),
5603 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
5604 oe => VCC,
5605         devpor => devpor,
5606         devclrn => devclrn,
5607         devoe => devoe,
5608         outclkena => VCC,
5609         inclkena => VCC,
5610         areset => GND,
5611         sreset => GND);
5612 \D_VSYNC_COUNTER_OUT_6_\: stratix_io generic map (
5613     operation_mode => "output"
5614     )
5615 port map (
5616 padio => D_VSYNC_COUNTERZ(6),
5617 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
5618 oe => VCC,
5619         devpor => devpor,
5620         devclrn => devclrn,
5621         devoe => devoe,
5622         outclkena => VCC,
5623         inclkena => VCC,
5624         areset => GND,
5625         sreset => GND);
5626 \D_VSYNC_COUNTER_OUT_5_\: stratix_io generic map (
5627     operation_mode => "output"
5628     )
5629 port map (
5630 padio => D_VSYNC_COUNTERZ(5),
5631 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
5632 oe => VCC,
5633         devpor => devpor,
5634         devclrn => devclrn,
5635         devoe => devoe,
5636         outclkena => VCC,
5637         inclkena => VCC,
5638         areset => GND,
5639         sreset => GND);
5640 \D_VSYNC_COUNTER_OUT_4_\: stratix_io generic map (
5641     operation_mode => "output"
5642     )
5643 port map (
5644 padio => D_VSYNC_COUNTERZ(4),
5645 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
5646 oe => VCC,
5647         devpor => devpor,
5648         devclrn => devclrn,
5649         devoe => devoe,
5650         outclkena => VCC,
5651         inclkena => VCC,
5652         areset => GND,
5653         sreset => GND);
5654 \D_VSYNC_COUNTER_OUT_3_\: stratix_io generic map (
5655     operation_mode => "output"
5656     )
5657 port map (
5658 padio => D_VSYNC_COUNTERZ(3),
5659 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
5660 oe => VCC,
5661         devpor => devpor,
5662         devclrn => devclrn,
5663         devoe => devoe,
5664         outclkena => VCC,
5665         inclkena => VCC,
5666         areset => GND,
5667         sreset => GND);
5668 \D_VSYNC_COUNTER_OUT_2_\: stratix_io generic map (
5669     operation_mode => "output"
5670     )
5671 port map (
5672 padio => D_VSYNC_COUNTERZ(2),
5673 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
5674 oe => VCC,
5675         devpor => devpor,
5676         devclrn => devclrn,
5677         devoe => devoe,
5678         outclkena => VCC,
5679         inclkena => VCC,
5680         areset => GND,
5681         sreset => GND);
5682 \D_VSYNC_COUNTER_OUT_1_\: stratix_io generic map (
5683     operation_mode => "output"
5684     )
5685 port map (
5686 padio => D_VSYNC_COUNTERZ(1),
5687 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
5688 oe => VCC,
5689         devpor => devpor,
5690         devclrn => devclrn,
5691         devoe => devoe,
5692         outclkena => VCC,
5693         inclkena => VCC,
5694         areset => GND,
5695         sreset => GND);
5696 \D_VSYNC_COUNTER_OUT_0_\: stratix_io generic map (
5697     operation_mode => "output"
5698     )
5699 port map (
5700 padio => D_VSYNC_COUNTERZ(0),
5701 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
5702 oe => VCC,
5703         devpor => devpor,
5704         devclrn => devclrn,
5705         devoe => devoe,
5706         outclkena => VCC,
5707         inclkena => VCC,
5708         areset => GND,
5709         sreset => GND);
5710 \D_HSYNC_COUNTER_OUT_9_\: stratix_io generic map (
5711     operation_mode => "output"
5712     )
5713 port map (
5714 padio => D_HSYNC_COUNTERZ(9),
5715 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
5716 oe => VCC,
5717         devpor => devpor,
5718         devclrn => devclrn,
5719         devoe => devoe,
5720         outclkena => VCC,
5721         inclkena => VCC,
5722         areset => GND,
5723         sreset => GND);
5724 \D_HSYNC_COUNTER_OUT_8_\: stratix_io generic map (
5725     operation_mode => "output"
5726     )
5727 port map (
5728 padio => D_HSYNC_COUNTERZ(8),
5729 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
5730 oe => VCC,
5731         devpor => devpor,
5732         devclrn => devclrn,
5733         devoe => devoe,
5734         outclkena => VCC,
5735         inclkena => VCC,
5736         areset => GND,
5737         sreset => GND);
5738 \D_HSYNC_COUNTER_OUT_7_\: stratix_io generic map (
5739     operation_mode => "output"
5740     )
5741 port map (
5742 padio => D_HSYNC_COUNTERZ(7),
5743 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
5744 oe => VCC,
5745         devpor => devpor,
5746         devclrn => devclrn,
5747         devoe => devoe,
5748         outclkena => VCC,
5749         inclkena => VCC,
5750         areset => GND,
5751         sreset => GND);
5752 \D_HSYNC_COUNTER_OUT_6_\: stratix_io generic map (
5753     operation_mode => "output"
5754     )
5755 port map (
5756 padio => D_HSYNC_COUNTERZ(6),
5757 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
5758 oe => VCC,
5759         devpor => devpor,
5760         devclrn => devclrn,
5761         devoe => devoe,
5762         outclkena => VCC,
5763         inclkena => VCC,
5764         areset => GND,
5765         sreset => GND);
5766 \D_HSYNC_COUNTER_OUT_5_\: stratix_io generic map (
5767     operation_mode => "output"
5768     )
5769 port map (
5770 padio => D_HSYNC_COUNTERZ(5),
5771 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
5772 oe => VCC,
5773         devpor => devpor,
5774         devclrn => devclrn,
5775         devoe => devoe,
5776         outclkena => VCC,
5777         inclkena => VCC,
5778         areset => GND,
5779         sreset => GND);
5780 \D_HSYNC_COUNTER_OUT_4_\: stratix_io generic map (
5781     operation_mode => "output"
5782     )
5783 port map (
5784 padio => D_HSYNC_COUNTERZ(4),
5785 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
5786 oe => VCC,
5787         devpor => devpor,
5788         devclrn => devclrn,
5789         devoe => devoe,
5790         outclkena => VCC,
5791         inclkena => VCC,
5792         areset => GND,
5793         sreset => GND);
5794 \D_HSYNC_COUNTER_OUT_3_\: stratix_io generic map (
5795     operation_mode => "output"
5796     )
5797 port map (
5798 padio => D_HSYNC_COUNTERZ(3),
5799 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
5800 oe => VCC,
5801         devpor => devpor,
5802         devclrn => devclrn,
5803         devoe => devoe,
5804         outclkena => VCC,
5805         inclkena => VCC,
5806         areset => GND,
5807         sreset => GND);
5808 \D_HSYNC_COUNTER_OUT_2_\: stratix_io generic map (
5809     operation_mode => "output"
5810     )
5811 port map (
5812 padio => D_HSYNC_COUNTERZ(2),
5813 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
5814 oe => VCC,
5815         devpor => devpor,
5816         devclrn => devclrn,
5817         devoe => devoe,
5818         outclkena => VCC,
5819         inclkena => VCC,
5820         areset => GND,
5821         sreset => GND);
5822 \D_HSYNC_COUNTER_OUT_1_\: stratix_io generic map (
5823     operation_mode => "output"
5824     )
5825 port map (
5826 padio => D_HSYNC_COUNTERZ(1),
5827 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
5828 oe => VCC,
5829         devpor => devpor,
5830         devclrn => devclrn,
5831         devoe => devoe,
5832         outclkena => VCC,
5833         inclkena => VCC,
5834         areset => GND,
5835         sreset => GND);
5836 \D_HSYNC_COUNTER_OUT_0_\: stratix_io generic map (
5837     operation_mode => "output"
5838     )
5839 port map (
5840 padio => D_HSYNC_COUNTERZ(0),
5841 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
5842 oe => VCC,
5843         devpor => devpor,
5844         devclrn => devclrn,
5845         devoe => devoe,
5846         outclkena => VCC,
5847         inclkena => VCC,
5848         areset => GND,
5849         sreset => GND);
5850 D_SET_LINE_COUNTER_OUT: stratix_io generic map (
5851     operation_mode => "output"
5852     )
5853 port map (
5854 padio => D_SET_LINE_COUNTERZ,
5855 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
5856 oe => VCC,
5857         devpor => devpor,
5858         devclrn => devclrn,
5859         devoe => devoe,
5860         outclkena => VCC,
5861         inclkena => VCC,
5862         areset => GND,
5863         sreset => GND);
5864 D_SET_COLUMN_COUNTER_OUT: stratix_io generic map (
5865     operation_mode => "output"
5866     )
5867 port map (
5868 padio => D_SET_COLUMN_COUNTERZ,
5869 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
5870 oe => VCC,
5871         devpor => devpor,
5872         devclrn => devclrn,
5873         devoe => devoe,
5874         outclkena => VCC,
5875         inclkena => VCC,
5876         areset => GND,
5877         sreset => GND);
5878 \D_LINE_COUNTER_OUT_8_\: stratix_io generic map (
5879     operation_mode => "output"
5880     )
5881 port map (
5882 padio => D_LINE_COUNTERZ(8),
5883 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
5884 oe => VCC,
5885         devpor => devpor,
5886         devclrn => devclrn,
5887         devoe => devoe,
5888         outclkena => VCC,
5889         inclkena => VCC,
5890         areset => GND,
5891         sreset => GND);
5892 \D_LINE_COUNTER_OUT_7_\: stratix_io generic map (
5893     operation_mode => "output"
5894     )
5895 port map (
5896 padio => D_LINE_COUNTERZ(7),
5897 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
5898 oe => VCC,
5899         devpor => devpor,
5900         devclrn => devclrn,
5901         devoe => devoe,
5902         outclkena => VCC,
5903         inclkena => VCC,
5904         areset => GND,
5905         sreset => GND);
5906 \D_LINE_COUNTER_OUT_6_\: stratix_io generic map (
5907     operation_mode => "output"
5908     )
5909 port map (
5910 padio => D_LINE_COUNTERZ(6),
5911 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
5912 oe => VCC,
5913         devpor => devpor,
5914         devclrn => devclrn,
5915         devoe => devoe,
5916         outclkena => VCC,
5917         inclkena => VCC,
5918         areset => GND,
5919         sreset => GND);
5920 \D_LINE_COUNTER_OUT_5_\: stratix_io generic map (
5921     operation_mode => "output"
5922     )
5923 port map (
5924 padio => D_LINE_COUNTERZ(5),
5925 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
5926 oe => VCC,
5927         devpor => devpor,
5928         devclrn => devclrn,
5929         devoe => devoe,
5930         outclkena => VCC,
5931         inclkena => VCC,
5932         areset => GND,
5933         sreset => GND);
5934 \D_LINE_COUNTER_OUT_4_\: stratix_io generic map (
5935     operation_mode => "output"
5936     )
5937 port map (
5938 padio => D_LINE_COUNTERZ(4),
5939 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
5940 oe => VCC,
5941         devpor => devpor,
5942         devclrn => devclrn,
5943         devoe => devoe,
5944         outclkena => VCC,
5945         inclkena => VCC,
5946         areset => GND,
5947         sreset => GND);
5948 \D_LINE_COUNTER_OUT_3_\: stratix_io generic map (
5949     operation_mode => "output"
5950     )
5951 port map (
5952 padio => D_LINE_COUNTERZ(3),
5953 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
5954 oe => VCC,
5955         devpor => devpor,
5956         devclrn => devclrn,
5957         devoe => devoe,
5958         outclkena => VCC,
5959         inclkena => VCC,
5960         areset => GND,
5961         sreset => GND);
5962 \D_LINE_COUNTER_OUT_2_\: stratix_io generic map (
5963     operation_mode => "output"
5964     )
5965 port map (
5966 padio => D_LINE_COUNTERZ(2),
5967 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
5968 oe => VCC,
5969         devpor => devpor,
5970         devclrn => devclrn,
5971         devoe => devoe,
5972         outclkena => VCC,
5973         inclkena => VCC,
5974         areset => GND,
5975         sreset => GND);
5976 \D_LINE_COUNTER_OUT_1_\: stratix_io generic map (
5977     operation_mode => "output"
5978     )
5979 port map (
5980 padio => D_LINE_COUNTERZ(1),
5981 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
5982 oe => VCC,
5983         devpor => devpor,
5984         devclrn => devclrn,
5985         devoe => devoe,
5986         outclkena => VCC,
5987         inclkena => VCC,
5988         areset => GND,
5989         sreset => GND);
5990 \D_LINE_COUNTER_OUT_0_\: stratix_io generic map (
5991     operation_mode => "output"
5992     )
5993 port map (
5994 padio => D_LINE_COUNTERZ(0),
5995 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
5996 oe => VCC,
5997         devpor => devpor,
5998         devclrn => devclrn,
5999         devoe => devoe,
6000         outclkena => VCC,
6001         inclkena => VCC,
6002         areset => GND,
6003         sreset => GND);
6004 \D_COLUMN_COUNTER_OUT_9_\: stratix_io generic map (
6005     operation_mode => "output"
6006     )
6007 port map (
6008 padio => D_COLUMN_COUNTERZ(9),
6009 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
6010 oe => VCC,
6011         devpor => devpor,
6012         devclrn => devclrn,
6013         devoe => devoe,
6014         outclkena => VCC,
6015         inclkena => VCC,
6016         areset => GND,
6017         sreset => GND);
6018 \D_COLUMN_COUNTER_OUT_8_\: stratix_io generic map (
6019     operation_mode => "output"
6020     )
6021 port map (
6022 padio => D_COLUMN_COUNTERZ(8),
6023 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
6024 oe => VCC,
6025         devpor => devpor,
6026         devclrn => devclrn,
6027         devoe => devoe,
6028         outclkena => VCC,
6029         inclkena => VCC,
6030         areset => GND,
6031         sreset => GND);
6032 \D_COLUMN_COUNTER_OUT_7_\: stratix_io generic map (
6033     operation_mode => "output"
6034     )
6035 port map (
6036 padio => D_COLUMN_COUNTERZ(7),
6037 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
6038 oe => VCC,
6039         devpor => devpor,
6040         devclrn => devclrn,
6041         devoe => devoe,
6042         outclkena => VCC,
6043         inclkena => VCC,
6044         areset => GND,
6045         sreset => GND);
6046 \D_COLUMN_COUNTER_OUT_6_\: stratix_io generic map (
6047     operation_mode => "output"
6048     )
6049 port map (
6050 padio => D_COLUMN_COUNTERZ(6),
6051 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
6052 oe => VCC,
6053         devpor => devpor,
6054         devclrn => devclrn,
6055         devoe => devoe,
6056         outclkena => VCC,
6057         inclkena => VCC,
6058         areset => GND,
6059         sreset => GND);
6060 \D_COLUMN_COUNTER_OUT_5_\: stratix_io generic map (
6061     operation_mode => "output"
6062     )
6063 port map (
6064 padio => D_COLUMN_COUNTERZ(5),
6065 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
6066 oe => VCC,
6067         devpor => devpor,
6068         devclrn => devclrn,
6069         devoe => devoe,
6070         outclkena => VCC,
6071         inclkena => VCC,
6072         areset => GND,
6073         sreset => GND);
6074 \D_COLUMN_COUNTER_OUT_4_\: stratix_io generic map (
6075     operation_mode => "output"
6076     )
6077 port map (
6078 padio => D_COLUMN_COUNTERZ(4),
6079 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
6080 oe => VCC,
6081         devpor => devpor,
6082         devclrn => devclrn,
6083         devoe => devoe,
6084         outclkena => VCC,
6085         inclkena => VCC,
6086         areset => GND,
6087         sreset => GND);
6088 \D_COLUMN_COUNTER_OUT_3_\: stratix_io generic map (
6089     operation_mode => "output"
6090     )
6091 port map (
6092 padio => D_COLUMN_COUNTERZ(3),
6093 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
6094 oe => VCC,
6095         devpor => devpor,
6096         devclrn => devclrn,
6097         devoe => devoe,
6098         outclkena => VCC,
6099         inclkena => VCC,
6100         areset => GND,
6101         sreset => GND);
6102 \D_COLUMN_COUNTER_OUT_2_\: stratix_io generic map (
6103     operation_mode => "output"
6104     )
6105 port map (
6106 padio => D_COLUMN_COUNTERZ(2),
6107 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
6108 oe => VCC,
6109         devpor => devpor,
6110         devclrn => devclrn,
6111         devoe => devoe,
6112         outclkena => VCC,
6113         inclkena => VCC,
6114         areset => GND,
6115         sreset => GND);
6116 \D_COLUMN_COUNTER_OUT_1_\: stratix_io generic map (
6117     operation_mode => "output"
6118     )
6119 port map (
6120 padio => D_COLUMN_COUNTERZ(1),
6121 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
6122 oe => VCC,
6123         devpor => devpor,
6124         devclrn => devclrn,
6125         devoe => devoe,
6126         outclkena => VCC,
6127         inclkena => VCC,
6128         areset => GND,
6129         sreset => GND);
6130 \D_COLUMN_COUNTER_OUT_0_\: stratix_io generic map (
6131     operation_mode => "output"
6132     )
6133 port map (
6134 padio => D_COLUMN_COUNTERZ(0),
6135 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
6136 oe => VCC,
6137         devpor => devpor,
6138         devclrn => devclrn,
6139         devoe => devoe,
6140         outclkena => VCC,
6141         inclkena => VCC,
6142         areset => GND,
6143         sreset => GND);
6144 D_VSYNC_OUT: stratix_io generic map (
6145     operation_mode => "output"
6146     )
6147 port map (
6148 padio => D_VSYNCZ,
6149 datain => \VGA_DRIVER_UNIT.V_SYNC\,
6150 oe => VCC,
6151         devpor => devpor,
6152         devclrn => devclrn,
6153         devoe => devoe,
6154         outclkena => VCC,
6155         inclkena => VCC,
6156         areset => GND,
6157         sreset => GND);
6158 D_HSYNC_OUT: stratix_io generic map (
6159     operation_mode => "output"
6160     )
6161 port map (
6162 padio => D_HSYNCZ,
6163 datain => \VGA_DRIVER_UNIT.H_SYNC\,
6164 oe => VCC,
6165         devpor => devpor,
6166         devclrn => devclrn,
6167         devoe => devoe,
6168         outclkena => VCC,
6169         inclkena => VCC,
6170         areset => GND,
6171         sreset => GND);
6172 \SEVEN_SEG_PIN_TRI_13_\: stratix_io generic map (
6173     operation_mode => "output"
6174     )
6175 port map (
6176 padio => SEVEN_SEG_PINZ(13),
6177 datain => VCC,
6178 oe => VCC,
6179         devpor => devpor,
6180         devclrn => devclrn,
6181         devoe => devoe,
6182         outclkena => VCC,
6183         inclkena => VCC,
6184         areset => GND,
6185         sreset => GND);
6186 \SEVEN_SEG_PIN_OUT_12_\: stratix_io generic map (
6187     operation_mode => "output"
6188     )
6189 port map (
6190 padio => SEVEN_SEG_PINZ(12),
6191 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6192 oe => VCC,
6193         devpor => devpor,
6194         devclrn => devclrn,
6195         devoe => devoe,
6196         outclkena => VCC,
6197         inclkena => VCC,
6198         areset => GND,
6199         sreset => GND);
6200 \SEVEN_SEG_PIN_OUT_11_\: stratix_io generic map (
6201     operation_mode => "output"
6202     )
6203 port map (
6204 padio => SEVEN_SEG_PINZ(11),
6205 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6206 oe => VCC,
6207         devpor => devpor,
6208         devclrn => devclrn,
6209         devoe => devoe,
6210         outclkena => VCC,
6211         inclkena => VCC,
6212         areset => GND,
6213         sreset => GND);
6214 \SEVEN_SEG_PIN_OUT_10_\: stratix_io generic map (
6215     operation_mode => "output"
6216     )
6217 port map (
6218 padio => SEVEN_SEG_PINZ(10),
6219 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6220 oe => VCC,
6221         devpor => devpor,
6222         devclrn => devclrn,
6223         devoe => devoe,
6224         outclkena => VCC,
6225         inclkena => VCC,
6226         areset => GND,
6227         sreset => GND);
6228 \SEVEN_SEG_PIN_OUT_9_\: stratix_io generic map (
6229     operation_mode => "output"
6230     )
6231 port map (
6232 padio => SEVEN_SEG_PINZ(9),
6233 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6234 oe => VCC,
6235         devpor => devpor,
6236         devclrn => devclrn,
6237         devoe => devoe,
6238         outclkena => VCC,
6239         inclkena => VCC,
6240         areset => GND,
6241         sreset => GND);
6242 \SEVEN_SEG_PIN_OUT_8_\: stratix_io generic map (
6243     operation_mode => "output"
6244     )
6245 port map (
6246 padio => SEVEN_SEG_PINZ(8),
6247 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6248 oe => VCC,
6249         devpor => devpor,
6250         devclrn => devclrn,
6251         devoe => devoe,
6252         outclkena => VCC,
6253         inclkena => VCC,
6254         areset => GND,
6255         sreset => GND);
6256 \SEVEN_SEG_PIN_OUT_7_\: stratix_io generic map (
6257     operation_mode => "output"
6258     )
6259 port map (
6260 padio => SEVEN_SEG_PINZ(7),
6261 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6262 oe => VCC,
6263         devpor => devpor,
6264         devclrn => devclrn,
6265         devoe => devoe,
6266         outclkena => VCC,
6267         inclkena => VCC,
6268         areset => GND,
6269         sreset => GND);
6270 \SEVEN_SEG_PIN_TRI_6_\: stratix_io generic map (
6271     operation_mode => "output"
6272     )
6273 port map (
6274 padio => SEVEN_SEG_PINZ(6),
6275 datain => VCC,
6276 oe => VCC,
6277         devpor => devpor,
6278         devclrn => devclrn,
6279         devoe => devoe,
6280         outclkena => VCC,
6281         inclkena => VCC,
6282         areset => GND,
6283         sreset => GND);
6284 \SEVEN_SEG_PIN_TRI_5_\: stratix_io generic map (
6285     operation_mode => "output"
6286     )
6287 port map (
6288 padio => SEVEN_SEG_PINZ(5),
6289 datain => VCC,
6290 oe => VCC,
6291         devpor => devpor,
6292         devclrn => devclrn,
6293         devoe => devoe,
6294         outclkena => VCC,
6295         inclkena => VCC,
6296         areset => GND,
6297         sreset => GND);
6298 \SEVEN_SEG_PIN_TRI_4_\: stratix_io generic map (
6299     operation_mode => "output"
6300     )
6301 port map (
6302 padio => SEVEN_SEG_PINZ(4),
6303 datain => VCC,
6304 oe => VCC,
6305         devpor => devpor,
6306         devclrn => devclrn,
6307         devoe => devoe,
6308         outclkena => VCC,
6309         inclkena => VCC,
6310         areset => GND,
6311         sreset => GND);
6312 \SEVEN_SEG_PIN_TRI_3_\: stratix_io generic map (
6313     operation_mode => "output"
6314     )
6315 port map (
6316 padio => SEVEN_SEG_PINZ(3),
6317 datain => VCC,
6318 oe => VCC,
6319         devpor => devpor,
6320         devclrn => devclrn,
6321         devoe => devoe,
6322         outclkena => VCC,
6323         inclkena => VCC,
6324         areset => GND,
6325         sreset => GND);
6326 \SEVEN_SEG_PIN_OUT_2_\: stratix_io generic map (
6327     operation_mode => "output"
6328     )
6329 port map (
6330 padio => SEVEN_SEG_PINZ(2),
6331 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6332 oe => VCC,
6333         devpor => devpor,
6334         devclrn => devclrn,
6335         devoe => devoe,
6336         outclkena => VCC,
6337         inclkena => VCC,
6338         areset => GND,
6339         sreset => GND);
6340 \SEVEN_SEG_PIN_OUT_1_\: stratix_io generic map (
6341     operation_mode => "output"
6342     )
6343 port map (
6344 padio => SEVEN_SEG_PINZ(1),
6345 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6346 oe => VCC,
6347         devpor => devpor,
6348         devclrn => devclrn,
6349         devoe => devoe,
6350         outclkena => VCC,
6351         inclkena => VCC,
6352         areset => GND,
6353         sreset => GND);
6354 \SEVEN_SEG_PIN_TRI_0_\: stratix_io generic map (
6355     operation_mode => "output"
6356     )
6357 port map (
6358 padio => SEVEN_SEG_PINZ(0),
6359 datain => VCC,
6360 oe => VCC,
6361         devpor => devpor,
6362         devclrn => devclrn,
6363         devoe => devoe,
6364         outclkena => VCC,
6365         inclkena => VCC,
6366         areset => GND,
6367         sreset => GND);
6368 VSYNC_PIN_OUT: stratix_io generic map (
6369     operation_mode => "output"
6370     )
6371 port map (
6372 padio => VSYNC_PINZ,
6373 datain => \VGA_DRIVER_UNIT.V_SYNC\,
6374 oe => VCC,
6375         devpor => devpor,
6376         devclrn => devclrn,
6377         devoe => devoe,
6378         outclkena => VCC,
6379         inclkena => VCC,
6380         areset => GND,
6381         sreset => GND);
6382 HSYNC_PIN_OUT: stratix_io generic map (
6383     operation_mode => "output"
6384     )
6385 port map (
6386 padio => HSYNC_PINZ,
6387 datain => \VGA_DRIVER_UNIT.H_SYNC\,
6388 oe => VCC,
6389         devpor => devpor,
6390         devclrn => devclrn,
6391         devoe => devoe,
6392         outclkena => VCC,
6393         inclkena => VCC,
6394         areset => GND,
6395         sreset => GND);
6396 B1_PIN_OUT: stratix_io generic map (
6397     operation_mode => "output"
6398     )
6399 port map (
6400 padio => B1_PINZ,
6401 datain => \VGA_CONTROL_UNIT.B\,
6402 oe => VCC,
6403         devpor => devpor,
6404         devclrn => devclrn,
6405         devoe => devoe,
6406         outclkena => VCC,
6407         inclkena => VCC,
6408         areset => GND,
6409         sreset => GND);
6410 B0_PIN_OUT: stratix_io generic map (
6411     operation_mode => "output"
6412     )
6413 port map (
6414 padio => B0_PINZ,
6415 datain => \VGA_CONTROL_UNIT.B\,
6416 oe => VCC,
6417         devpor => devpor,
6418         devclrn => devclrn,
6419         devoe => devoe,
6420         outclkena => VCC,
6421         inclkena => VCC,
6422         areset => GND,
6423         sreset => GND);
6424 G2_PIN_OUT: stratix_io generic map (
6425     operation_mode => "output"
6426     )
6427 port map (
6428 padio => G2_PINZ,
6429 datain => \VGA_CONTROL_UNIT.G\,
6430 oe => VCC,
6431         devpor => devpor,
6432         devclrn => devclrn,
6433         devoe => devoe,
6434         outclkena => VCC,
6435         inclkena => VCC,
6436         areset => GND,
6437         sreset => GND);
6438 G1_PIN_OUT: stratix_io generic map (
6439     operation_mode => "output"
6440     )
6441 port map (
6442 padio => G1_PINZ,
6443 datain => \VGA_CONTROL_UNIT.G\,
6444 oe => VCC,
6445         devpor => devpor,
6446         devclrn => devclrn,
6447         devoe => devoe,
6448         outclkena => VCC,
6449         inclkena => VCC,
6450         areset => GND,
6451         sreset => GND);
6452 G0_PIN_OUT: stratix_io generic map (
6453     operation_mode => "output"
6454     )
6455 port map (
6456 padio => G0_PINZ,
6457 datain => \VGA_CONTROL_UNIT.G\,
6458 oe => VCC,
6459         devpor => devpor,
6460         devclrn => devclrn,
6461         devoe => devoe,
6462         outclkena => VCC,
6463         inclkena => VCC,
6464         areset => GND,
6465         sreset => GND);
6466 R2_PIN_OUT: stratix_io generic map (
6467     operation_mode => "output"
6468     )
6469 port map (
6470 padio => R2_PINZ,
6471 datain => \VGA_CONTROL_UNIT.R\,
6472 oe => VCC,
6473         devpor => devpor,
6474         devclrn => devclrn,
6475         devoe => devoe,
6476         outclkena => VCC,
6477         inclkena => VCC,
6478         areset => GND,
6479         sreset => GND);
6480 R1_PIN_OUT: stratix_io generic map (
6481     operation_mode => "output"
6482     )
6483 port map (
6484 padio => R1_PINZ,
6485 datain => \VGA_CONTROL_UNIT.R\,
6486 oe => VCC,
6487         devpor => devpor,
6488         devclrn => devclrn,
6489         devoe => devoe,
6490         outclkena => VCC,
6491         inclkena => VCC,
6492         areset => GND,
6493         sreset => GND);
6494 R0_PIN_OUT: stratix_io generic map (
6495     operation_mode => "output"
6496     )
6497 port map (
6498 padio => R0_PINZ,
6499 datain => \VGA_CONTROL_UNIT.R\,
6500 oe => VCC,
6501         devpor => devpor,
6502         devclrn => devclrn,
6503         devoe => devoe,
6504         outclkena => VCC,
6505         inclkena => VCC,
6506         areset => GND,
6507         sreset => GND);
6508 G_33 <= CLK_PIN_C;
6509 VGA_DRIVER_UNIT: vga_driver port map (
6510 line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
6511 line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
6512 line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
6513 line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
6514 line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
6515 line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
6516 line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
6517 line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
6518 line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
6519 dly_counter_1 => DLY_COUNTER(1),
6520 dly_counter_0 => DLY_COUNTER(0),
6521 vsync_state_2 => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
6522 vsync_state_5 => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
6523 vsync_state_3 => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
6524 vsync_state_6 => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
6525 vsync_state_4 => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
6526 vsync_state_1 => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
6527 vsync_state_0 => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
6528 hsync_state_2 => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
6529 hsync_state_4 => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
6530 hsync_state_0 => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
6531 hsync_state_5 => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
6532 hsync_state_1 => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
6533 hsync_state_3 => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
6534 hsync_state_6 => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
6535 column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
6536 column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
6537 column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
6538 column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
6539 column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
6540 column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
6541 column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
6542 column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
6543 column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
6544 column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
6545 vsync_counter_9 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
6546 vsync_counter_8 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
6547 vsync_counter_7 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
6548 vsync_counter_6 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
6549 vsync_counter_5 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
6550 vsync_counter_4 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
6551 vsync_counter_3 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
6552 vsync_counter_2 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
6553 vsync_counter_1 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
6554 vsync_counter_0 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
6555 hsync_counter_9 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
6556 hsync_counter_8 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
6557 hsync_counter_7 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
6558 hsync_counter_6 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
6559 hsync_counter_5 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
6560 hsync_counter_4 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
6561 hsync_counter_3 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
6562 hsync_counter_2 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
6563 hsync_counter_1 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
6564 hsync_counter_0 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
6565 d_set_vsync_counter => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
6566 v_sync => \VGA_DRIVER_UNIT.V_SYNC\,
6567 h_sync => \VGA_DRIVER_UNIT.H_SYNC\,
6568 h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
6569 v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
6570 reset_pin_c => RESET_PIN_C,
6571 un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6572 d_set_hsync_counter => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
6573 clk_pin_c => CLK_PIN_C);
6574 VGA_CONTROL_UNIT: vga_control port map (
6575 line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
6576 line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
6577 line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
6578 line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
6579 line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
6580 line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
6581 line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
6582 line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
6583 line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
6584 column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
6585 column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
6586 column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
6587 column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
6588 column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
6589 column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
6590 column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
6591 column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
6592 column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
6593 column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
6594 toggle_counter_sig_0 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0),
6595 toggle_counter_sig_1 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1),
6596 toggle_counter_sig_2 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2),
6597 toggle_counter_sig_3 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3),
6598 toggle_counter_sig_4 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4),
6599 toggle_counter_sig_5 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5),
6600 toggle_counter_sig_6 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6),
6601 toggle_counter_sig_7 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7),
6602 toggle_counter_sig_8 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8),
6603 toggle_counter_sig_9 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9),
6604 toggle_counter_sig_10 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10),
6605 toggle_counter_sig_11 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11),
6606 toggle_counter_sig_12 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12),
6607 toggle_counter_sig_13 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13),
6608 toggle_counter_sig_14 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14),
6609 toggle_counter_sig_15 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15),
6610 toggle_counter_sig_16 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16),
6611 toggle_counter_sig_17 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17),
6612 toggle_counter_sig_18 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18),
6613 toggle_counter_sig_19 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19),
6614 toggle_counter_sig_20 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20),
6615 toggle_counter_sig_21 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21),
6616 toggle_counter_sig_22 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22),
6617 toggle_counter_sig_23 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23),
6618 toggle_counter_sig_24 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24),
6619 h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
6620 g => \VGA_CONTROL_UNIT.G\,
6621 b => \VGA_CONTROL_UNIT.B\,
6622 v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
6623 r => \VGA_CONTROL_UNIT.R\,
6624 toggle_sig => \VGA_CONTROL_UNIT.TOGGLE_SIG\,
6625 un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6626 clk_pin_c => CLK_PIN_C);
6627 N_1 <= CLK_PIN_INTERNAL;
6628 N_2 <= RESET_PIN_INTERNAL;
6629 N_84_0 <= R0_PINZ;
6630 N_85_0 <= R1_PINZ;
6631 N_86_0 <= R2_PINZ;
6632 N_87_0 <= G0_PINZ;
6633 N_88_0 <= G1_PINZ;
6634 N_89_0 <= G2_PINZ;
6635 N_90_0 <= B0_PINZ;
6636 N_91_0 <= B1_PINZ;
6637 N_92_0 <= HSYNC_PINZ;
6638 N_93_0 <= VSYNC_PINZ;
6639 N_94_0 <= SEVEN_SEG_PINZ(0);
6640 N_95_0 <= SEVEN_SEG_PINZ(1);
6641 N_96_0 <= SEVEN_SEG_PINZ(2);
6642 N_97_0 <= SEVEN_SEG_PINZ(3);
6643 N_98_0 <= SEVEN_SEG_PINZ(4);
6644 N_99_0 <= SEVEN_SEG_PINZ(5);
6645 N_100_0 <= SEVEN_SEG_PINZ(6);
6646 N_101_0 <= SEVEN_SEG_PINZ(7);
6647 N_102_0 <= SEVEN_SEG_PINZ(8);
6648 N_103_0 <= SEVEN_SEG_PINZ(9);
6649 N_104_0 <= SEVEN_SEG_PINZ(10);
6650 N_105_0 <= SEVEN_SEG_PINZ(11);
6651 N_106_0 <= SEVEN_SEG_PINZ(12);
6652 N_107_0 <= SEVEN_SEG_PINZ(13);
6653 N_108_0 <= D_HSYNCZ;
6654 N_109_0 <= D_VSYNCZ;
6655 N_110_0 <= D_COLUMN_COUNTERZ(0);
6656 N_111_0 <= D_COLUMN_COUNTERZ(1);
6657 N_112_0 <= D_COLUMN_COUNTERZ(2);
6658 N_113_0 <= D_COLUMN_COUNTERZ(3);
6659 N_114_0 <= D_COLUMN_COUNTERZ(4);
6660 N_115_0 <= D_COLUMN_COUNTERZ(5);
6661 N_116_0 <= D_COLUMN_COUNTERZ(6);
6662 N_117_0 <= D_COLUMN_COUNTERZ(7);
6663 N_118 <= D_COLUMN_COUNTERZ(8);
6664 N_119 <= D_COLUMN_COUNTERZ(9);
6665 N_120 <= D_LINE_COUNTERZ(0);
6666 N_121 <= D_LINE_COUNTERZ(1);
6667 N_122 <= D_LINE_COUNTERZ(2);
6668 N_123 <= D_LINE_COUNTERZ(3);
6669 N_124 <= D_LINE_COUNTERZ(4);
6670 N_125 <= D_LINE_COUNTERZ(5);
6671 N_126 <= D_LINE_COUNTERZ(6);
6672 N_127 <= D_LINE_COUNTERZ(7);
6673 N_128 <= D_LINE_COUNTERZ(8);
6674 N_129 <= D_SET_COLUMN_COUNTERZ;
6675 N_130 <= D_SET_LINE_COUNTERZ;
6676 N_131 <= D_HSYNC_COUNTERZ(0);
6677 N_132 <= D_HSYNC_COUNTERZ(1);
6678 N_133 <= D_HSYNC_COUNTERZ(2);
6679 N_134 <= D_HSYNC_COUNTERZ(3);
6680 N_135 <= D_HSYNC_COUNTERZ(4);
6681 N_136 <= D_HSYNC_COUNTERZ(5);
6682 N_137 <= D_HSYNC_COUNTERZ(6);
6683 N_138 <= D_HSYNC_COUNTERZ(7);
6684 N_139 <= D_HSYNC_COUNTERZ(8);
6685 N_140 <= D_HSYNC_COUNTERZ(9);
6686 N_141 <= D_VSYNC_COUNTERZ(0);
6687 N_142 <= D_VSYNC_COUNTERZ(1);
6688 N_143 <= D_VSYNC_COUNTERZ(2);
6689 N_144 <= D_VSYNC_COUNTERZ(3);
6690 N_145 <= D_VSYNC_COUNTERZ(4);
6691 N_146 <= D_VSYNC_COUNTERZ(5);
6692 N_147 <= D_VSYNC_COUNTERZ(6);
6693 N_148 <= D_VSYNC_COUNTERZ(7);
6694 N_149 <= D_VSYNC_COUNTERZ(8);
6695 N_150 <= D_VSYNC_COUNTERZ(9);
6696 N_151 <= D_SET_HSYNC_COUNTERZ;
6697 N_152 <= D_SET_VSYNC_COUNTERZ;
6698 N_153 <= D_H_ENABLEZ;
6699 N_154 <= D_V_ENABLEZ;
6700 N_155 <= D_RZ;
6701 N_156 <= D_GZ;
6702 N_157 <= D_BZ;
6703 N_158 <= D_HSYNC_STATEZ(6);
6704 N_159 <= D_HSYNC_STATEZ(5);
6705 N_160 <= D_HSYNC_STATEZ(4);
6706 N_161 <= D_HSYNC_STATEZ(3);
6707 N_162 <= D_HSYNC_STATEZ(2);
6708 N_163 <= D_HSYNC_STATEZ(1);
6709 N_164 <= D_HSYNC_STATEZ(0);
6710 N_165 <= D_VSYNC_STATEZ(6);
6711 N_166 <= D_VSYNC_STATEZ(5);
6712 N_167 <= D_VSYNC_STATEZ(4);
6713 N_168 <= D_VSYNC_STATEZ(3);
6714 N_169 <= D_VSYNC_STATEZ(2);
6715 N_170 <= D_VSYNC_STATEZ(1);
6716 N_171 <= D_VSYNC_STATEZ(0);
6717 N_172 <= D_STATE_CLKZ;
6718 N_173 <= D_TOGGLEZ;
6719 N_174 <= D_TOGGLE_COUNTERZ(0);
6720 N_175 <= D_TOGGLE_COUNTERZ(1);
6721 N_176 <= D_TOGGLE_COUNTERZ(2);
6722 N_177 <= D_TOGGLE_COUNTERZ(3);
6723 N_178 <= D_TOGGLE_COUNTERZ(4);
6724 N_179 <= D_TOGGLE_COUNTERZ(5);
6725 N_180 <= D_TOGGLE_COUNTERZ(6);
6726 N_181 <= D_TOGGLE_COUNTERZ(7);
6727 N_182 <= D_TOGGLE_COUNTERZ(8);
6728 N_183 <= D_TOGGLE_COUNTERZ(9);
6729 N_184 <= D_TOGGLE_COUNTERZ(10);
6730 N_185 <= D_TOGGLE_COUNTERZ(11);
6731 N_186 <= D_TOGGLE_COUNTERZ(12);
6732 N_187 <= D_TOGGLE_COUNTERZ(13);
6733 N_188 <= D_TOGGLE_COUNTERZ(14);
6734 N_189 <= D_TOGGLE_COUNTERZ(15);
6735 N_190 <= D_TOGGLE_COUNTERZ(16);
6736 N_191 <= D_TOGGLE_COUNTERZ(17);
6737 N_192 <= D_TOGGLE_COUNTERZ(18);
6738 N_193 <= D_TOGGLE_COUNTERZ(19);
6739 N_194 <= D_TOGGLE_COUNTERZ(20);
6740 N_195 <= D_TOGGLE_COUNTERZ(21);
6741 N_196 <= D_TOGGLE_COUNTERZ(22);
6742 N_197 <= D_TOGGLE_COUNTERZ(23);
6743 N_198 <= D_TOGGLE_COUNTERZ(24);
6744 r0_pin <= N_84_0;
6745 r1_pin <= N_85_0;
6746 r2_pin <= N_86_0;
6747 g0_pin <= N_87_0;
6748 g1_pin <= N_88_0;
6749 g2_pin <= N_89_0;
6750 b0_pin <= N_90_0;
6751 b1_pin <= N_91_0;
6752 hsync_pin <= N_92_0;
6753 vsync_pin <= N_93_0;
6754 seven_seg_pin(0) <= N_94_0;
6755 seven_seg_pin(1) <= N_95_0;
6756 seven_seg_pin(2) <= N_96_0;
6757 seven_seg_pin(3) <= N_97_0;
6758 seven_seg_pin(4) <= N_98_0;
6759 seven_seg_pin(5) <= N_99_0;
6760 seven_seg_pin(6) <= N_100_0;
6761 seven_seg_pin(7) <= N_101_0;
6762 seven_seg_pin(8) <= N_102_0;
6763 seven_seg_pin(9) <= N_103_0;
6764 seven_seg_pin(10) <= N_104_0;
6765 seven_seg_pin(11) <= N_105_0;
6766 seven_seg_pin(12) <= N_106_0;
6767 seven_seg_pin(13) <= N_107_0;
6768 d_hsync <= N_108_0;
6769 d_vsync <= N_109_0;
6770 d_column_counter(0) <= N_110_0;
6771 d_column_counter(1) <= N_111_0;
6772 d_column_counter(2) <= N_112_0;
6773 d_column_counter(3) <= N_113_0;
6774 d_column_counter(4) <= N_114_0;
6775 d_column_counter(5) <= N_115_0;
6776 d_column_counter(6) <= N_116_0;
6777 d_column_counter(7) <= N_117_0;
6778 d_column_counter(8) <= N_118;
6779 d_column_counter(9) <= N_119;
6780 d_line_counter(0) <= N_120;
6781 d_line_counter(1) <= N_121;
6782 d_line_counter(2) <= N_122;
6783 d_line_counter(3) <= N_123;
6784 d_line_counter(4) <= N_124;
6785 d_line_counter(5) <= N_125;
6786 d_line_counter(6) <= N_126;
6787 d_line_counter(7) <= N_127;
6788 d_line_counter(8) <= N_128;
6789 d_set_column_counter <= N_129;
6790 d_set_line_counter <= N_130;
6791 d_hsync_counter(0) <= N_131;
6792 d_hsync_counter(1) <= N_132;
6793 d_hsync_counter(2) <= N_133;
6794 d_hsync_counter(3) <= N_134;
6795 d_hsync_counter(4) <= N_135;
6796 d_hsync_counter(5) <= N_136;
6797 d_hsync_counter(6) <= N_137;
6798 d_hsync_counter(7) <= N_138;
6799 d_hsync_counter(8) <= N_139;
6800 d_hsync_counter(9) <= N_140;
6801 d_vsync_counter(0) <= N_141;
6802 d_vsync_counter(1) <= N_142;
6803 d_vsync_counter(2) <= N_143;
6804 d_vsync_counter(3) <= N_144;
6805 d_vsync_counter(4) <= N_145;
6806 d_vsync_counter(5) <= N_146;
6807 d_vsync_counter(6) <= N_147;
6808 d_vsync_counter(7) <= N_148;
6809 d_vsync_counter(8) <= N_149;
6810 d_vsync_counter(9) <= N_150;
6811 d_set_hsync_counter <= N_151;
6812 d_set_vsync_counter <= N_152;
6813 d_h_enable <= N_153;
6814 d_v_enable <= N_154;
6815 d_r <= N_155;
6816 d_g <= N_156;
6817 d_b <= N_157;
6818 d_hsync_state(6) <= N_158;
6819 d_hsync_state(5) <= N_159;
6820 d_hsync_state(4) <= N_160;
6821 d_hsync_state(3) <= N_161;
6822 d_hsync_state(2) <= N_162;
6823 d_hsync_state(1) <= N_163;
6824 d_hsync_state(0) <= N_164;
6825 d_vsync_state(6) <= N_165;
6826 d_vsync_state(5) <= N_166;
6827 d_vsync_state(4) <= N_167;
6828 d_vsync_state(3) <= N_168;
6829 d_vsync_state(2) <= N_169;
6830 d_vsync_state(1) <= N_170;
6831 d_vsync_state(0) <= N_171;
6832 d_state_clk <= N_172;
6833 d_toggle <= N_173;
6834 d_toggle_counter(0) <= N_174;
6835 d_toggle_counter(1) <= N_175;
6836 d_toggle_counter(2) <= N_176;
6837 d_toggle_counter(3) <= N_177;
6838 d_toggle_counter(4) <= N_178;
6839 d_toggle_counter(5) <= N_179;
6840 d_toggle_counter(6) <= N_180;
6841 d_toggle_counter(7) <= N_181;
6842 d_toggle_counter(8) <= N_182;
6843 d_toggle_counter(9) <= N_183;
6844 d_toggle_counter(10) <= N_184;
6845 d_toggle_counter(11) <= N_185;
6846 d_toggle_counter(12) <= N_186;
6847 d_toggle_counter(13) <= N_187;
6848 d_toggle_counter(14) <= N_188;
6849 d_toggle_counter(15) <= N_189;
6850 d_toggle_counter(16) <= N_190;
6851 d_toggle_counter(17) <= N_191;
6852 d_toggle_counter(18) <= N_192;
6853 d_toggle_counter(19) <= N_193;
6854 d_toggle_counter(20) <= N_194;
6855 d_toggle_counter(21) <= N_195;
6856 d_toggle_counter(22) <= N_196;
6857 d_toggle_counter(23) <= N_197;
6858 d_toggle_counter(24) <= N_198;
6859 CLK_PIN_INTERNAL <= clk_pin;
6860 RESET_PIN_INTERNAL <= reset_pin;
6861 end beh;
6862