--- /dev/null
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement default branches.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/report/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL/Verilog immediate assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+; level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name: # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable System Verilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during
+; simulation. If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: these ini variables can be overriden by the vsim command
+; line switch "-onfinish <ask|stop|exit>".
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA concurrent assertion pass enable.
+; For SVA, Default is on when the assertion has a pass action block, or
+; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
+; For PSL, Default is on only when vsim switch "-assertdebug" is used
+; and the vopt "+acc=a" flag is active.
+; AssertionPassEnable = 0
+
+; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL/SVA concurrent assertion pass limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = 1
+
+; Set PSL/SVA concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
+; are included for toggle coverage. This leads to a longer simulation time with bigger
+; arrays covered with toggle coverage. Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable is 1
+; SVCovergroup63Compatibility = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
+; Sv_Seed = 0
+
+; Maximum size of dynamic arrays that are resized during randomize().
+; The default is 1000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 1000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; The default is 0 (no error).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures (SystemVerilog).
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; When SolveFailDebug is enabled, this value specifies the algorithm used to
+; discover conflicts between constraints for randomize() failures.
+; The default is "many".
+;
+; Valid schemes are:
+; "many" = best for determining conflicts due to many related constraints
+; "few" = best for determining conflicts due to few related constraints
+;
+; SolveFailDebugScheme = many
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum number of constraint subsets that will be tested for
+; conflicts.
+; The default is 0 (no limit).
+; SolveFailDebugLimit = 0
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum size of constraint subsets that will be tested for
+; conflicts.
+; The default value is 0 (no limit).
+; SolveFailDebugMaxSet = 0
+
+; Maximum size of the solution graph that may be generated during randomize().
+; This value can be used to force randomize() to abort if the memory
+; requirements of the constraint scenario exceeds the specified limit. This
+; value is specified in 1000s of nodes.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Maximum number of evaluations that may be performed on the solution graph
+; generated during randomize(). This value can be used to force randomize() to
+; abort if the complexity of the constraint scenario (in time) exceeds the
+; specified limit. This value is specified in 10000s of evaluations.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of
+; the constraint solver for others.
+; The default value is "" (no options).
+;
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints
+; n = disable bit interleaving for all constraints
+; r = reverse bit interleaving
+;
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; Note: To achieve the same random sequences, solver optimizations and/or
+; bug fixes introduced since the specified release may be disabled -
+; yielding the performance / behavior of the prior release.
+; Default value set to "" (random compatibility not required).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
--- /dev/null
+m255
+K3
+cModel Technology Builtin Library
+13
+Z0 dD:\qa\buildsites\6.5b\builds\win32\modeltech
+Penv
+Z1 OL;C;6.5b;42
+32
+b1
+Z2 OP;C;6.5b;42
+Z3 w1242971927
+Z4 d$MODEL_TECH/..
+Z5 8vhdl_src/std/env.vhd
+Z6 Fvhdl_src/std/env.vhd
+l0
+L1
+VMS<MD0@]6L0EihU2C?95]0
+Z7 OE;C;6.5b;42
+Z8 o-work std -dirpath {$MODEL_TECH/..}
+Z9 tExplicit 1
+!s100 Jk]WLNXXY90REn6H_ahP:3
+Bbody
+DBx4 work 3 env 0 22 MS<MD0@]6L0EihU2C?95]0
+R1
+32
+R2
+l0
+L11
+Vc=H5Zk>h;Gmh>9BN<MDk<3
+R7
+R8
+R9
+nbody
+!s100 Q2aL@L`86VXT`NWicN9BE0
+Pstandard
+R1
+33
+R2
+R3
+R4
+8vhdl_src/std/standard.vhd
+Fvhdl_src/std/standard.vhd
+l0
+L8
+VM]UbYN`go6foOAGb42z_92
+R7
+o-s -2008 -work std -dirpath {$MODEL_TECH/..}
+R9
+!s100 ddgmKj`IlOCVkRDj1[3^93
+Ptextio
+R1
+33
+b1
+R2
+R3
+R4
+Z10 8vhdl_src/std/textio.vhd
+Z11 Fvhdl_src/std/textio.vhd
+l0
+L12
+Vm2KQDRRhmF833<<DjYdL70
+R7
+Z12 o-2008 -work std -dirpath {$MODEL_TECH/..}
+R9
+!s100 9=H8XRm2GgHGk4^GSVfTD3
+Bbody
+DBx4 work 6 textio 0 22 m2KQDRRhmF833<<DjYdL70
+R1
+33
+R2
+l0
+L162
+VCbz:dGNX5zl`2nYKYBS>`3
+R7
+R12
+R9
+nbody
+!s100 9k9n?Y0BCW@M9E4=S3GCM2
--- /dev/null
+m255
+K3
+cModel Technology Builtin Library
+13
+Z0 dD:\qa\buildsites\6.5b\builds\win32\modeltech
+Pmath_complex
+Z1 DPx4 work 9 math_real 0 22 zjAF7SKfg_RPI0GT^n1N`1
+Z2 OL;C;6.5b;42
+31
+b1
+Z3 Mx1 4 work 9 math_real
+Z4 OP;C;6.5b;42
+Z5 w1208391546
+Z6 d$MODEL_TECH/..
+Z7 8vhdl_src/ieee/1076-2code.vhd
+Z8 Fvhdl_src/ieee/1076-2code.vhd
+l0
+L687
+V1a;R8Z_kc3Q7^>9;gKVIV0
+Z9 OE;C;6.5b;42
+Z10 o-93 -work ieee -dirpath {$MODEL_TECH/..}
+Z11 tExplicit 1
+!s100 j6YPGc@:alQm=gAZDnLd<2
+Bbody
+DBx4 work 12 math_complex 0 22 1a;R8Z_kc3Q7^>9;gKVIV0
+R1
+R2
+31
+R3
+R4
+l0
+L3719
+VIMmI^hXJEW@Uoa4kJFX:K1
+R9
+R10
+R11
+nbody
+!s100 GRUnO8ScI[9kFB=Ki3;5f2
+Pmath_real
+R2
+31
+b1
+R4
+R5
+R6
+R7
+R8
+l0
+L55
+VzjAF7SKfg_RPI0GT^n1N`1
+R9
+R10
+R11
+!s100 ?h[BJdc9h<H[IRQe:3oKI1
+Bbody
+DBx4 work 9 math_real 0 22 zjAF7SKfg_RPI0GT^n1N`1
+R2
+31
+R4
+l0
+L1772
+V:TOmE?QHig?1Xi[gFIA[l1
+R9
+R10
+R11
+nbody
+!s100 k8]3?:F=XKke_dV>AMLfn1
+Pnumeric_bit
+R2
+31
+b1
+R4
+Z12 w1242971927
+R6
+Z13 8vhdl_src/ieee/mti_numeric_bit.vhd
+Z14 Fvhdl_src/ieee/mti_numeric_bit.vhd
+l0
+L58
+V0:R3B671ke]N`8]?lK_c_1
+R9
+Z15 o-93 -work ieee -dirpath {$MODEL_TECH/..} -nowarn 3
+R11
+!s100 b164i8a]Ti[DoEJ?8VoH00
+Bbody
+DBx4 work 11 numeric_bit 0 22 0:R3B671ke]N`8]?lK_c_1
+R2
+31
+R4
+l0
+L1045
+VMl`J4ca2be3ejNXY`>k4Y1
+R9
+R15
+R11
+nbody
+!s100 G_bI[L810b3Q]LV2V2za01
+Pnumeric_std
+Z16 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
+R2
+31
+b1
+Z17 Mx1 4 ieee 14 std_logic_1164
+R4
+R12
+R6
+Z18 8vhdl_src/ieee/mti_numeric_std.vhd
+Z19 Fvhdl_src/ieee/mti_numeric_std.vhd
+l0
+L57
+V=NSdli^?T5OD8;4F<blj<3
+R9
+R15
+R11
+!s100 VoXZ=H`a=49gQGdC[Y9Z21
+Bbody
+DBx4 work 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3
+R16
+R2
+31
+R17
+R4
+l0
+L1100
+V;m@IM<mVXokEM:EdoJkM40
+R9
+R15
+R11
+nbody
+!s100 1cgbZWo^oXbeE6NO65mZ=1
+Pstd_logic_1164
+R2
+31
+b1
+R4
+R12
+R6
+Z20 8vhdl_src/ieee/stdlogic.vhd
+Z21 Fvhdl_src/ieee/stdlogic.vhd
+l0
+L36
+VGH1=`jDDBJ=`LM;:Ak`kf2
+R9
+R10
+R11
+!s100 Z6;nC83Z4f^^XJaZ:TVAb1
+Bbody
+DBx4 work 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
+R2
+31
+R4
+l0
+L169
+V?YNEkS<^lY?<6LBZLFa8D0
+R9
+R10
+R11
+nbody
+!s100 6leLR2`?2Fd;N4T0X@_oa3
+Pstd_logic_arith
+R16
+R2
+31
+b1
+R17
+R4
+R12
+R6
+Z22 8vhdl_src/synopsys/mti_std_logic_arith.vhd
+Z23 Fvhdl_src/synopsys/mti_std_logic_arith.vhd
+l0
+L25
+VGJbAT?7@hRQU9IQ702DT]2
+R9
+R10
+R11
+!s100 Sa7R1jMegK@3B0AV8`ReA0
+Bbody
+DBx4 work 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
+R16
+R2
+31
+R17
+R4
+l0
+L620
+V@]n`Xb_DgYnHKLT95S1dB1
+R9
+R10
+R11
+nbody
+!s100 P1PiLbE11nL731z_^XjK92
+Pstd_logic_misc
+Z24 DPx8 synopsys 10 attributes 0 22 2Q8I4L@H0S1aHEXkjUYDC1
+R16
+R2
+31
+b1
+Z25 Mx2 4 ieee 14 std_logic_1164
+Z26 Mx1 8 synopsys 10 attributes
+R4
+R12
+R6
+Z27 8vhdl_src/synopsys/mti_std_logic_misc.vhd
+Z28 Fvhdl_src/synopsys/mti_std_logic_misc.vhd
+l0
+L24
+VD2f;@P3IKJA9T^H8HI[9K0
+R9
+R10
+R11
+!s100 1zB4YNJ<`YghL_A>3aVEY0
+Bbody
+DBx4 work 14 std_logic_misc 0 22 D2f;@P3IKJA9T^H8HI[9K0
+R24
+R16
+R2
+31
+R25
+R26
+R4
+l0
+L173
+Vd@dC3[2h4nN7HB2XD:8CM1
+R9
+R10
+R11
+nbody
+!s100 Nh<M=F4GQcbj[<UaS33LA1
+Pstd_logic_signed
+Z29 DPx4 ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
+R16
+R2
+31
+b1
+R25
+Z30 Mx1 4 ieee 15 std_logic_arith
+R4
+R12
+R6
+Z31 8vhdl_src/synopsys/mti_std_logic_signed.vhd
+Z32 Fvhdl_src/synopsys/mti_std_logic_signed.vhd
+l0
+L35
+V<9<Kcl:S52:oW`F]FQhb20
+R9
+R10
+R11
+!s100 mSh:b6d=DKVg2KeEQH^kd0
+Bbody
+DBx4 work 16 std_logic_signed 0 22 <9<Kcl:S52:oW`F]FQhb20
+R29
+R16
+R2
+31
+R25
+R30
+R4
+l0
+L232
+VDR>6>65S7FR:e[I>ADUQO1
+R9
+R10
+R11
+nbody
+!s100 ]?UNFEkZD:LZf;=G2=^OM3
+Pstd_logic_textio
+R16
+Z33 DPx3 std 6 textio 0 22 m2KQDRRhmF833<<DjYdL70
+R2
+31
+b1
+Z34 Mx2 3 std 6 textio
+R17
+R4
+R12
+R6
+Z35 8vhdl_src/synopsys/std_logic_textio.vhd
+Z36 Fvhdl_src/synopsys/std_logic_textio.vhd
+l0
+L22
+V8YS?iX`WD1REQG`ZRYQGB2
+R9
+R10
+R11
+!s100 <34OlBOka?E186MPPbJ<F1
+Bbody
+DBx4 work 16 std_logic_textio 0 22 8YS?iX`WD1REQG`ZRYQGB2
+R16
+R33
+R2
+31
+R34
+R17
+R4
+l0
+L70
+Vj9DSczGXI>dbiF;m2[GMa2
+R9
+R10
+R11
+nbody
+!s100 6OHe=[AFemLP2O5e01aCn1
+Pstd_logic_unsigned
+R29
+R16
+R2
+31
+b1
+R25
+R30
+R4
+R12
+R6
+Z37 8vhdl_src/synopsys/mti_std_logic_unsigned.vhd
+Z38 Fvhdl_src/synopsys/mti_std_logic_unsigned.vhd
+l0
+L34
+VhEMVMlaNCR^<OOoVNV;m90
+R9
+R10
+R11
+!s100 m;ka?gIZQ?7M5D732VDkQ2
+Bbody
+DBx4 work 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
+R29
+R16
+R2
+31
+R25
+R30
+R4
+l0
+L234
+V1=Y]oOSl8JChnzj5R39ha2
+R9
+R10
+R11
+nbody
+!s100 4k4oOhm[kk0Z>a:GNXQeK2
+Pvital_primitives
+Z39 DPx4 ieee 12 vital_timing 0 22 OBWK>;kUYmkG<OChK2lhV1
+R16
+R2
+30
+b1
+R25
+Mx1 4 ieee 12 vital_timing
+R4
+Z40 w1242971928
+R6
+8vhdl_src/vital95/prmtvs_p.vhd
+Fvhdl_src/vital95/prmtvs_p.vhd
+l0
+L47
+VE9g6AWKAc2T]enMfl94If3
+R9
+Z41 o-87 -novital -novital -work ieee -dirpath {$MODEL_TECH/..}
+R11
+!s100 j6nRfL18l=3@J0:=7g8GH0
+Bbody
+DBx4 work 16 vital_primitives 0 22 E9g6AWKAc2T]enMfl94If3
+R33
+R39
+R16
+R2
+30
+Z42 Mx3 4 ieee 14 std_logic_1164
+Mx2 4 ieee 12 vital_timing
+Z43 Mx1 3 std 6 textio
+R4
+8vhdl_src/vital95/prmtvs_b.vhd
+Fvhdl_src/vital95/prmtvs_b.vhd
+l0
+L26
+V>[EMmIIzoCHn?@614I_=a3
+R9
+R41
+R11
+nbody
+!s100 ccDc[]`DWjj?>mGBe93>82
+Pvital_timing
+R16
+R2
+30
+b1
+R17
+R4
+R40
+R6
+8vhdl_src/vital95/timing_p.vhd
+Fvhdl_src/vital95/timing_p.vhd
+l0
+L46
+VOBWK>;kUYmkG<OChK2lhV1
+R9
+R41
+R11
+!s100 0aicHc]@V^<Hc5ggAgIP82
+Bbody
+DBx4 work 12 vital_timing 0 22 OBWK>;kUYmkG<OChK2lhV1
+R33
+R16
+R2
+30
+R25
+R43
+R4
+8vhdl_src/vital95/timing_b.vhd
+Fvhdl_src/vital95/timing_b.vhd
+l0
+L25
+VfN[Pf:HE;^Z^LCeH6gGI81
+R9
+R41
+R11
+nbody
+!s100 hhU`7L40D93Ij3b8NNlJ>1
--- /dev/null
+m255
+K3
+13
+cModel Technology
+Z0 d/homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh
+T_opt
+Z1 V@4KfU?FbS@FH54NY3BYng0
+Z2 04 12 0 work vga_conf_beh 1
+Z3 =1-0015609eced9-4adf1e22-ea0eb-15eb
+Z4 o-quiet -auto_acc_if_foreign -work work
+Z5 n@_opt
+Z6 OE;O;6.5b;42
+Eboard_driver
+Z7 w1255952276
+Z8 DPx4 work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
+Z9 DPx4 ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
+Z10 DPx4 ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
+Z11 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
+Z12 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd
+Z13 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd
+l0
+L36
+Z14 VBVQhR;nY9[R<n2hUAfP^Z2
+Z15 OE;C;6.5b;42
+32
+Z16 o-work work
+Z17 tExplicit 1
+Z18 !s100 ZmKIT`@9Y:8bV1lIMd:O50
+Abehav
+Z19 DEx4 work 12 board_driver 0 22 BVQhR;nY9[R<n2hUAfP^Z2
+R8
+R9
+R10
+R11
+Z20 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd
+Z21 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd
+l49
+L37
+Z22 VGBN_oSTG]bM6]TXPeRSH52
+R15
+32
+Z23 Mx4 4 ieee 14 std_logic_1164
+Z24 Mx3 4 ieee 18 std_logic_unsigned
+Z25 Mx2 4 ieee 15 std_logic_arith
+Z26 Mx1 4 work 7 vga_pak
+R16
+R17
+Z27 !s100 z`LzgF:SW^5X7Ld12aiE[3
+Evga
+R7
+Z28 DPx57 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh/work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
+Z29 DPx17 __model_tech/ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
+Z30 DPx17 __model_tech/ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
+Z31 DPx17 __model_tech/ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
+32
+Z32 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd
+Z33 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd
+l0
+L38
+Z34 V;Z82Tkc_=iYE3=^SJM?Z72
+R15
+R16
+R17
+Z35 !s100 [Gn7gl]K8XZ[NlCWflEmQ1
+Abehav
+Z36 w1256135072
+DEx57 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh/work 11 vga_control 0 22 OiaY^6HGzj]Hj@bZog<<C2
+Z37 DEx57 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh/work 10 vga_driver 0 22 WM]N=KVQa>:4ozHZC=^hX0
+DEx57 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh/work 12 board_driver 0 22 BVQhR;nY9[R<n2hUAfP^Z2
+Z38 DEx57 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh/work 3 vga 0 22 ;Z82Tkc_=iYE3=^SJM?Z72
+R28
+R29
+R30
+R31
+32
+Z39 Mx4 17 __model_tech/ieee 14 std_logic_1164
+Z40 Mx3 17 __model_tech/ieee 18 std_logic_unsigned
+Z41 Mx2 17 __model_tech/ieee 15 std_logic_arith
+Z42 Mx1 57 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh/work 7 vga_pak
+Z43 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd
+Z44 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd
+l109
+L36
+Z45 V^=j1omIkg8OEUbG72d1?23
+R15
+R16
+R17
+Z46 !s100 >[o9ATEzKLEaUQOnGh0z01
+Cvga_conf_beh
+R38
+DAx57 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh/work 6 vga_tb 9 behaviour 22 I3NFZcjIh_=T`0za;J3h^2
+R28
+R29
+R30
+R31
+Z47 DEx57 /homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh/work 6 vga_tb 0 22 K;WQR0;ZeC2I8`N5aIRdM1
+32
+R39
+R40
+R41
+R42
+Z48 abehaviour
+Z49 evga_tb
+R7
+Z50 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_beh_tb.vhd
+Z51 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_beh_tb.vhd
+l0
+L187
+Z52 VeNNJi03>MIdzNk_IKJFBX0
+R15
+R16
+R17
+Z53 !s100 baoj;WW0d=L:Y@hn2U?=:1
+Evga_control
+R7
+R8
+R9
+R10
+R11
+Z54 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd
+Z55 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd
+l0
+L37
+Z56 VOiaY^6HGzj]Hj@bZog<<C2
+R15
+32
+R16
+R17
+Z57 !s100 ]^V2KE>B7amzdNkAG;;Ie2
+Abehav
+Z58 DEx4 work 11 vga_control 0 22 OiaY^6HGzj]Hj@bZog<<C2
+R8
+R9
+R10
+R11
+Z59 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd
+Z60 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd
+l52
+L36
+Z61 V77PMdiF8Be]?7_MQ4cWnP1
+R15
+32
+R23
+R24
+R25
+R26
+R16
+R17
+Z62 !s100 DKVAKeoe4?H3OFK=6m30b0
+Evga_driver
+Z63 w1256135047
+R28
+R29
+R30
+R31
+32
+Z64 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd
+Z65 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd
+l0
+L37
+Z66 VWM]N=KVQa>:4ozHZC=^hX0
+R15
+R16
+R17
+Z67 !s100 Y<?mNHeGL<kb9W4ng:D_62
+Abehav
+R37
+R28
+R29
+R30
+R31
+32
+R39
+R40
+R41
+R42
+Z68 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd
+Z69 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd
+l89
+L36
+Z70 Ve;Di?_OoPUgXCMBlVURO<1
+R15
+R16
+R17
+Z71 !s100 m[>=IM[TaR5C=MnzMT7>c2
+Pvga_pak
+R29
+R30
+R31
+32
+Mx3 17 __model_tech/ieee 14 std_logic_1164
+Mx2 17 __model_tech/ieee 18 std_logic_unsigned
+Mx1 17 __model_tech/ieee 15 std_logic_arith
+R7
+Z72 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
+Z73 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
+l0
+L35
+Z74 VHkmzP=gd;mD@MOhh4AYKl3
+R15
+R16
+R17
+Z75 !s100 VL:Z2?FJISz9N5>XaK:5k0
+Evga_tb
+R7
+R28
+R29
+R30
+R31
+32
+R50
+R51
+l0
+L37
+Z76 VK;WQR0;ZeC2I8`N5aIRdM1
+R15
+R16
+R17
+Z77 !s100 KBk8Lb76>dJd2ihUfkYfd2
+Abehaviour
+R38
+R28
+R29
+R30
+R31
+R47
+32
+R39
+R40
+R41
+R42
+l100
+L45
+Z78 VI3NFZcjIh_=T`0za;J3h^2
+R15
+R16
+R17
+Z79 !s100 gzdc1SL=je=>NSFaLPW;]2
--- /dev/null
+m255
+K3
+13
+cModel Technology
+Z0 d/homes/burban/didelu/dide_16/bsp2/Designflow/sim/beh
+T_opt
+V@4KfU?FbS@FH54NY3BYng0
+04 12 0 work vga_conf_beh 1
+=1-0015609eced9-4adf1e22-ea0eb-15eb
+o-quiet -auto_acc_if_foreign -work work
+n@_opt
+OE;O;6.5b;42
+Eboard_driver
+Z1 w1255952276
+Z2 DPx4 work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
+Z3 DPx4 ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
+Z4 DPx4 ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
+Z5 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd
+l0
+L36
+VBVQhR;nY9[R<n2hUAfP^Z2
+Z6 OE;C;6.5b;42
+32
+Z7 o-work work
+Z8 tExplicit 1
+!s100 ZmKIT`@9Y:8bV1lIMd:O50
+Abehav
+DEx4 work 12 board_driver 0 22 BVQhR;nY9[R<n2hUAfP^Z2
+R2
+R3
+R4
+R5
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd
+l49
+L37
+VGBN_oSTG]bM6]TXPeRSH52
+R6
+32
+Z9 Mx4 4 ieee 14 std_logic_1164
+Z10 Mx3 4 ieee 18 std_logic_unsigned
+Z11 Mx2 4 ieee 15 std_logic_arith
+Z12 Mx1 4 work 7 vga_pak
+R7
+R8
+!s100 z`LzgF:SW^5X7Ld12aiE[3
+Evga
+R1
+R2
+R3
+R4
+R5
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd
+l0
+L38
+V;Z82Tkc_=iYE3=^SJM?Z72
+R6
+32
+R7
+R8
+!s100 [Gn7gl]K8XZ[NlCWflEmQ1
+Abehav
+w1256135072
+Z13 DEx4 work 3 vga 0 22 ;Z82Tkc_=iYE3=^SJM?Z72
+R2
+R3
+R4
+R5
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd
+l109
+L36
+V^=j1omIkg8OEUbG72d1?23
+!s100 >[o9ATEzKLEaUQOnGh0z01
+R6
+32
+R9
+R10
+R11
+R12
+R7
+R8
+Cvga_conf_beh
+abehaviour
+evga_tb
+R13
+DAx4 work 6 vga_tb 9 behaviour 22 I3NFZcjIh_=T`0za;J3h^2
+R2
+R3
+R4
+R5
+Z14 DEx4 work 6 vga_tb 0 22 K;WQR0;ZeC2I8`N5aIRdM1
+R1
+Z15 8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_beh_tb.vhd
+Z16 F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_beh_tb.vhd
+l0
+L187
+VeNNJi03>MIdzNk_IKJFBX0
+!s100 baoj;WW0d=L:Y@hn2U?=:1
+R6
+32
+R9
+R10
+R11
+R12
+R7
+R8
+Evga_control
+R1
+R2
+R3
+R4
+R5
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd
+l0
+L37
+VOiaY^6HGzj]Hj@bZog<<C2
+R6
+32
+R7
+R8
+!s100 ]^V2KE>B7amzdNkAG;;Ie2
+Abehav
+DEx4 work 11 vga_control 0 22 OiaY^6HGzj]Hj@bZog<<C2
+R2
+R3
+R4
+R5
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd
+l52
+L36
+V77PMdiF8Be]?7_MQ4cWnP1
+R6
+32
+R9
+R10
+R11
+R12
+R7
+R8
+!s100 DKVAKeoe4?H3OFK=6m30b0
+Evga_driver
+Z17 w1256135047
+R2
+R3
+R4
+R5
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd
+l0
+L37
+VWM]N=KVQa>:4ozHZC=^hX0
+R6
+32
+R7
+R8
+!s100 Y<?mNHeGL<kb9W4ng:D_62
+Abehav
+DEx4 work 10 vga_driver 0 22 WM]N=KVQa>:4ozHZC=^hX0
+R2
+R3
+R4
+R5
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd
+l89
+L36
+Ve;Di?_OoPUgXCMBlVURO<1
+R6
+32
+R9
+R10
+R11
+R12
+R7
+R8
+!s100 m[>=IM[TaR5C=MnzMT7>c2
+Pvga_pak
+R3
+R4
+R5
+R1
+8/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
+F/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd
+l0
+L35
+VHkmzP=gd;mD@MOhh4AYKl3
+R6
+32
+Z18 Mx3 4 ieee 14 std_logic_1164
+Mx2 4 ieee 18 std_logic_unsigned
+Z19 Mx1 4 ieee 15 std_logic_arith
+R7
+R8
+!s100 VL:Z2?FJISz9N5>XaK:5k0
+Evga_tb
+R1
+R2
+R3
+R4
+R5
+R15
+R16
+l0
+L37
+VK;WQR0;ZeC2I8`N5aIRdM1
+!s100 KBk8Lb76>dJd2ihUfkYfd2
+R6
+32
+R7
+R8
+Abehaviour
+R2
+R3
+R4
+R5
+R14
+l100
+L45
+Z20 VI3NFZcjIh_=T`0za;J3h^2
+Z21 !s100 gzdc1SL=je=>NSFaLPW;]2
+R6
+32
+R9
+R10
+R11
+R12
+R7
+R8
--- /dev/null
+m255
+K3
+cModel Technology
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Title : board_driver architecture\r
+-- Project : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File : board_driver.vhd\r
+-- Author : Thomas Handl\r
+-- Company : TU Wien\r
+-- Created : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: display number on 7-segment display\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions :\r
+-- Date Version Author Description\r
+-- 2004-12-15 1.0 handl Created\r
+-- 2006-02-24 2.0 ST revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+architecture behav of board_driver is\r
+\r
+ attribute syn_preserve : boolean;\r
+ attribute syn_preserve of behav : architecture is true;\r
+\r
+\r
+ signal display_value : std_logic_vector(2*BCD_WIDTH-1 downto 0);\r
+ signal ten_value : std_logic_vector(BCD_WIDTH-1 downto 0);\r
+ signal one_value : std_logic_vector(BCD_WIDTH-1 downto 0);\r
+ signal digit_left : std_logic_vector(SEG_WIDTH-1 downto 0);\r
+ signal digit_right : std_logic_vector(SEG_WIDTH-1 downto 0);\r
+\r
+begin\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- generate control data\r
+ -----------------------------------------------------------------------------\r
+\r
+\r
+ display_value <= "00000001"; -- vector of two BCD coded numbers to be displayed\r
+ one_value <= display_value(BCD_WIDTH-1 downto 0); -- BCD number to be displayed in right digit\r
+ ten_value <= display_value(2*BCD_WIDTH-1 downto BCD_WIDTH); -- BCD number to be displayed in left digit\r
+\r
+\r
+ SEG_DATA: process(reset, one_value, ten_value)\r
+ begin\r
+ if (reset = RES_ACT) then -- upon reset\r
+ digit_left <= DIGIT_OFF; -- ... switch off display\r
+ digit_right <= DIGIT_OFF;\r
+ else -- during operation\r
+ case one_value is -- ...display "one" position according\r
+ when "0000" => digit_right <= DIGIT_ZERO; -- ...to translation table\r
+ when "0001" => digit_right <= DIGIT_ONE;\r
+ when "0010" => digit_right <= DIGIT_TWO;\r
+ when "0011" => digit_right <= DIGIT_THREE;\r
+ when "0100" => digit_right <= DIGIT_FOUR;\r
+ when "0101" => digit_right <= DIGIT_FIVE;\r
+ when "0110" => digit_right <= DIGIT_SIX;\r
+ when "0111" => digit_right <= DIGIT_SEVEN;\r
+ when "1000" => digit_right <= DIGIT_EIGHT;\r
+ when "1001" => digit_right <= DIGIT_NINE;\r
+ when others => digit_right <= DIGIT_F; -- use "F" as overflow\r
+ end case;\r
+\r
+ case ten_value is -- same for "ten" position\r
+ when "0000" => digit_left <= DIGIT_ZERO;\r
+ when "0001" => digit_left <= DIGIT_ONE;\r
+ when "0010" => digit_left <= DIGIT_TWO;\r
+ when "0011" => digit_left <= DIGIT_THREE;\r
+ when "0100" => digit_left <= DIGIT_FOUR;\r
+ when "0101" => digit_left <= DIGIT_FIVE;\r
+ when "0110" => digit_left <= DIGIT_SIX;\r
+ when "0111" => digit_left <= DIGIT_SEVEN;\r
+ when "1000" => digit_left <= DIGIT_EIGHT;\r
+ when "1001" => digit_left <= DIGIT_NINE;\r
+ when others => digit_left <= DIGIT_F;\r
+ end case;\r
+ end if;\r
+ end process;\r
+\r
+\r
+-- combine the two digits to one bus\r
+ seven_seg(SEG_WIDTH-1 downto 0) <= digit_right;\r
+ seven_seg(2*SEG_WIDTH-1 downto SEG_WIDTH) <= digit_left;\r
+ \r
+end behav;\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Title : board_driver entity\r
+-- Project : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File : board_driver_ent.vhd\r
+-- Author : Thomas Handl\r
+-- Company : TU Wien\r
+-- Created : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: display number on 7-segment display\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions :\r
+-- Date Version Author Description\r
+-- 2004-12-15 1.0 handl Created\r
+-- 2006-02-24 2.0 ST revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ENTITY\r
+-------------------------------------------------------------------------------\r
+\r
+entity board_driver is\r
+ \r
+ port (\r
+ reset : in std_logic;\r
+ seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0)\r
+ ); \r
+end board_driver;\r
--- /dev/null
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement default branches.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/report/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL/Verilog immediate assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+; level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name: # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable System Verilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during
+; simulation. If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: these ini variables can be overriden by the vsim command
+; line switch "-onfinish <ask|stop|exit>".
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA concurrent assertion pass enable.
+; For SVA, Default is on when the assertion has a pass action block, or
+; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
+; For PSL, Default is on only when vsim switch "-assertdebug" is used
+; and the vopt "+acc=a" flag is active.
+; AssertionPassEnable = 0
+
+; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL/SVA concurrent assertion pass limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = 1
+
+; Set PSL/SVA concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
+; are included for toggle coverage. This leads to a longer simulation time with bigger
+; arrays covered with toggle coverage. Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable is 1
+; SVCovergroup63Compatibility = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
+; Sv_Seed = 0
+
+; Maximum size of dynamic arrays that are resized during randomize().
+; The default is 1000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 1000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; The default is 0 (no error).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures (SystemVerilog).
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; When SolveFailDebug is enabled, this value specifies the algorithm used to
+; discover conflicts between constraints for randomize() failures.
+; The default is "many".
+;
+; Valid schemes are:
+; "many" = best for determining conflicts due to many related constraints
+; "few" = best for determining conflicts due to few related constraints
+;
+; SolveFailDebugScheme = many
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum number of constraint subsets that will be tested for
+; conflicts.
+; The default is 0 (no limit).
+; SolveFailDebugLimit = 0
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum size of constraint subsets that will be tested for
+; conflicts.
+; The default value is 0 (no limit).
+; SolveFailDebugMaxSet = 0
+
+; Maximum size of the solution graph that may be generated during randomize().
+; This value can be used to force randomize() to abort if the memory
+; requirements of the constraint scenario exceeds the specified limit. This
+; value is specified in 1000s of nodes.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Maximum number of evaluations that may be performed on the solution graph
+; generated during randomize(). This value can be used to force randomize() to
+; abort if the complexity of the constraint scenario (in time) exceeds the
+; specified limit. This value is specified in 10000s of evaluations.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of
+; the constraint solver for others.
+; The default value is "" (no options).
+;
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints
+; n = disable bit interleaving for all constraints
+; r = reverse bit interleaving
+;
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; Note: To achieve the same random sequences, solver optimizations and/or
+; bug fixes introduced since the specified release may be disabled -
+; yielding the performance / behavior of the prior release.
+; Default value set to "" (random compatibility not required).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
--- /dev/null
+:010000001ce3\r
+:010001001ce2\r
+:010002001ce1\r
+:010003001ce0\r
+:010004001cdf\r
+:010005001cde\r
+:010006001cdd\r
+:010007001cdc\r
+:010008001cdb\r
+:010009001cda\r
+:01000a001cd9\r
+:01000b001cd8\r
+:01000c001cd7\r
+:01000d001cd6\r
+:01000e001cd5\r
+:01000f001cd4\r
+:010010001cd3\r
+:010011001cd2\r
+:010012001cd1\r
+:010013001cd0\r
+:010014001ccf\r
+:010015001cce\r
+:010016001ccd\r
+:010017001ccc\r
+:010018001ccb\r
+:010019001cca\r
+:01001a001cc9\r
+:01001b001cc8\r
+:01001c001cc7\r
+:01001d001cc6\r
+:01001e001cc5\r
+:01001f001cc4\r
+:010020001cc3\r
+:010021001cc2\r
+:010022001cc1\r
+:010023001cc0\r
+:010024001cbf\r
+:010025001cbe\r
+:010026001cbd\r
+:010027001cbc\r
+:010028001cbb\r
+:010029001cba\r
+:01002a001cb9\r
+:01002b001cb8\r
+:01002c001cb7\r
+:01002d001cb6\r
+:01002e001cb5\r
+:01002f001cb4\r
+:010030001cb3\r
+:010031001cb2\r
+:010032001cb1\r
+:010033001cb0\r
+:010034001caf\r
+:010035001cae\r
+:010036001cad\r
+:010037001cac\r
+:010038001cab\r
+:010039001caa\r
+:01003a001ca9\r
+:01003b001ca8\r
+:01003c001ca7\r
+:01003d001ca6\r
+:01003e001ca5\r
+:01003f001ca4\r
+:0100400003bc\r
+:0100410000be\r
+:0100420000bd\r
+:0100430000bc\r
+:0100440000bb\r
+:0100450000ba\r
+:0100460000b9\r
+:0100470000b8\r
+:0100480000b7\r
+:0100490000b6\r
+:01004a0000b5\r
+:01004b0000b4\r
+:01004c0000b3\r
+:01004d0000b2\r
+:01004e0000b1\r
+:01004f0000b0\r
+:0100500000af\r
+:0100510000ae\r
+:0100520000ad\r
+:0100530000ac\r
+:0100540000ab\r
+:0100550000aa\r
+:0100560000a9\r
+:0100570000a8\r
+:0100580000a7\r
+:0100590000a6\r
+:01005a0000a5\r
+:01005b0000a4\r
+:01005c0000a3\r
+:01005d0000a2\r
+:01005e0000a1\r
+:01005f0000a0\r
+:01006000009f\r
+:01006100009e\r
+:01006200009d\r
+:01006300009c\r
+:01006400009b\r
+:01006500009a\r
+:010066000099\r
+:010067000098\r
+:010068000097\r
+:010069000096\r
+:01006a000095\r
+:01006b000094\r
+:01006c000093\r
+:01006d000092\r
+:01006e000091\r
+:01006f000090\r
+:01007000008f\r
+:01007100008e\r
+:01007200008d\r
+:01007300008c\r
+:01007400008b\r
+:01007500008a\r
+:010076000089\r
+:010077000088\r
+:010078000087\r
+:010079000086\r
+:01007a000085\r
+:01007b000084\r
+:01007c000083\r
+:01007d000082\r
+:01007e000081\r
+:01007f0090f0\r
+:01008000037c\r
+:01008100007e\r
+:01008200007d\r
+:01008300007c\r
+:01008400007b\r
+:01008500007a\r
+:010086000079\r
+:010087000078\r
+:010088000077\r
+:010089000076\r
+:01008a000075\r
+:01008b000074\r
+:01008c000073\r
+:01008d000072\r
+:01008e000071\r
+:01008f000070\r
+:01009000006f\r
+:01009100006e\r
+:01009200006d\r
+:01009300006c\r
+:01009400006b\r
+:01009500006a\r
+:010096000069\r
+:010097000068\r
+:010098000067\r
+:010099000066\r
+:01009a000065\r
+:01009b000064\r
+:01009c000063\r
+:01009d000062\r
+:01009e000061\r
+:01009f000060\r
+:0100a000005f\r
+:0100a100005e\r
+:0100a200005d\r
+:0100a300005c\r
+:0100a400005b\r
+:0100a500005a\r
+:0100a6000059\r
+:0100a7000058\r
+:0100a8000057\r
+:0100a9000056\r
+:0100aa000055\r
+:0100ab000054\r
+:0100ac000053\r
+:0100ad000052\r
+:0100ae000051\r
+:0100af000050\r
+:0100b000004f\r
+:0100b100004e\r
+:0100b200004d\r
+:0100b300004c\r
+:0100b400004b\r
+:0100b500004a\r
+:0100b6000049\r
+:0100b7000048\r
+:0100b8000047\r
+:0100b9000046\r
+:0100ba000045\r
+:0100bb000044\r
+:0100bc000043\r
+:0100bd000042\r
+:0100be000041\r
+:0100bf0090b0\r
+:0100c000033c\r
+:0100c100003e\r
+:0100c200003d\r
+:0100c300003c\r
+:0100c400003b\r
+:0100c500003a\r
+:0100c6000039\r
+:0100c7000038\r
+:0100c8000037\r
+:0100c9000036\r
+:0100ca000035\r
+:0100cb000034\r
+:0100cc000033\r
+:0100cd000032\r
+:0100ce000031\r
+:0100cf000030\r
+:0100d000002f\r
+:0100d100002e\r
+:0100d200002d\r
+:0100d300002c\r
+:0100d400002b\r
+:0100d500002a\r
+:0100d6000029\r
+:0100d7000028\r
+:0100d8000027\r
+:0100d9000026\r
+:0100da000025\r
+:0100db000024\r
+:0100dc000023\r
+:0100dd000022\r
+:0100de000021\r
+:0100df000020\r
+:0100e000001f\r
+:0100e100001e\r
+:0100e200001d\r
+:0100e300001c\r
+:0100e400001b\r
+:0100e500001a\r
+:0100e6000019\r
+:0100e7000018\r
+:0100e8000017\r
+:0100e9000016\r
+:0100ea000015\r
+:0100eb000014\r
+:0100ec000013\r
+:0100ed000012\r
+:0100ee000011\r
+:0100ef000010\r
+:0100f000000f\r
+:0100f100000e\r
+:0100f200000d\r
+:0100f300000c\r
+:0100f400000b\r
+:0100f500000a\r
+:0100f6000009\r
+:0100f7000008\r
+:0100f8000007\r
+:0100f9000006\r
+:0100fa000005\r
+:0100fb000004\r
+:0100fc000003\r
+:0100fd000002\r
+:0100fe000001\r
+:0100ff009070\r
+:0101000003fb\r
+:0101010000fd\r
+:0101020000fc\r
+:0101030000fb\r
+:0101040000fa\r
+:0101050000f9\r
+:0101060000f8\r
+:0101070000f7\r
+:0101080000f6\r
+:0101090000f5\r
+:01010a0000f4\r
+:01010b0000f3\r
+:01010c0000f2\r
+:01010d0000f1\r
+:01010e0000f0\r
+:01010f0000ef\r
+:0101100000ee\r
+:0101110000ed\r
+:0101120000ec\r
+:0101130000eb\r
+:0101140000ea\r
+:0101150000e9\r
+:0101160000e8\r
+:0101170000e7\r
+:0101180000e6\r
+:0101190000e5\r
+:01011a0000e4\r
+:01011b0000e3\r
+:01011c0000e2\r
+:01011d0000e1\r
+:01011e0000e0\r
+:01011f0000df\r
+:0101200000de\r
+:0101210000dd\r
+:0101220000dc\r
+:0101230000db\r
+:0101240000da\r
+:0101250000d9\r
+:0101260000d8\r
+:0101270000d7\r
+:0101280000d6\r
+:0101290000d5\r
+:01012a0000d4\r
+:01012b0000d3\r
+:01012c0000d2\r
+:01012d0000d1\r
+:01012e0000d0\r
+:01012f0000cf\r
+:0101300000ce\r
+:0101310000cd\r
+:0101320000cc\r
+:0101330000cb\r
+:0101340000ca\r
+:0101350000c9\r
+:0101360000c8\r
+:0101370000c7\r
+:0101380000c6\r
+:0101390000c5\r
+:01013a0000c4\r
+:01013b0000c3\r
+:01013c0000c2\r
+:01013d0000c1\r
+:01013e0000c0\r
+:01013f00902f\r
+:0101400003bb\r
+:0101410000bd\r
+:0101420000bc\r
+:0101430000bb\r
+:0101440000ba\r
+:0101450000b9\r
+:0101460000b8\r
+:0101470000b7\r
+:0101480000b6\r
+:0101490000b5\r
+:01014a0000b4\r
+:01014b0000b3\r
+:01014c0000b2\r
+:01014d0000b1\r
+:01014e0000b0\r
+:01014f0000af\r
+:0101500000ae\r
+:0101510000ad\r
+:0101520000ac\r
+:0101530000ab\r
+:0101540000aa\r
+:0101550000a9\r
+:0101560000a8\r
+:0101570000a7\r
+:0101580000a6\r
+:0101590000a5\r
+:01015a0000a4\r
+:01015b0000a3\r
+:01015c0000a2\r
+:01015d0000a1\r
+:01015e0000a0\r
+:01015f00009f\r
+:01016000009e\r
+:01016100009d\r
+:01016200009c\r
+:01016300009b\r
+:01016400009a\r
+:010165000099\r
+:010166000098\r
+:010167000097\r
+:010168000096\r
+:010169000095\r
+:01016a000094\r
+:01016b000093\r
+:01016c000092\r
+:01016d000091\r
+:01016e000090\r
+:01016f00008f\r
+:01017000008e\r
+:01017100008d\r
+:01017200008c\r
+:01017300008b\r
+:01017400008a\r
+:010175000089\r
+:010176000088\r
+:010177000087\r
+:010178000086\r
+:010179000085\r
+:01017a000084\r
+:01017b000083\r
+:01017c000082\r
+:01017d000081\r
+:01017e000080\r
+:01017f0090ef\r
+:01018000037b\r
+:01018100007d\r
+:01018200007c\r
+:01018300007b\r
+:01018400007a\r
+:010185000079\r
+:010186000078\r
+:010187000077\r
+:010188000076\r
+:010189000075\r
+:01018a000074\r
+:01018b000073\r
+:01018c000072\r
+:01018d000071\r
+:01018e000070\r
+:01018f00006f\r
+:01019000006e\r
+:01019100006d\r
+:01019200006c\r
+:01019300006b\r
+:01019400006a\r
+:010195000069\r
+:010196000068\r
+:010197000067\r
+:010198000066\r
+:010199000065\r
+:01019a000064\r
+:01019b000063\r
+:01019c000062\r
+:01019d000061\r
+:01019e000060\r
+:01019f00005f\r
+:0101a000005e\r
+:0101a100005d\r
+:0101a200005c\r
+:0101a300005b\r
+:0101a400005a\r
+:0101a5000059\r
+:0101a6000058\r
+:0101a7000057\r
+:0101a8000056\r
+:0101a9000055\r
+:0101aa000054\r
+:0101ab000053\r
+:0101ac000052\r
+:0101ad000051\r
+:0101ae000050\r
+:0101af00004f\r
+:0101b000004e\r
+:0101b100004d\r
+:0101b200004c\r
+:0101b300004b\r
+:0101b400004a\r
+:0101b5000049\r
+:0101b6000048\r
+:0101b7000047\r
+:0101b8000046\r
+:0101b9000045\r
+:0101ba000044\r
+:0101bb000043\r
+:0101bc000042\r
+:0101bd000041\r
+:0101be000040\r
+:0101bf0090af\r
+:0101c000033b\r
+:0101c100003d\r
+:0101c200003c\r
+:0101c300003b\r
+:0101c400003a\r
+:0101c5000039\r
+:0101c6000038\r
+:0101c7000037\r
+:0101c8000036\r
+:0101c9000035\r
+:0101ca000034\r
+:0101cb000033\r
+:0101cc000032\r
+:0101cd000031\r
+:0101ce000030\r
+:0101cf00002f\r
+:0101d000002e\r
+:0101d100002d\r
+:0101d200002c\r
+:0101d300002b\r
+:0101d400002a\r
+:0101d5000029\r
+:0101d6000028\r
+:0101d7000027\r
+:0101d8000026\r
+:0101d9000025\r
+:0101da000024\r
+:0101db000023\r
+:0101dc000022\r
+:0101dd000021\r
+:0101de000020\r
+:0101df00001f\r
+:0101e000001e\r
+:0101e100001d\r
+:0101e200001c\r
+:0101e300001b\r
+:0101e400001a\r
+:0101e5000019\r
+:0101e6000018\r
+:0101e7000017\r
+:0101e8000016\r
+:0101e9000015\r
+:0101ea000014\r
+:0101eb000013\r
+:0101ec000012\r
+:0101ed000011\r
+:0101ee000010\r
+:0101ef00000f\r
+:0101f000000e\r
+:0101f100000d\r
+:0101f200000c\r
+:0101f300000b\r
+:0101f400000a\r
+:0101f5000009\r
+:0101f6000008\r
+:0101f7000007\r
+:0101f8000006\r
+:0101f9000005\r
+:0101fa000004\r
+:0101fb000003\r
+:0101fc000002\r
+:0101fd000001\r
+:0101fe000000\r
+:0101ff00906f\r
+:0102000003fa\r
+:0102010000fc\r
+:0102020000fb\r
+:0102030000fa\r
+:0102040000f9\r
+:0102050000f8\r
+:0102060000f7\r
+:0102070000f6\r
+:0102080000f5\r
+:0102090000f4\r
+:01020a0000f3\r
+:01020b0000f2\r
+:01020c0000f1\r
+:01020d0000f0\r
+:01020e0000ef\r
+:01020f0000ee\r
+:0102100000ed\r
+:0102110000ec\r
+:0102120000eb\r
+:0102130000ea\r
+:0102140000e9\r
+:0102150000e8\r
+:0102160000e7\r
+:0102170000e6\r
+:0102180000e5\r
+:0102190000e4\r
+:01021a0000e3\r
+:01021b0000e2\r
+:01021c0000e1\r
+:01021d0000e0\r
+:01021e0000df\r
+:01021f0000de\r
+:0102200000dd\r
+:0102210000dc\r
+:0102220000db\r
+:0102230000da\r
+:0102240000d9\r
+:0102250000d8\r
+:0102260000d7\r
+:0102270000d6\r
+:0102280000d5\r
+:0102290000d4\r
+:01022a0000d3\r
+:01022b0000d2\r
+:01022c0000d1\r
+:01022d0000d0\r
+:01022e0000cf\r
+:01022f0000ce\r
+:0102300000cd\r
+:0102310000cc\r
+:0102320000cb\r
+:0102330000ca\r
+:0102340000c9\r
+:0102350000c8\r
+:0102360000c7\r
+:0102370000c6\r
+:0102380000c5\r
+:0102390000c4\r
+:01023a0000c3\r
+:01023b0000c2\r
+:01023c0000c1\r
+:01023d0000c0\r
+:01023e0000bf\r
+:01023f00902e\r
+:0102400003ba\r
+:0102410000bc\r
+:0102420000bb\r
+:0102430000ba\r
+:0102440000b9\r
+:0102450000b8\r
+:0102460000b7\r
+:0102470000b6\r
+:0102480000b5\r
+:0102490000b4\r
+:01024a0000b3\r
+:01024b0000b2\r
+:01024c0000b1\r
+:01024d0000b0\r
+:01024e0000af\r
+:01024f0000ae\r
+:0102500000ad\r
+:0102510000ac\r
+:0102520000ab\r
+:0102530000aa\r
+:0102540000a9\r
+:0102550000a8\r
+:0102560000a7\r
+:0102570000a6\r
+:0102580000a5\r
+:0102590000a4\r
+:01025a0000a3\r
+:01025b0000a2\r
+:01025c0000a1\r
+:01025d0000a0\r
+:01025e00009f\r
+:01025f00009e\r
+:01026000009d\r
+:01026100009c\r
+:01026200009b\r
+:01026300009a\r
+:010264000099\r
+:010265000098\r
+:010266000097\r
+:010267000096\r
+:010268000095\r
+:010269000094\r
+:01026a000093\r
+:01026b000092\r
+:01026c000091\r
+:01026d000090\r
+:01026e00008f\r
+:01026f00008e\r
+:01027000008d\r
+:01027100008c\r
+:01027200008b\r
+:01027300008a\r
+:010274000089\r
+:010275000088\r
+:010276000087\r
+:010277000086\r
+:010278000085\r
+:010279000084\r
+:01027a000083\r
+:01027b000082\r
+:01027c000081\r
+:01027d000080\r
+:01027e00007f\r
+:01027f0090ee\r
+:01028000037a\r
+:01028100007c\r
+:01028200007b\r
+:01028300007a\r
+:010284000079\r
+:010285000078\r
+:010286000077\r
+:010287000076\r
+:010288000075\r
+:010289000074\r
+:01028a000073\r
+:01028b000072\r
+:01028c000071\r
+:01028d000070\r
+:01028e00006f\r
+:01028f00006e\r
+:01029000006d\r
+:01029100006c\r
+:01029200006b\r
+:01029300006a\r
+:010294000069\r
+:010295000068\r
+:010296000067\r
+:010297000066\r
+:010298000065\r
+:010299000064\r
+:01029a000063\r
+:01029b000062\r
+:01029c000061\r
+:01029d000060\r
+:01029e00005f\r
+:01029f00005e\r
+:0102a000005d\r
+:0102a100005c\r
+:0102a200005b\r
+:0102a300005a\r
+:0102a4000059\r
+:0102a5000058\r
+:0102a6000057\r
+:0102a7000056\r
+:0102a8000055\r
+:0102a9000054\r
+:0102aa000053\r
+:0102ab000052\r
+:0102ac000051\r
+:0102ad000050\r
+:0102ae00004f\r
+:0102af00004e\r
+:0102b000004d\r
+:0102b100004c\r
+:0102b200004b\r
+:0102b300004a\r
+:0102b4000049\r
+:0102b5000048\r
+:0102b6000047\r
+:0102b7000046\r
+:0102b8000045\r
+:0102b9000044\r
+:0102ba000043\r
+:0102bb000042\r
+:0102bc000041\r
+:0102bd000040\r
+:0102be00003f\r
+:0102bf0090ae\r
+:0102c000033a\r
+:0102c100003c\r
+:0102c200003b\r
+:0102c300003a\r
+:0102c4000039\r
+:0102c5000038\r
+:0102c6000037\r
+:0102c7000036\r
+:0102c8000035\r
+:0102c9000034\r
+:0102ca000033\r
+:0102cb000032\r
+:0102cc000031\r
+:0102cd000030\r
+:0102ce00002f\r
+:0102cf00002e\r
+:0102d000002d\r
+:0102d100002c\r
+:0102d200002b\r
+:0102d300002a\r
+:0102d4000029\r
+:0102d5000028\r
+:0102d6000027\r
+:0102d7000026\r
+:0102d8000025\r
+:0102d9000024\r
+:0102da000023\r
+:0102db000022\r
+:0102dc000021\r
+:0102dd000020\r
+:0102de00001f\r
+:0102df00001e\r
+:0102e000001d\r
+:0102e100001c\r
+:0102e200001b\r
+:0102e300001a\r
+:0102e4000019\r
+:0102e5000018\r
+:0102e6000017\r
+:0102e7000016\r
+:0102e8000015\r
+:0102e9000014\r
+:0102ea000013\r
+:0102eb000012\r
+:0102ec000011\r
+:0102ed000010\r
+:0102ee00000f\r
+:0102ef00000e\r
+:0102f000000d\r
+:0102f100000c\r
+:0102f200000b\r
+:0102f300000a\r
+:0102f4000009\r
+:0102f5000008\r
+:0102f6000007\r
+:0102f7000006\r
+:0102f8000005\r
+:0102f9000004\r
+:0102fa000003\r
+:0102fb000002\r
+:0102fc000001\r
+:0102fd000000\r
+:0102fe0000ff\r
+:0102ff00906e\r
+:0103000003f9\r
+:0103010000fb\r
+:0103020000fa\r
+:0103030000f9\r
+:0103040000f8\r
+:0103050000f7\r
+:0103060000f6\r
+:0103070000f5\r
+:0103080000f4\r
+:0103090000f3\r
+:01030a0000f2\r
+:01030b0000f1\r
+:01030c0000f0\r
+:01030d0000ef\r
+:01030e0000ee\r
+:01030f0000ed\r
+:0103100000ec\r
+:0103110000eb\r
+:0103120000ea\r
+:0103130000e9\r
+:0103140000e8\r
+:0103150000e7\r
+:0103160000e6\r
+:0103170000e5\r
+:0103180000e4\r
+:0103190000e3\r
+:01031a0000e2\r
+:01031b0000e1\r
+:01031c0000e0\r
+:01031d0000df\r
+:01031e0000de\r
+:01031f0000dd\r
+:0103200000dc\r
+:0103210000db\r
+:0103220000da\r
+:0103230000d9\r
+:0103240000d8\r
+:0103250000d7\r
+:0103260000d6\r
+:0103270000d5\r
+:0103280000d4\r
+:0103290000d3\r
+:01032a0000d2\r
+:01032b0000d1\r
+:01032c0000d0\r
+:01032d0000cf\r
+:01032e0000ce\r
+:01032f0000cd\r
+:0103300000cc\r
+:0103310000cb\r
+:0103320000ca\r
+:0103330000c9\r
+:0103340000c8\r
+:0103350000c7\r
+:0103360000c6\r
+:0103370000c5\r
+:0103380000c4\r
+:0103390000c3\r
+:01033a0000c2\r
+:01033b0000c1\r
+:01033c0000c0\r
+:01033d0000bf\r
+:01033e0000be\r
+:01033f00902d\r
+:0103400003b9\r
+:0103410000bb\r
+:0103420000ba\r
+:0103430000b9\r
+:0103440000b8\r
+:0103450000b7\r
+:0103460000b6\r
+:0103470000b5\r
+:0103480000b4\r
+:0103490000b3\r
+:01034a0000b2\r
+:01034b0000b1\r
+:01034c0000b0\r
+:01034d0000af\r
+:01034e0000ae\r
+:01034f0000ad\r
+:0103500000ac\r
+:0103510000ab\r
+:0103520000aa\r
+:0103530000a9\r
+:0103540000a8\r
+:0103550000a7\r
+:0103560000a6\r
+:0103570000a5\r
+:0103580000a4\r
+:0103590000a3\r
+:01035a0000a2\r
+:01035b0000a1\r
+:01035c0000a0\r
+:01035d00009f\r
+:01035e00009e\r
+:01035f00009d\r
+:01036000009c\r
+:01036100009b\r
+:01036200009a\r
+:010363000099\r
+:010364000098\r
+:010365000097\r
+:010366000096\r
+:010367000095\r
+:010368000094\r
+:010369000093\r
+:01036a000092\r
+:01036b000091\r
+:01036c000090\r
+:01036d00008f\r
+:01036e00008e\r
+:01036f00008d\r
+:01037000008c\r
+:01037100008b\r
+:01037200008a\r
+:010373000089\r
+:010374000088\r
+:010375000087\r
+:010376000086\r
+:010377000085\r
+:010378000084\r
+:010379000083\r
+:01037a000082\r
+:01037b000081\r
+:01037c000080\r
+:01037d00007f\r
+:01037e00007e\r
+:01037f0090ed\r
+:010380000379\r
+:01038100007b\r
+:01038200007a\r
+:010383000079\r
+:010384000078\r
+:010385000077\r
+:010386000076\r
+:010387000075\r
+:010388000074\r
+:010389000073\r
+:01038a000072\r
+:01038b000071\r
+:01038c000070\r
+:01038d00006f\r
+:01038e00006e\r
+:01038f00006d\r
+:01039000006c\r
+:01039100006b\r
+:01039200006a\r
+:010393000069\r
+:010394000068\r
+:010395000067\r
+:010396000066\r
+:010397000065\r
+:010398000064\r
+:010399000063\r
+:01039a000062\r
+:01039b000061\r
+:01039c000060\r
+:01039d00005f\r
+:01039e00005e\r
+:01039f00005d\r
+:0103a000005c\r
+:0103a100005b\r
+:0103a200005a\r
+:0103a3000059\r
+:0103a4000058\r
+:0103a5000057\r
+:0103a6000056\r
+:0103a7000055\r
+:0103a8000054\r
+:0103a9000053\r
+:0103aa000052\r
+:0103ab000051\r
+:0103ac000050\r
+:0103ad00004f\r
+:0103ae00004e\r
+:0103af00004d\r
+:0103b000004c\r
+:0103b100004b\r
+:0103b200004a\r
+:0103b3000049\r
+:0103b4000048\r
+:0103b5000047\r
+:0103b6000046\r
+:0103b7000045\r
+:0103b8000044\r
+:0103b9000043\r
+:0103ba000042\r
+:0103bb000041\r
+:0103bc000040\r
+:0103bd00003f\r
+:0103be00003e\r
+:0103bf0090ad\r
+:0103c0000339\r
+:0103c100003b\r
+:0103c200003a\r
+:0103c3000039\r
+:0103c4000038\r
+:0103c5000037\r
+:0103c6000036\r
+:0103c7000035\r
+:0103c8000034\r
+:0103c9000033\r
+:0103ca000032\r
+:0103cb000031\r
+:0103cc000030\r
+:0103cd00002f\r
+:0103ce00002e\r
+:0103cf00002d\r
+:0103d000002c\r
+:0103d100002b\r
+:0103d200002a\r
+:0103d3000029\r
+:0103d4000028\r
+:0103d5000027\r
+:0103d6000026\r
+:0103d7000025\r
+:0103d8000024\r
+:0103d9000023\r
+:0103da000022\r
+:0103db000021\r
+:0103dc000020\r
+:0103dd00001f\r
+:0103de00001e\r
+:0103df00001d\r
+:0103e000001c\r
+:0103e100001b\r
+:0103e200001a\r
+:0103e3000019\r
+:0103e4000018\r
+:0103e5000017\r
+:0103e6000016\r
+:0103e7000015\r
+:0103e8000014\r
+:0103e9000013\r
+:0103ea000012\r
+:0103eb000011\r
+:0103ec000010\r
+:0103ed00000f\r
+:0103ee00000e\r
+:0103ef00000d\r
+:0103f000000c\r
+:0103f100000b\r
+:0103f200000a\r
+:0103f3000009\r
+:0103f4000008\r
+:0103f5000007\r
+:0103f6000006\r
+:0103f7000005\r
+:0103f8000004\r
+:0103f9000003\r
+:0103fa000002\r
+:0103fb000001\r
+:0103fc000000\r
+:0103fd0000ff\r
+:0103fe0000fe\r
+:0103ff00906d\r
+:0104000003f8\r
+:0104010000fa\r
+:0104020000f9\r
+:0104030000f8\r
+:0104040000f7\r
+:0104050000f6\r
+:0104060000f5\r
+:0104070000f4\r
+:0104080000f3\r
+:0104090000f2\r
+:01040a0000f1\r
+:01040b0000f0\r
+:01040c0000ef\r
+:01040d0000ee\r
+:01040e0000ed\r
+:01040f0000ec\r
+:0104100000eb\r
+:0104110000ea\r
+:0104120000e9\r
+:0104130000e8\r
+:0104140000e7\r
+:0104150000e6\r
+:0104160000e5\r
+:0104170000e4\r
+:0104180000e3\r
+:0104190000e2\r
+:01041a0000e1\r
+:01041b0000e0\r
+:01041c0000df\r
+:01041d0000de\r
+:01041e0000dd\r
+:01041f0000dc\r
+:0104200000db\r
+:0104210000da\r
+:0104220000d9\r
+:0104230000d8\r
+:0104240000d7\r
+:0104250000d6\r
+:0104260000d5\r
+:0104270000d4\r
+:0104280000d3\r
+:0104290000d2\r
+:01042a0000d1\r
+:01042b0000d0\r
+:01042c0000cf\r
+:01042d0000ce\r
+:01042e0000cd\r
+:01042f0000cc\r
+:0104300000cb\r
+:0104310000ca\r
+:0104320000c9\r
+:0104330000c8\r
+:0104340000c7\r
+:0104350000c6\r
+:0104360000c5\r
+:0104370000c4\r
+:0104380000c3\r
+:0104390000c2\r
+:01043a0000c1\r
+:01043b0000c0\r
+:01043c0000bf\r
+:01043d0000be\r
+:01043e0000bd\r
+:01043f00902c\r
+:0104400003b8\r
+:0104410000ba\r
+:0104420000b9\r
+:0104430000b8\r
+:0104440000b7\r
+:0104450000b6\r
+:0104460000b5\r
+:0104470000b4\r
+:0104480000b3\r
+:0104490000b2\r
+:01044a0000b1\r
+:01044b0000b0\r
+:01044c0000af\r
+:01044d0000ae\r
+:01044e0000ad\r
+:01044f0000ac\r
+:0104500000ab\r
+:0104510000aa\r
+:0104520000a9\r
+:0104530000a8\r
+:0104540000a7\r
+:0104550000a6\r
+:0104560000a5\r
+:0104570000a4\r
+:0104580000a3\r
+:0104590000a2\r
+:01045a0000a1\r
+:01045b0000a0\r
+:01045c00009f\r
+:01045d00009e\r
+:01045e00009d\r
+:01045f00009c\r
+:01046000009b\r
+:01046100009a\r
+:010462000099\r
+:010463000098\r
+:010464000097\r
+:010465000096\r
+:010466000095\r
+:010467000094\r
+:010468000093\r
+:010469000092\r
+:01046a000091\r
+:01046b000090\r
+:01046c00008f\r
+:01046d00008e\r
+:01046e00008d\r
+:01046f00008c\r
+:01047000008b\r
+:01047100008a\r
+:010472000089\r
+:010473000088\r
+:010474000087\r
+:010475000086\r
+:010476000085\r
+:010477000084\r
+:010478000083\r
+:010479000082\r
+:01047a000081\r
+:01047b000080\r
+:01047c00007f\r
+:01047d00007e\r
+:01047e00007d\r
+:01047f0090ec\r
+:010480000378\r
+:01048100007a\r
+:010482000079\r
+:010483000078\r
+:010484000077\r
+:010485000076\r
+:010486000075\r
+:010487000074\r
+:010488000073\r
+:010489000072\r
+:01048a000071\r
+:01048b000070\r
+:01048c00006f\r
+:01048d00006e\r
+:01048e00006d\r
+:01048f00006c\r
+:01049000006b\r
+:01049100006a\r
+:010492000069\r
+:010493000068\r
+:010494000067\r
+:010495000066\r
+:010496000065\r
+:010497000064\r
+:010498000063\r
+:010499000062\r
+:01049a000061\r
+:01049b000060\r
+:01049c00005f\r
+:01049d00005e\r
+:01049e00005d\r
+:01049f00005c\r
+:0104a000005b\r
+:0104a100005a\r
+:0104a2000059\r
+:0104a3000058\r
+:0104a4000057\r
+:0104a5000056\r
+:0104a6000055\r
+:0104a7000054\r
+:0104a8000053\r
+:0104a9000052\r
+:0104aa000051\r
+:0104ab000050\r
+:0104ac00004f\r
+:0104ad00004e\r
+:0104ae00004d\r
+:0104af00004c\r
+:0104b000004b\r
+:0104b100004a\r
+:0104b2000049\r
+:0104b3000048\r
+:0104b4000047\r
+:0104b5000046\r
+:0104b6000045\r
+:0104b7000044\r
+:0104b8000043\r
+:0104b9000042\r
+:0104ba000041\r
+:0104bb000040\r
+:0104bc00003f\r
+:0104bd00003e\r
+:0104be00003d\r
+:0104bf0090ac\r
+:0104c0000338\r
+:0104c100003a\r
+:0104c2000039\r
+:0104c3000038\r
+:0104c4000037\r
+:0104c5000036\r
+:0104c6000035\r
+:0104c7000034\r
+:0104c8000033\r
+:0104c9000032\r
+:0104ca000031\r
+:0104cb000030\r
+:0104cc00002f\r
+:0104cd00002e\r
+:0104ce00002d\r
+:0104cf00002c\r
+:0104d000002b\r
+:0104d100002a\r
+:0104d2000029\r
+:0104d3000028\r
+:0104d4000027\r
+:0104d5000026\r
+:0104d6000025\r
+:0104d7000024\r
+:0104d8000023\r
+:0104d9000022\r
+:0104da000021\r
+:0104db000020\r
+:0104dc00001f\r
+:0104dd00001e\r
+:0104de00001d\r
+:0104df00001c\r
+:0104e000001b\r
+:0104e100001a\r
+:0104e2000019\r
+:0104e3000018\r
+:0104e4000017\r
+:0104e5000016\r
+:0104e6000015\r
+:0104e7000014\r
+:0104e8000013\r
+:0104e9000012\r
+:0104ea000011\r
+:0104eb000010\r
+:0104ec00000f\r
+:0104ed00000e\r
+:0104ee00000d\r
+:0104ef00000c\r
+:0104f000000b\r
+:0104f100000a\r
+:0104f2000009\r
+:0104f3000008\r
+:0104f4000007\r
+:0104f5000006\r
+:0104f6000005\r
+:0104f7000004\r
+:0104f8000003\r
+:0104f9000002\r
+:0104fa000001\r
+:0104fb000000\r
+:0104fc0000ff\r
+:0104fd0000fe\r
+:0104fe0000fd\r
+:0104ff00906c\r
+:0105000003f7\r
+:0105010000f9\r
+:0105020000f8\r
+:0105030000f7\r
+:0105040000f6\r
+:0105050000f5\r
+:0105060000f4\r
+:0105070000f3\r
+:0105080000f2\r
+:0105090000f1\r
+:01050a0000f0\r
+:01050b0000ef\r
+:01050c0000ee\r
+:01050d0000ed\r
+:01050e0000ec\r
+:01050f0000eb\r
+:0105100000ea\r
+:0105110000e9\r
+:0105120000e8\r
+:0105130000e7\r
+:0105140000e6\r
+:0105150000e5\r
+:0105160000e4\r
+:0105170000e3\r
+:0105180000e2\r
+:0105190000e1\r
+:01051a0000e0\r
+:01051b0000df\r
+:01051c0000de\r
+:01051d0000dd\r
+:01051e0000dc\r
+:01051f0000db\r
+:0105200000da\r
+:0105210000d9\r
+:0105220000d8\r
+:0105230000d7\r
+:0105240000d6\r
+:0105250000d5\r
+:0105260000d4\r
+:0105270000d3\r
+:0105280000d2\r
+:0105290000d1\r
+:01052a0000d0\r
+:01052b0000cf\r
+:01052c0000ce\r
+:01052d0000cd\r
+:01052e0000cc\r
+:01052f0000cb\r
+:0105300000ca\r
+:0105310000c9\r
+:0105320000c8\r
+:0105330000c7\r
+:0105340000c6\r
+:0105350000c5\r
+:0105360000c4\r
+:0105370000c3\r
+:0105380000c2\r
+:0105390000c1\r
+:01053a0000c0\r
+:01053b0000bf\r
+:01053c0000be\r
+:01053d0000bd\r
+:01053e0000bc\r
+:01053f00902b\r
+:0105400003b7\r
+:0105410000b9\r
+:0105420000b8\r
+:0105430000b7\r
+:0105440000b6\r
+:0105450000b5\r
+:0105460000b4\r
+:0105470000b3\r
+:0105480000b2\r
+:0105490000b1\r
+:01054a0000b0\r
+:01054b0000af\r
+:01054c0000ae\r
+:01054d0000ad\r
+:01054e0000ac\r
+:01054f0000ab\r
+:0105500000aa\r
+:0105510000a9\r
+:0105520000a8\r
+:0105530000a7\r
+:0105540000a6\r
+:0105550000a5\r
+:0105560000a4\r
+:0105570000a3\r
+:0105580000a2\r
+:0105590000a1\r
+:01055a0000a0\r
+:01055b00009f\r
+:01055c00009e\r
+:01055d00009d\r
+:01055e00009c\r
+:01055f00009b\r
+:01056000009a\r
+:010561000099\r
+:010562000098\r
+:010563000097\r
+:010564000096\r
+:010565000095\r
+:010566000094\r
+:010567000093\r
+:010568000092\r
+:010569000091\r
+:01056a000090\r
+:01056b00008f\r
+:01056c00008e\r
+:01056d00008d\r
+:01056e00008c\r
+:01056f00008b\r
+:01057000008a\r
+:010571000089\r
+:010572000088\r
+:010573000087\r
+:010574000086\r
+:010575000085\r
+:010576000084\r
+:010577000083\r
+:010578000082\r
+:010579000081\r
+:01057a000080\r
+:01057b00007f\r
+:01057c00007e\r
+:01057d00007d\r
+:01057e00007c\r
+:01057f0090eb\r
+:010580000377\r
+:010581000079\r
+:010582000078\r
+:010583000077\r
+:010584000076\r
+:010585000075\r
+:010586000074\r
+:010587000073\r
+:010588000072\r
+:010589000071\r
+:01058a000070\r
+:01058b00006f\r
+:01058c00006e\r
+:01058d00006d\r
+:01058e00006c\r
+:01058f00006b\r
+:01059000006a\r
+:010591000069\r
+:010592000068\r
+:010593000067\r
+:010594000066\r
+:010595000065\r
+:010596000064\r
+:010597000063\r
+:010598000062\r
+:010599000061\r
+:01059a000060\r
+:01059b00005f\r
+:01059c00005e\r
+:01059d00005d\r
+:01059e00005c\r
+:01059f00005b\r
+:0105a000005a\r
+:0105a1000059\r
+:0105a2000058\r
+:0105a3000057\r
+:0105a4000056\r
+:0105a5000055\r
+:0105a6000054\r
+:0105a7000053\r
+:0105a8000052\r
+:0105a9000051\r
+:0105aa000050\r
+:0105ab00004f\r
+:0105ac00004e\r
+:0105ad00004d\r
+:0105ae00004c\r
+:0105af00004b\r
+:0105b000004a\r
+:0105b1000049\r
+:0105b2000048\r
+:0105b3000047\r
+:0105b4000046\r
+:0105b5000045\r
+:0105b6000044\r
+:0105b7000043\r
+:0105b8000042\r
+:0105b9000041\r
+:0105ba000040\r
+:0105bb00003f\r
+:0105bc00003e\r
+:0105bd00003d\r
+:0105be00003c\r
+:0105bf0090ab\r
+:0105c0000337\r
+:0105c1000039\r
+:0105c2000038\r
+:0105c3000037\r
+:0105c4000036\r
+:0105c5000035\r
+:0105c6000034\r
+:0105c7000033\r
+:0105c8000032\r
+:0105c9000031\r
+:0105ca000030\r
+:0105cb00002f\r
+:0105cc00002e\r
+:0105cd00002d\r
+:0105ce00002c\r
+:0105cf00002b\r
+:0105d000002a\r
+:0105d1000029\r
+:0105d2000028\r
+:0105d3000027\r
+:0105d4000026\r
+:0105d5000025\r
+:0105d6000024\r
+:0105d7000023\r
+:0105d8000022\r
+:0105d9000021\r
+:0105da000020\r
+:0105db00001f\r
+:0105dc00001e\r
+:0105dd00001d\r
+:0105de00001c\r
+:0105df00001b\r
+:0105e000001a\r
+:0105e1000019\r
+:0105e2000018\r
+:0105e3000017\r
+:0105e4000016\r
+:0105e5000015\r
+:0105e6000014\r
+:0105e7000013\r
+:0105e8000012\r
+:0105e9000011\r
+:0105ea000010\r
+:0105eb00000f\r
+:0105ec00000e\r
+:0105ed00000d\r
+:0105ee00000c\r
+:0105ef00000b\r
+:0105f000000a\r
+:0105f1000009\r
+:0105f2000008\r
+:0105f3000007\r
+:0105f4000006\r
+:0105f5000005\r
+:0105f6000004\r
+:0105f7000003\r
+:0105f8000002\r
+:0105f9000001\r
+:0105fa000000\r
+:0105fb0000ff\r
+:0105fc0000fe\r
+:0105fd0000fd\r
+:0105fe0000fc\r
+:0105ff00906b\r
+:0106000003f6\r
+:0106010000f8\r
+:0106020000f7\r
+:0106030000f6\r
+:0106040000f5\r
+:0106050000f4\r
+:0106060000f3\r
+:0106070000f2\r
+:0106080000f1\r
+:0106090000f0\r
+:01060a0000ef\r
+:01060b0000ee\r
+:01060c0000ed\r
+:01060d0000ec\r
+:01060e0000eb\r
+:01060f0000ea\r
+:0106100000e9\r
+:0106110000e8\r
+:0106120000e7\r
+:0106130000e6\r
+:0106140000e5\r
+:0106150000e4\r
+:0106160000e3\r
+:0106170000e2\r
+:0106180000e1\r
+:0106190000e0\r
+:01061a0000df\r
+:01061b0000de\r
+:01061c0000dd\r
+:01061d0000dc\r
+:01061e0000db\r
+:01061f0000da\r
+:0106200000d9\r
+:0106210000d8\r
+:0106220000d7\r
+:0106230000d6\r
+:0106240000d5\r
+:0106250000d4\r
+:0106260000d3\r
+:0106270000d2\r
+:0106280000d1\r
+:0106290000d0\r
+:01062a0000cf\r
+:01062b0000ce\r
+:01062c0000cd\r
+:01062d0000cc\r
+:01062e0000cb\r
+:01062f0000ca\r
+:0106300000c9\r
+:0106310000c8\r
+:0106320000c7\r
+:0106330000c6\r
+:0106340000c5\r
+:0106350000c4\r
+:0106360000c3\r
+:0106370000c2\r
+:0106380000c1\r
+:0106390000c0\r
+:01063a0000bf\r
+:01063b0000be\r
+:01063c0000bd\r
+:01063d0000bc\r
+:01063e0000bb\r
+:01063f00902a\r
+:0106400003b6\r
+:0106410000b8\r
+:0106420000b7\r
+:0106430000b6\r
+:0106440000b5\r
+:0106450000b4\r
+:0106460000b3\r
+:0106470000b2\r
+:0106480000b1\r
+:0106490000b0\r
+:01064a0000af\r
+:01064b0000ae\r
+:01064c0000ad\r
+:01064d0000ac\r
+:01064e0000ab\r
+:01064f0000aa\r
+:0106500000a9\r
+:0106510000a8\r
+:0106520000a7\r
+:0106530000a6\r
+:0106540000a5\r
+:0106550000a4\r
+:0106560000a3\r
+:0106570000a2\r
+:0106580000a1\r
+:0106590000a0\r
+:01065a00009f\r
+:01065b00009e\r
+:01065c00009d\r
+:01065d00009c\r
+:01065e00009b\r
+:01065f00009a\r
+:010660000099\r
+:010661000098\r
+:010662000097\r
+:010663000096\r
+:010664000095\r
+:010665000094\r
+:010666000093\r
+:010667000092\r
+:010668000091\r
+:010669000090\r
+:01066a00008f\r
+:01066b00008e\r
+:01066c00008d\r
+:01066d00008c\r
+:01066e00008b\r
+:01066f00008a\r
+:010670000089\r
+:010671000088\r
+:010672000087\r
+:010673000086\r
+:010674000085\r
+:010675000084\r
+:010676000083\r
+:010677000082\r
+:010678000081\r
+:010679000080\r
+:01067a00007f\r
+:01067b00007e\r
+:01067c00007d\r
+:01067d00007c\r
+:01067e00007b\r
+:01067f0090ea\r
+:010680000376\r
+:010681000078\r
+:010682000077\r
+:010683000076\r
+:010684000075\r
+:010685000074\r
+:010686000073\r
+:010687000072\r
+:010688000071\r
+:010689000070\r
+:01068a00006f\r
+:01068b00006e\r
+:01068c00006d\r
+:01068d00006c\r
+:01068e00006b\r
+:01068f00006a\r
+:010690000069\r
+:010691000068\r
+:010692000067\r
+:010693000066\r
+:010694000065\r
+:010695000064\r
+:010696000063\r
+:010697000062\r
+:010698000061\r
+:010699000060\r
+:01069a00005f\r
+:01069b00005e\r
+:01069c00005d\r
+:01069d00005c\r
+:01069e00005b\r
+:01069f00005a\r
+:0106a0000059\r
+:0106a1000058\r
+:0106a2000057\r
+:0106a3000056\r
+:0106a4000055\r
+:0106a5000054\r
+:0106a6000053\r
+:0106a7000052\r
+:0106a8000051\r
+:0106a9000050\r
+:0106aa00004f\r
+:0106ab00004e\r
+:0106ac00004d\r
+:0106ad00004c\r
+:0106ae00004b\r
+:0106af00004a\r
+:0106b0000049\r
+:0106b1000048\r
+:0106b2000047\r
+:0106b3000046\r
+:0106b4000045\r
+:0106b5000044\r
+:0106b6000043\r
+:0106b7000042\r
+:0106b8000041\r
+:0106b9000040\r
+:0106ba00003f\r
+:0106bb00003e\r
+:0106bc00003d\r
+:0106bd00003c\r
+:0106be00003b\r
+:0106bf0090aa\r
+:0106c0000336\r
+:0106c1000038\r
+:0106c2000037\r
+:0106c3000036\r
+:0106c4000035\r
+:0106c5000034\r
+:0106c6000033\r
+:0106c7000032\r
+:0106c8000031\r
+:0106c9000030\r
+:0106ca00002f\r
+:0106cb00002e\r
+:0106cc00002d\r
+:0106cd00002c\r
+:0106ce00002b\r
+:0106cf00002a\r
+:0106d0000029\r
+:0106d1000028\r
+:0106d2000027\r
+:0106d3000026\r
+:0106d4000025\r
+:0106d5000024\r
+:0106d6000023\r
+:0106d7000022\r
+:0106d8000021\r
+:0106d9000020\r
+:0106da00001f\r
+:0106db00001e\r
+:0106dc00001d\r
+:0106dd00001c\r
+:0106de00001b\r
+:0106df00001a\r
+:0106e0000019\r
+:0106e1000018\r
+:0106e2000017\r
+:0106e3000016\r
+:0106e4000015\r
+:0106e5000014\r
+:0106e6000013\r
+:0106e7000012\r
+:0106e8000011\r
+:0106e9000010\r
+:0106ea00000f\r
+:0106eb00000e\r
+:0106ec00000d\r
+:0106ed00000c\r
+:0106ee00000b\r
+:0106ef00000a\r
+:0106f0000009\r
+:0106f1000008\r
+:0106f2000007\r
+:0106f3000006\r
+:0106f4000005\r
+:0106f5000004\r
+:0106f6000003\r
+:0106f7000002\r
+:0106f8000001\r
+:0106f9000000\r
+:0106fa0000ff\r
+:0106fb0000fe\r
+:0106fc0000fd\r
+:0106fd0000fc\r
+:0106fe0000fb\r
+:0106ff00906a\r
+:0107000003f5\r
+:0107010000f7\r
+:0107020000f6\r
+:0107030000f5\r
+:0107040000f4\r
+:0107050000f3\r
+:0107060000f2\r
+:0107070000f1\r
+:0107080000f0\r
+:0107090000ef\r
+:01070a0000ee\r
+:01070b0000ed\r
+:01070c0000ec\r
+:01070d0000eb\r
+:01070e0000ea\r
+:01070f0000e9\r
+:0107100000e8\r
+:0107110000e7\r
+:0107120000e6\r
+:0107130000e5\r
+:0107140000e4\r
+:0107150000e3\r
+:0107160000e2\r
+:0107170000e1\r
+:0107180000e0\r
+:0107190000df\r
+:01071a0000de\r
+:01071b0000dd\r
+:01071c0000dc\r
+:01071d0000db\r
+:01071e0000da\r
+:01071f0000d9\r
+:0107200000d8\r
+:0107210000d7\r
+:0107220000d6\r
+:0107230000d5\r
+:0107240000d4\r
+:0107250000d3\r
+:0107260000d2\r
+:0107270000d1\r
+:0107280000d0\r
+:0107290000cf\r
+:01072a0000ce\r
+:01072b0000cd\r
+:01072c0000cc\r
+:01072d0000cb\r
+:01072e0000ca\r
+:01072f0000c9\r
+:0107300000c8\r
+:0107310000c7\r
+:0107320000c6\r
+:0107330000c5\r
+:0107340000c4\r
+:0107350000c3\r
+:0107360000c2\r
+:0107370000c1\r
+:0107380000c0\r
+:0107390000bf\r
+:01073a0000be\r
+:01073b0000bd\r
+:01073c0000bc\r
+:01073d0000bb\r
+:01073e0000ba\r
+:01073f009029\r
+:0107400003b5\r
+:0107410000b7\r
+:0107420000b6\r
+:0107430000b5\r
+:0107440000b4\r
+:0107450000b3\r
+:0107460000b2\r
+:0107470000b1\r
+:0107480000b0\r
+:0107490000af\r
+:01074a0000ae\r
+:01074b0000ad\r
+:01074c0000ac\r
+:01074d0000ab\r
+:01074e0000aa\r
+:01074f0000a9\r
+:0107500000a8\r
+:0107510000a7\r
+:0107520000a6\r
+:0107530000a5\r
+:0107540000a4\r
+:0107550000a3\r
+:0107560000a2\r
+:0107570000a1\r
+:0107580000a0\r
+:01075900009f\r
+:01075a00009e\r
+:01075b00009d\r
+:01075c00009c\r
+:01075d00009b\r
+:01075e00009a\r
+:01075f000099\r
+:010760000098\r
+:010761000097\r
+:010762000096\r
+:010763000095\r
+:010764000094\r
+:010765000093\r
+:010766000092\r
+:010767000091\r
+:010768000090\r
+:01076900008f\r
+:01076a00008e\r
+:01076b00008d\r
+:01076c00008c\r
+:01076d00008b\r
+:01076e00008a\r
+:01076f000089\r
+:010770000088\r
+:010771000087\r
+:010772000086\r
+:010773000085\r
+:010774000084\r
+:010775000083\r
+:010776000082\r
+:010777000081\r
+:010778000080\r
+:01077900007f\r
+:01077a00007e\r
+:01077b00007d\r
+:01077c00007c\r
+:01077d00007b\r
+:01077e00007a\r
+:01077f0090e9\r
+:010780000375\r
+:010781000077\r
+:010782000076\r
+:010783000075\r
+:010784000074\r
+:010785000073\r
+:010786000072\r
+:010787000071\r
+:010788000070\r
+:01078900006f\r
+:01078a00006e\r
+:01078b00006d\r
+:01078c00006c\r
+:01078d00006b\r
+:01078e00006a\r
+:01078f000069\r
+:010790000068\r
+:010791000067\r
+:010792000066\r
+:010793000065\r
+:010794000064\r
+:010795000063\r
+:010796000062\r
+:010797000061\r
+:010798000060\r
+:01079900005f\r
+:01079a00005e\r
+:01079b00005d\r
+:01079c00005c\r
+:01079d00005b\r
+:01079e00005a\r
+:01079f000059\r
+:0107a0000058\r
+:0107a1000057\r
+:0107a2000056\r
+:0107a3000055\r
+:0107a4000054\r
+:0107a5000053\r
+:0107a6000052\r
+:0107a7000051\r
+:0107a8000050\r
+:0107a900004f\r
+:0107aa00004e\r
+:0107ab00004d\r
+:0107ac00004c\r
+:0107ad00004b\r
+:0107ae00004a\r
+:0107af000049\r
+:0107b0000048\r
+:0107b1000047\r
+:0107b2000046\r
+:0107b3000045\r
+:0107b4000044\r
+:0107b5000043\r
+:0107b6000042\r
+:0107b7000041\r
+:0107b8000040\r
+:0107b900003f\r
+:0107ba00003e\r
+:0107bb00003d\r
+:0107bc00003c\r
+:0107bd00003b\r
+:0107be00003a\r
+:0107bf0090a9\r
+:0107c0000335\r
+:0107c1000037\r
+:0107c2000036\r
+:0107c3000035\r
+:0107c4000034\r
+:0107c5000033\r
+:0107c6000032\r
+:0107c7000031\r
+:0107c8000030\r
+:0107c900002f\r
+:0107ca00002e\r
+:0107cb00002d\r
+:0107cc00002c\r
+:0107cd00002b\r
+:0107ce00002a\r
+:0107cf000029\r
+:0107d0000028\r
+:0107d1000027\r
+:0107d2000026\r
+:0107d3000025\r
+:0107d4000024\r
+:0107d5000023\r
+:0107d6000022\r
+:0107d7000021\r
+:0107d8000020\r
+:0107d900001f\r
+:0107da00001e\r
+:0107db00001d\r
+:0107dc00001c\r
+:0107dd00001b\r
+:0107de00001a\r
+:0107df000019\r
+:0107e0000018\r
+:0107e1000017\r
+:0107e2000016\r
+:0107e3000015\r
+:0107e4000014\r
+:0107e5000013\r
+:0107e6000012\r
+:0107e7000011\r
+:0107e8000010\r
+:0107e900000f\r
+:0107ea00000e\r
+:0107eb00000d\r
+:0107ec00000c\r
+:0107ed00000b\r
+:0107ee00000a\r
+:0107ef000009\r
+:0107f0000008\r
+:0107f1000007\r
+:0107f2000006\r
+:0107f3000005\r
+:0107f4000004\r
+:0107f5000003\r
+:0107f6000002\r
+:0107f7000001\r
+:0107f8000000\r
+:0107f90000ff\r
+:0107fa0000fe\r
+:0107fb0000fd\r
+:0107fc0000fc\r
+:0107fd0000fb\r
+:0107fe0000fa\r
+:0107ff009069\r
+:0108000003f4\r
+:0108010000f6\r
+:0108020000f5\r
+:0108030000f4\r
+:0108040000f3\r
+:0108050000f2\r
+:0108060000f1\r
+:0108070000f0\r
+:0108080000ef\r
+:0108090000ee\r
+:01080a0000ed\r
+:01080b0000ec\r
+:01080c0000eb\r
+:01080d0000ea\r
+:01080e0000e9\r
+:01080f0000e8\r
+:0108100000e7\r
+:0108110000e6\r
+:0108120000e5\r
+:0108130000e4\r
+:0108140000e3\r
+:0108150000e2\r
+:0108160000e1\r
+:0108170000e0\r
+:0108180000df\r
+:0108190000de\r
+:01081a0000dd\r
+:01081b0000dc\r
+:01081c0000db\r
+:01081d0000da\r
+:01081e0000d9\r
+:01081f0000d8\r
+:0108200000d7\r
+:0108210000d6\r
+:0108220000d5\r
+:0108230000d4\r
+:0108240000d3\r
+:0108250000d2\r
+:0108260000d1\r
+:0108270000d0\r
+:0108280000cf\r
+:0108290000ce\r
+:01082a0000cd\r
+:01082b0000cc\r
+:01082c0000cb\r
+:01082d0000ca\r
+:01082e0000c9\r
+:01082f0000c8\r
+:0108300000c7\r
+:0108310000c6\r
+:0108320000c5\r
+:0108330000c4\r
+:0108340000c3\r
+:0108350000c2\r
+:0108360000c1\r
+:0108370000c0\r
+:0108380000bf\r
+:0108390000be\r
+:01083a0000bd\r
+:01083b0000bc\r
+:01083c0000bb\r
+:01083d0000ba\r
+:01083e0000b9\r
+:01083f009028\r
+:0108400003b4\r
+:0108410000b6\r
+:0108420000b5\r
+:0108430000b4\r
+:0108440000b3\r
+:0108450000b2\r
+:0108460000b1\r
+:0108470000b0\r
+:0108480000af\r
+:0108490000ae\r
+:01084a0000ad\r
+:01084b0000ac\r
+:01084c0000ab\r
+:01084d0000aa\r
+:01084e0000a9\r
+:01084f0000a8\r
+:0108500000a7\r
+:0108510000a6\r
+:0108520000a5\r
+:0108530000a4\r
+:0108540000a3\r
+:0108550000a2\r
+:0108560000a1\r
+:0108570000a0\r
+:01085800009f\r
+:01085900009e\r
+:01085a00009d\r
+:01085b00009c\r
+:01085c00009b\r
+:01085d00009a\r
+:01085e000099\r
+:01085f000098\r
+:010860000097\r
+:010861000096\r
+:010862000095\r
+:010863000094\r
+:010864000093\r
+:010865000092\r
+:010866000091\r
+:010867000090\r
+:01086800008f\r
+:01086900008e\r
+:01086a00008d\r
+:01086b00008c\r
+:01086c00008b\r
+:01086d00008a\r
+:01086e000089\r
+:01086f000088\r
+:010870000087\r
+:010871000086\r
+:010872000085\r
+:010873000084\r
+:010874000083\r
+:010875000082\r
+:010876000081\r
+:010877000080\r
+:01087800007f\r
+:01087900007e\r
+:01087a00007d\r
+:01087b00007c\r
+:01087c00007b\r
+:01087d00007a\r
+:01087e000079\r
+:01087f0090e8\r
+:010880000374\r
+:010881000076\r
+:010882000075\r
+:010883000074\r
+:010884000073\r
+:010885000072\r
+:010886000071\r
+:010887000070\r
+:01088800006f\r
+:01088900006e\r
+:01088a00006d\r
+:01088b00006c\r
+:01088c00006b\r
+:01088d00006a\r
+:01088e000069\r
+:01088f000068\r
+:010890000067\r
+:010891000066\r
+:010892000065\r
+:010893000064\r
+:010894000063\r
+:010895000062\r
+:010896000061\r
+:010897000060\r
+:01089800005f\r
+:01089900005e\r
+:01089a00005d\r
+:01089b00005c\r
+:01089c00005b\r
+:01089d00005a\r
+:01089e000059\r
+:01089f000058\r
+:0108a0000057\r
+:0108a1000056\r
+:0108a2000055\r
+:0108a3000054\r
+:0108a4000053\r
+:0108a5000052\r
+:0108a6000051\r
+:0108a7000050\r
+:0108a800004f\r
+:0108a900004e\r
+:0108aa00004d\r
+:0108ab00004c\r
+:0108ac00004b\r
+:0108ad00004a\r
+:0108ae000049\r
+:0108af000048\r
+:0108b0000047\r
+:0108b1000046\r
+:0108b2000045\r
+:0108b3000044\r
+:0108b4000043\r
+:0108b5000042\r
+:0108b6000041\r
+:0108b7000040\r
+:0108b800003f\r
+:0108b900003e\r
+:0108ba00003d\r
+:0108bb00003c\r
+:0108bc00003b\r
+:0108bd00003a\r
+:0108be000039\r
+:0108bf0090a8\r
+:0108c0000334\r
+:0108c1000036\r
+:0108c2000035\r
+:0108c3000034\r
+:0108c4000033\r
+:0108c5000032\r
+:0108c6000031\r
+:0108c7000030\r
+:0108c800002f\r
+:0108c900002e\r
+:0108ca00002d\r
+:0108cb00002c\r
+:0108cc00002b\r
+:0108cd00002a\r
+:0108ce000029\r
+:0108cf000028\r
+:0108d0000027\r
+:0108d1000026\r
+:0108d2000025\r
+:0108d3000024\r
+:0108d4000023\r
+:0108d5000022\r
+:0108d6000021\r
+:0108d7000020\r
+:0108d800001f\r
+:0108d900001e\r
+:0108da00001d\r
+:0108db00001c\r
+:0108dc00001b\r
+:0108dd00001a\r
+:0108de000019\r
+:0108df000018\r
+:0108e0000017\r
+:0108e1000016\r
+:0108e2000015\r
+:0108e3000014\r
+:0108e4000013\r
+:0108e5000012\r
+:0108e6000011\r
+:0108e7000010\r
+:0108e800000f\r
+:0108e900000e\r
+:0108ea00000d\r
+:0108eb00000c\r
+:0108ec00000b\r
+:0108ed00000a\r
+:0108ee000009\r
+:0108ef000008\r
+:0108f0000007\r
+:0108f1000006\r
+:0108f2000005\r
+:0108f3000004\r
+:0108f4000003\r
+:0108f5000002\r
+:0108f6000001\r
+:0108f7000000\r
+:0108f80000ff\r
+:0108f90000fe\r
+:0108fa0000fd\r
+:0108fb0000fc\r
+:0108fc0000fb\r
+:0108fd0000fa\r
+:0108fe0000f9\r
+:0108ff009068\r
+:0109000003f3\r
+:0109010000f5\r
+:0109020000f4\r
+:0109030000f3\r
+:0109040000f2\r
+:0109050000f1\r
+:0109060000f0\r
+:0109070000ef\r
+:0109080000ee\r
+:0109090000ed\r
+:01090a0000ec\r
+:01090b0000eb\r
+:01090c0000ea\r
+:01090d0000e9\r
+:01090e0000e8\r
+:01090f0000e7\r
+:0109100000e6\r
+:0109110000e5\r
+:0109120000e4\r
+:0109130000e3\r
+:0109140000e2\r
+:0109150000e1\r
+:0109160000e0\r
+:0109170000df\r
+:0109180000de\r
+:0109190000dd\r
+:01091a0000dc\r
+:01091b0000db\r
+:01091c0000da\r
+:01091d0000d9\r
+:01091e0000d8\r
+:01091f0000d7\r
+:0109200000d6\r
+:0109210000d5\r
+:0109220000d4\r
+:0109230000d3\r
+:0109240000d2\r
+:0109250000d1\r
+:0109260000d0\r
+:0109270000cf\r
+:0109280000ce\r
+:0109290000cd\r
+:01092a0000cc\r
+:01092b0000cb\r
+:01092c0000ca\r
+:01092d0000c9\r
+:01092e0000c8\r
+:01092f0000c7\r
+:0109300000c6\r
+:0109310000c5\r
+:0109320000c4\r
+:0109330000c3\r
+:0109340000c2\r
+:0109350000c1\r
+:0109360000c0\r
+:0109370000bf\r
+:0109380000be\r
+:0109390000bd\r
+:01093a0000bc\r
+:01093b0000bb\r
+:01093c0000ba\r
+:01093d0000b9\r
+:01093e0000b8\r
+:01093f009027\r
+:0109400003b3\r
+:0109410000b5\r
+:0109420000b4\r
+:0109430000b3\r
+:0109440000b2\r
+:0109450000b1\r
+:0109460000b0\r
+:0109470000af\r
+:0109480000ae\r
+:0109490000ad\r
+:01094a0000ac\r
+:01094b0000ab\r
+:01094c0000aa\r
+:01094d0000a9\r
+:01094e0000a8\r
+:01094f0000a7\r
+:0109500000a6\r
+:0109510000a5\r
+:0109520000a4\r
+:0109530000a3\r
+:0109540000a2\r
+:0109550000a1\r
+:0109560000a0\r
+:01095700009f\r
+:01095800009e\r
+:01095900009d\r
+:01095a00009c\r
+:01095b00009b\r
+:01095c00009a\r
+:01095d000099\r
+:01095e000098\r
+:01095f000097\r
+:010960000096\r
+:010961000095\r
+:010962000094\r
+:010963000093\r
+:010964000092\r
+:010965000091\r
+:010966000090\r
+:01096700008f\r
+:01096800008e\r
+:01096900008d\r
+:01096a00008c\r
+:01096b00008b\r
+:01096c00008a\r
+:01096d000089\r
+:01096e000088\r
+:01096f000087\r
+:010970000086\r
+:010971000085\r
+:010972000084\r
+:010973000083\r
+:010974000082\r
+:010975000081\r
+:010976000080\r
+:01097700007f\r
+:01097800007e\r
+:01097900007d\r
+:01097a00007c\r
+:01097b00007b\r
+:01097c00007a\r
+:01097d000079\r
+:01097e000078\r
+:01097f0090e7\r
+:010980000373\r
+:010981000075\r
+:010982000074\r
+:010983000073\r
+:010984000072\r
+:010985000071\r
+:010986000070\r
+:01098700006f\r
+:01098800006e\r
+:01098900006d\r
+:01098a00006c\r
+:01098b00006b\r
+:01098c00006a\r
+:01098d000069\r
+:01098e000068\r
+:01098f000067\r
+:010990000066\r
+:010991000065\r
+:010992000064\r
+:010993000063\r
+:010994000062\r
+:010995000061\r
+:010996000060\r
+:01099700005f\r
+:01099800005e\r
+:01099900005d\r
+:01099a00005c\r
+:01099b00005b\r
+:01099c00005a\r
+:01099d000059\r
+:01099e000058\r
+:01099f000057\r
+:0109a0000056\r
+:0109a1000055\r
+:0109a2000054\r
+:0109a3000053\r
+:0109a4000052\r
+:0109a5000051\r
+:0109a6000050\r
+:0109a700004f\r
+:0109a800004e\r
+:0109a900004d\r
+:0109aa00004c\r
+:0109ab00004b\r
+:0109ac00004a\r
+:0109ad000049\r
+:0109ae000048\r
+:0109af000047\r
+:0109b0000046\r
+:0109b1000045\r
+:0109b2000044\r
+:0109b3000043\r
+:0109b4000042\r
+:0109b5000041\r
+:0109b6000040\r
+:0109b700003f\r
+:0109b800003e\r
+:0109b900003d\r
+:0109ba00003c\r
+:0109bb00003b\r
+:0109bc00003a\r
+:0109bd000039\r
+:0109be000038\r
+:0109bf0090a7\r
+:0109c0000333\r
+:0109c1000035\r
+:0109c2000034\r
+:0109c3000033\r
+:0109c4000032\r
+:0109c5000031\r
+:0109c6000030\r
+:0109c700002f\r
+:0109c800002e\r
+:0109c900002d\r
+:0109ca00002c\r
+:0109cb00002b\r
+:0109cc00002a\r
+:0109cd000029\r
+:0109ce000028\r
+:0109cf000027\r
+:0109d0000026\r
+:0109d1000025\r
+:0109d2000024\r
+:0109d3000023\r
+:0109d4000022\r
+:0109d5000021\r
+:0109d6000020\r
+:0109d700001f\r
+:0109d800001e\r
+:0109d900001d\r
+:0109da00001c\r
+:0109db00001b\r
+:0109dc00001a\r
+:0109dd000019\r
+:0109de000018\r
+:0109df000017\r
+:0109e0000016\r
+:0109e1000015\r
+:0109e2000014\r
+:0109e3000013\r
+:0109e4000012\r
+:0109e5000011\r
+:0109e6000010\r
+:0109e700000f\r
+:0109e800000e\r
+:0109e900000d\r
+:0109ea00000c\r
+:0109eb00000b\r
+:0109ec00000a\r
+:0109ed000009\r
+:0109ee000008\r
+:0109ef000007\r
+:0109f0000006\r
+:0109f1000005\r
+:0109f2000004\r
+:0109f3000003\r
+:0109f4000002\r
+:0109f5000001\r
+:0109f6000000\r
+:0109f70000ff\r
+:0109f80000fe\r
+:0109f90000fd\r
+:0109fa0000fc\r
+:0109fb0000fb\r
+:0109fc0000fa\r
+:0109fd0000f9\r
+:0109fe0000f8\r
+:0109ff009067\r
+:010a000003f2\r
+:010a010000f4\r
+:010a020000f3\r
+:010a030000f2\r
+:010a040000f1\r
+:010a050000f0\r
+:010a060000ef\r
+:010a070000ee\r
+:010a080000ed\r
+:010a090000ec\r
+:010a0a0000eb\r
+:010a0b0000ea\r
+:010a0c0000e9\r
+:010a0d0000e8\r
+:010a0e0000e7\r
+:010a0f0000e6\r
+:010a100000e5\r
+:010a110000e4\r
+:010a120000e3\r
+:010a130000e2\r
+:010a140000e1\r
+:010a150000e0\r
+:010a160000df\r
+:010a170000de\r
+:010a180000dd\r
+:010a190000dc\r
+:010a1a0000db\r
+:010a1b0000da\r
+:010a1c0000d9\r
+:010a1d0000d8\r
+:010a1e0000d7\r
+:010a1f0000d6\r
+:010a200000d5\r
+:010a210000d4\r
+:010a220000d3\r
+:010a230000d2\r
+:010a240000d1\r
+:010a250000d0\r
+:010a260000cf\r
+:010a270000ce\r
+:010a280000cd\r
+:010a290000cc\r
+:010a2a0000cb\r
+:010a2b0000ca\r
+:010a2c0000c9\r
+:010a2d0000c8\r
+:010a2e0000c7\r
+:010a2f0000c6\r
+:010a300000c5\r
+:010a310000c4\r
+:010a320000c3\r
+:010a330000c2\r
+:010a340000c1\r
+:010a350000c0\r
+:010a360000bf\r
+:010a370000be\r
+:010a380000bd\r
+:010a390000bc\r
+:010a3a0000bb\r
+:010a3b0000ba\r
+:010a3c0000b9\r
+:010a3d0000b8\r
+:010a3e0000b7\r
+:010a3f009026\r
+:010a400003b2\r
+:010a410000b4\r
+:010a420000b3\r
+:010a430000b2\r
+:010a440000b1\r
+:010a450000b0\r
+:010a460000af\r
+:010a470000ae\r
+:010a480000ad\r
+:010a490000ac\r
+:010a4a0000ab\r
+:010a4b0000aa\r
+:010a4c0000a9\r
+:010a4d0000a8\r
+:010a4e0000a7\r
+:010a4f0000a6\r
+:010a500000a5\r
+:010a510000a4\r
+:010a520000a3\r
+:010a530000a2\r
+:010a540000a1\r
+:010a550000a0\r
+:010a5600009f\r
+:010a5700009e\r
+:010a5800009d\r
+:010a5900009c\r
+:010a5a00009b\r
+:010a5b00009a\r
+:010a5c000099\r
+:010a5d000098\r
+:010a5e000097\r
+:010a5f000096\r
+:010a60000095\r
+:010a61000094\r
+:010a62000093\r
+:010a63000092\r
+:010a64000091\r
+:010a65000090\r
+:010a6600008f\r
+:010a6700008e\r
+:010a6800008d\r
+:010a6900008c\r
+:010a6a00008b\r
+:010a6b00008a\r
+:010a6c000089\r
+:010a6d000088\r
+:010a6e000087\r
+:010a6f000086\r
+:010a70000085\r
+:010a71000084\r
+:010a72000083\r
+:010a73000082\r
+:010a74000081\r
+:010a75000080\r
+:010a7600007f\r
+:010a7700007e\r
+:010a7800007d\r
+:010a7900007c\r
+:010a7a00007b\r
+:010a7b00007a\r
+:010a7c000079\r
+:010a7d000078\r
+:010a7e000077\r
+:010a7f0090e6\r
+:010a80000372\r
+:010a81000074\r
+:010a82000073\r
+:010a83000072\r
+:010a84000071\r
+:010a85000070\r
+:010a8600006f\r
+:010a8700006e\r
+:010a8800006d\r
+:010a8900006c\r
+:010a8a00006b\r
+:010a8b00006a\r
+:010a8c000069\r
+:010a8d000068\r
+:010a8e000067\r
+:010a8f000066\r
+:010a90000065\r
+:010a91000064\r
+:010a92000063\r
+:010a93000062\r
+:010a94000061\r
+:010a95000060\r
+:010a9600005f\r
+:010a9700005e\r
+:010a9800005d\r
+:010a9900005c\r
+:010a9a00005b\r
+:010a9b00005a\r
+:010a9c000059\r
+:010a9d000058\r
+:010a9e000057\r
+:010a9f000056\r
+:010aa0000055\r
+:010aa1000054\r
+:010aa2000053\r
+:010aa3000052\r
+:010aa4000051\r
+:010aa5000050\r
+:010aa600004f\r
+:010aa700004e\r
+:010aa800004d\r
+:010aa900004c\r
+:010aaa00004b\r
+:010aab00004a\r
+:010aac000049\r
+:010aad000048\r
+:010aae000047\r
+:010aaf000046\r
+:010ab0000045\r
+:010ab1000044\r
+:010ab2000043\r
+:010ab3000042\r
+:010ab4000041\r
+:010ab5000040\r
+:010ab600003f\r
+:010ab700003e\r
+:010ab800003d\r
+:010ab900003c\r
+:010aba00003b\r
+:010abb00003a\r
+:010abc000039\r
+:010abd000038\r
+:010abe000037\r
+:010abf0090a6\r
+:010ac0000332\r
+:010ac1000034\r
+:010ac2000033\r
+:010ac3000032\r
+:010ac4000031\r
+:010ac5000030\r
+:010ac600002f\r
+:010ac700002e\r
+:010ac800002d\r
+:010ac900002c\r
+:010aca00002b\r
+:010acb00002a\r
+:010acc000029\r
+:010acd000028\r
+:010ace000027\r
+:010acf000026\r
+:010ad0000025\r
+:010ad1000024\r
+:010ad2000023\r
+:010ad3000022\r
+:010ad4000021\r
+:010ad5000020\r
+:010ad600001f\r
+:010ad700001e\r
+:010ad800001d\r
+:010ad900001c\r
+:010ada00001b\r
+:010adb00001a\r
+:010adc000019\r
+:010add000018\r
+:010ade000017\r
+:010adf000016\r
+:010ae0000015\r
+:010ae1000014\r
+:010ae2000013\r
+:010ae3000012\r
+:010ae4000011\r
+:010ae5000010\r
+:010ae600000f\r
+:010ae700000e\r
+:010ae800000d\r
+:010ae900000c\r
+:010aea00000b\r
+:010aeb00000a\r
+:010aec000009\r
+:010aed000008\r
+:010aee000007\r
+:010aef000006\r
+:010af0000005\r
+:010af1000004\r
+:010af2000003\r
+:010af3000002\r
+:010af4000001\r
+:010af5000000\r
+:010af60000ff\r
+:010af70000fe\r
+:010af80000fd\r
+:010af90000fc\r
+:010afa0000fb\r
+:010afb0000fa\r
+:010afc0000f9\r
+:010afd0000f8\r
+:010afe0000f7\r
+:010aff009066\r
+:010b000003f1\r
+:010b010000f3\r
+:010b020000f2\r
+:010b030000f1\r
+:010b040000f0\r
+:010b050000ef\r
+:010b060000ee\r
+:010b070000ed\r
+:010b080000ec\r
+:010b090000eb\r
+:010b0a0000ea\r
+:010b0b0000e9\r
+:010b0c0000e8\r
+:010b0d0000e7\r
+:010b0e0000e6\r
+:010b0f0000e5\r
+:010b100000e4\r
+:010b110000e3\r
+:010b120000e2\r
+:010b130000e1\r
+:010b140000e0\r
+:010b150000df\r
+:010b160000de\r
+:010b170000dd\r
+:010b180000dc\r
+:010b190000db\r
+:010b1a0000da\r
+:010b1b0000d9\r
+:010b1c0000d8\r
+:010b1d0000d7\r
+:010b1e0000d6\r
+:010b1f0000d5\r
+:010b200000d4\r
+:010b210000d3\r
+:010b220000d2\r
+:010b230000d1\r
+:010b240000d0\r
+:010b250000cf\r
+:010b260000ce\r
+:010b270000cd\r
+:010b280000cc\r
+:010b290000cb\r
+:010b2a0000ca\r
+:010b2b0000c9\r
+:010b2c0000c8\r
+:010b2d0000c7\r
+:010b2e0000c6\r
+:010b2f0000c5\r
+:010b300000c4\r
+:010b310000c3\r
+:010b320000c2\r
+:010b330000c1\r
+:010b340000c0\r
+:010b350000bf\r
+:010b360000be\r
+:010b370000bd\r
+:010b380000bc\r
+:010b390000bb\r
+:010b3a0000ba\r
+:010b3b0000b9\r
+:010b3c0000b8\r
+:010b3d0000b7\r
+:010b3e0000b6\r
+:010b3f009025\r
+:010b400003b1\r
+:010b410000b3\r
+:010b420000b2\r
+:010b430000b1\r
+:010b440000b0\r
+:010b450000af\r
+:010b460000ae\r
+:010b470000ad\r
+:010b480000ac\r
+:010b490000ab\r
+:010b4a0000aa\r
+:010b4b0000a9\r
+:010b4c0000a8\r
+:010b4d0000a7\r
+:010b4e0000a6\r
+:010b4f0000a5\r
+:010b500000a4\r
+:010b510000a3\r
+:010b520000a2\r
+:010b530000a1\r
+:010b540000a0\r
+:010b5500009f\r
+:010b5600009e\r
+:010b5700009d\r
+:010b5800009c\r
+:010b5900009b\r
+:010b5a00009a\r
+:010b5b000099\r
+:010b5c000098\r
+:010b5d000097\r
+:010b5e000096\r
+:010b5f000095\r
+:010b60000094\r
+:010b61000093\r
+:010b62000092\r
+:010b63000091\r
+:010b64000090\r
+:010b6500008f\r
+:010b6600008e\r
+:010b6700008d\r
+:010b6800008c\r
+:010b6900008b\r
+:010b6a00008a\r
+:010b6b000089\r
+:010b6c000088\r
+:010b6d000087\r
+:010b6e000086\r
+:010b6f000085\r
+:010b70000084\r
+:010b71000083\r
+:010b72000082\r
+:010b73000081\r
+:010b74000080\r
+:010b7500007f\r
+:010b7600007e\r
+:010b7700007d\r
+:010b7800007c\r
+:010b7900007b\r
+:010b7a00007a\r
+:010b7b000079\r
+:010b7c000078\r
+:010b7d000077\r
+:010b7e000076\r
+:010b7f0090e5\r
+:010b80000371\r
+:010b81000073\r
+:010b82000072\r
+:010b83000071\r
+:010b84000070\r
+:010b8500006f\r
+:010b8600006e\r
+:010b8700006d\r
+:010b8800006c\r
+:010b8900006b\r
+:010b8a00006a\r
+:010b8b000069\r
+:010b8c000068\r
+:010b8d000067\r
+:010b8e000066\r
+:010b8f000065\r
+:010b90000064\r
+:010b91000063\r
+:010b92000062\r
+:010b93000061\r
+:010b94000060\r
+:010b9500005f\r
+:010b9600005e\r
+:010b9700005d\r
+:010b9800005c\r
+:010b9900005b\r
+:010b9a00005a\r
+:010b9b000059\r
+:010b9c000058\r
+:010b9d000057\r
+:010b9e000056\r
+:010b9f000055\r
+:010ba0000054\r
+:010ba1000053\r
+:010ba2000052\r
+:010ba3000051\r
+:010ba4000050\r
+:010ba500004f\r
+:010ba600004e\r
+:010ba700004d\r
+:010ba800004c\r
+:010ba900004b\r
+:010baa00004a\r
+:010bab000049\r
+:010bac000048\r
+:010bad000047\r
+:010bae000046\r
+:010baf000045\r
+:010bb0000044\r
+:010bb1000043\r
+:010bb2000042\r
+:010bb3000041\r
+:010bb4000040\r
+:010bb500003f\r
+:010bb600003e\r
+:010bb700003d\r
+:010bb800003c\r
+:010bb900003b\r
+:010bba00003a\r
+:010bbb000039\r
+:010bbc000038\r
+:010bbd000037\r
+:010bbe000036\r
+:010bbf0090a5\r
+:010bc0000331\r
+:010bc1000033\r
+:010bc2000032\r
+:010bc3000031\r
+:010bc4000030\r
+:010bc500002f\r
+:010bc600002e\r
+:010bc700002d\r
+:010bc800002c\r
+:010bc900002b\r
+:010bca00002a\r
+:010bcb000029\r
+:010bcc000028\r
+:010bcd000027\r
+:010bce000026\r
+:010bcf000025\r
+:010bd0000024\r
+:010bd1000023\r
+:010bd2000022\r
+:010bd3000021\r
+:010bd4000020\r
+:010bd500001f\r
+:010bd600001e\r
+:010bd700001d\r
+:010bd800001c\r
+:010bd900001b\r
+:010bda00001a\r
+:010bdb000019\r
+:010bdc000018\r
+:010bdd000017\r
+:010bde000016\r
+:010bdf000015\r
+:010be0000014\r
+:010be1000013\r
+:010be2000012\r
+:010be3000011\r
+:010be4000010\r
+:010be500000f\r
+:010be600000e\r
+:010be700000d\r
+:010be800000c\r
+:010be900000b\r
+:010bea00000a\r
+:010beb000009\r
+:010bec000008\r
+:010bed000007\r
+:010bee000006\r
+:010bef000005\r
+:010bf0000004\r
+:010bf1000003\r
+:010bf2000002\r
+:010bf3000001\r
+:010bf4000000\r
+:010bf50000ff\r
+:010bf60000fe\r
+:010bf70000fd\r
+:010bf80000fc\r
+:010bf90000fb\r
+:010bfa0000fa\r
+:010bfb0000f9\r
+:010bfc0000f8\r
+:010bfd0000f7\r
+:010bfe0000f6\r
+:010bff009065\r
+:010c000003f0\r
+:010c010000f2\r
+:010c020000f1\r
+:010c030000f0\r
+:010c040000ef\r
+:010c050000ee\r
+:010c060000ed\r
+:010c070000ec\r
+:010c080000eb\r
+:010c090000ea\r
+:010c0a0000e9\r
+:010c0b0000e8\r
+:010c0c0000e7\r
+:010c0d0000e6\r
+:010c0e0000e5\r
+:010c0f0000e4\r
+:010c100000e3\r
+:010c110000e2\r
+:010c120000e1\r
+:010c130000e0\r
+:010c140000df\r
+:010c150000de\r
+:010c160000dd\r
+:010c170000dc\r
+:010c180000db\r
+:010c190000da\r
+:010c1a0000d9\r
+:010c1b0000d8\r
+:010c1c0000d7\r
+:010c1d0000d6\r
+:010c1e0000d5\r
+:010c1f0000d4\r
+:010c200000d3\r
+:010c210000d2\r
+:010c220000d1\r
+:010c230000d0\r
+:010c240000cf\r
+:010c250000ce\r
+:010c260000cd\r
+:010c270000cc\r
+:010c280000cb\r
+:010c290000ca\r
+:010c2a0000c9\r
+:010c2b0000c8\r
+:010c2c0000c7\r
+:010c2d0000c6\r
+:010c2e0000c5\r
+:010c2f0000c4\r
+:010c300000c3\r
+:010c310000c2\r
+:010c320000c1\r
+:010c330000c0\r
+:010c340000bf\r
+:010c350000be\r
+:010c360000bd\r
+:010c370000bc\r
+:010c380000bb\r
+:010c390000ba\r
+:010c3a0000b9\r
+:010c3b0000b8\r
+:010c3c0000b7\r
+:010c3d0000b6\r
+:010c3e0000b5\r
+:010c3f009024\r
+:010c400003b0\r
+:010c410000b2\r
+:010c420000b1\r
+:010c430000b0\r
+:010c440000af\r
+:010c450000ae\r
+:010c460000ad\r
+:010c470000ac\r
+:010c480000ab\r
+:010c490000aa\r
+:010c4a0000a9\r
+:010c4b0000a8\r
+:010c4c0000a7\r
+:010c4d0000a6\r
+:010c4e0000a5\r
+:010c4f0000a4\r
+:010c500000a3\r
+:010c510000a2\r
+:010c520000a1\r
+:010c530000a0\r
+:010c5400009f\r
+:010c5500009e\r
+:010c5600009d\r
+:010c5700009c\r
+:010c5800009b\r
+:010c5900009a\r
+:010c5a000099\r
+:010c5b000098\r
+:010c5c000097\r
+:010c5d000096\r
+:010c5e000095\r
+:010c5f000094\r
+:010c60000093\r
+:010c61000092\r
+:010c62000091\r
+:010c63000090\r
+:010c6400008f\r
+:010c6500008e\r
+:010c6600008d\r
+:010c6700008c\r
+:010c6800008b\r
+:010c6900008a\r
+:010c6a000089\r
+:010c6b000088\r
+:010c6c000087\r
+:010c6d000086\r
+:010c6e000085\r
+:010c6f000084\r
+:010c70000083\r
+:010c71000082\r
+:010c72000081\r
+:010c73000080\r
+:010c7400007f\r
+:010c7500007e\r
+:010c7600007d\r
+:010c7700007c\r
+:010c7800007b\r
+:010c7900007a\r
+:010c7a000079\r
+:010c7b000078\r
+:010c7c000077\r
+:010c7d000076\r
+:010c7e000075\r
+:010c7f0090e4\r
+:010c80000370\r
+:010c81000072\r
+:010c82000071\r
+:010c83000070\r
+:010c8400006f\r
+:010c8500006e\r
+:010c8600006d\r
+:010c8700006c\r
+:010c8800006b\r
+:010c8900006a\r
+:010c8a000069\r
+:010c8b000068\r
+:010c8c000067\r
+:010c8d000066\r
+:010c8e000065\r
+:010c8f000064\r
+:010c90000063\r
+:010c91000062\r
+:010c92000061\r
+:010c93000060\r
+:010c9400005f\r
+:010c9500005e\r
+:010c9600005d\r
+:010c9700005c\r
+:010c9800005b\r
+:010c9900005a\r
+:010c9a000059\r
+:010c9b000058\r
+:010c9c000057\r
+:010c9d000056\r
+:010c9e000055\r
+:010c9f000054\r
+:010ca0000053\r
+:010ca1000052\r
+:010ca2000051\r
+:010ca3000050\r
+:010ca400004f\r
+:010ca500004e\r
+:010ca600004d\r
+:010ca700004c\r
+:010ca800004b\r
+:010ca900004a\r
+:010caa000049\r
+:010cab000048\r
+:010cac000047\r
+:010cad000046\r
+:010cae000045\r
+:010caf000044\r
+:010cb0000043\r
+:010cb1000042\r
+:010cb2000041\r
+:010cb3000040\r
+:010cb400003f\r
+:010cb500003e\r
+:010cb600003d\r
+:010cb700003c\r
+:010cb800003b\r
+:010cb900003a\r
+:010cba000039\r
+:010cbb000038\r
+:010cbc000037\r
+:010cbd000036\r
+:010cbe000035\r
+:010cbf0090a4\r
+:010cc0000330\r
+:010cc1000032\r
+:010cc2000031\r
+:010cc3000030\r
+:010cc400002f\r
+:010cc500002e\r
+:010cc600002d\r
+:010cc700002c\r
+:010cc800002b\r
+:010cc900002a\r
+:010cca000029\r
+:010ccb000028\r
+:010ccc000027\r
+:010ccd000026\r
+:010cce000025\r
+:010ccf000024\r
+:010cd0000023\r
+:010cd1000022\r
+:010cd2000021\r
+:010cd3000020\r
+:010cd400001f\r
+:010cd500001e\r
+:010cd600001d\r
+:010cd700001c\r
+:010cd800001b\r
+:010cd900001a\r
+:010cda000019\r
+:010cdb000018\r
+:010cdc000017\r
+:010cdd000016\r
+:010cde000015\r
+:010cdf000014\r
+:010ce0000013\r
+:010ce1000012\r
+:010ce2000011\r
+:010ce3000010\r
+:010ce400000f\r
+:010ce500000e\r
+:010ce600000d\r
+:010ce700000c\r
+:010ce800000b\r
+:010ce900000a\r
+:010cea000009\r
+:010ceb000008\r
+:010cec000007\r
+:010ced000006\r
+:010cee000005\r
+:010cef000004\r
+:010cf0000003\r
+:010cf1000002\r
+:010cf2000001\r
+:010cf3000000\r
+:010cf40000ff\r
+:010cf50000fe\r
+:010cf60000fd\r
+:010cf70000fc\r
+:010cf80000fb\r
+:010cf90000fa\r
+:010cfa0000f9\r
+:010cfb0000f8\r
+:010cfc0000f7\r
+:010cfd0000f6\r
+:010cfe0000f5\r
+:010cff009064\r
+:010d000003ef\r
+:010d010000f1\r
+:010d020000f0\r
+:010d030000ef\r
+:010d040000ee\r
+:010d050000ed\r
+:010d060000ec\r
+:010d070000eb\r
+:010d080000ea\r
+:010d090000e9\r
+:010d0a0000e8\r
+:010d0b0000e7\r
+:010d0c0000e6\r
+:010d0d0000e5\r
+:010d0e0000e4\r
+:010d0f0000e3\r
+:010d100000e2\r
+:010d110000e1\r
+:010d120000e0\r
+:010d130000df\r
+:010d140000de\r
+:010d150000dd\r
+:010d160000dc\r
+:010d170000db\r
+:010d180000da\r
+:010d190000d9\r
+:010d1a0000d8\r
+:010d1b0000d7\r
+:010d1c0000d6\r
+:010d1d0000d5\r
+:010d1e0000d4\r
+:010d1f0000d3\r
+:010d200000d2\r
+:010d210000d1\r
+:010d220000d0\r
+:010d230000cf\r
+:010d240000ce\r
+:010d250000cd\r
+:010d260000cc\r
+:010d270000cb\r
+:010d280000ca\r
+:010d290000c9\r
+:010d2a0000c8\r
+:010d2b0000c7\r
+:010d2c0000c6\r
+:010d2d0000c5\r
+:010d2e0000c4\r
+:010d2f0000c3\r
+:010d300000c2\r
+:010d310000c1\r
+:010d320000c0\r
+:010d330000bf\r
+:010d340000be\r
+:010d350000bd\r
+:010d360000bc\r
+:010d370000bb\r
+:010d380000ba\r
+:010d390000b9\r
+:010d3a0000b8\r
+:010d3b0000b7\r
+:010d3c0000b6\r
+:010d3d0000b5\r
+:010d3e0000b4\r
+:010d3f009023\r
+:010d400003af\r
+:010d410000b1\r
+:010d420000b0\r
+:010d430000af\r
+:010d440000ae\r
+:010d450000ad\r
+:010d460000ac\r
+:010d470000ab\r
+:010d480000aa\r
+:010d490000a9\r
+:010d4a0000a8\r
+:010d4b0000a7\r
+:010d4c0000a6\r
+:010d4d0000a5\r
+:010d4e0000a4\r
+:010d4f0000a3\r
+:010d500000a2\r
+:010d510000a1\r
+:010d520000a0\r
+:010d5300009f\r
+:010d5400009e\r
+:010d5500009d\r
+:010d5600009c\r
+:010d5700009b\r
+:010d5800009a\r
+:010d59000099\r
+:010d5a000098\r
+:010d5b000097\r
+:010d5c000096\r
+:010d5d000095\r
+:010d5e000094\r
+:010d5f000093\r
+:010d60000092\r
+:010d61000091\r
+:010d62000090\r
+:010d6300008f\r
+:010d6400008e\r
+:010d6500008d\r
+:010d6600008c\r
+:010d6700008b\r
+:010d6800008a\r
+:010d69000089\r
+:010d6a000088\r
+:010d6b000087\r
+:010d6c000086\r
+:010d6d000085\r
+:010d6e000084\r
+:010d6f000083\r
+:010d70000082\r
+:010d71000081\r
+:010d72000080\r
+:010d7300007f\r
+:010d7400007e\r
+:010d7500007d\r
+:010d7600007c\r
+:010d7700007b\r
+:010d7800007a\r
+:010d79000079\r
+:010d7a000078\r
+:010d7b000077\r
+:010d7c000076\r
+:010d7d000075\r
+:010d7e000074\r
+:010d7f0090e3\r
+:010d8000036f\r
+:010d81000071\r
+:010d82000070\r
+:010d8300006f\r
+:010d8400006e\r
+:010d8500006d\r
+:010d8600006c\r
+:010d8700006b\r
+:010d8800006a\r
+:010d89000069\r
+:010d8a000068\r
+:010d8b000067\r
+:010d8c000066\r
+:010d8d000065\r
+:010d8e000064\r
+:010d8f000063\r
+:010d90000062\r
+:010d91000061\r
+:010d92000060\r
+:010d9300005f\r
+:010d9400005e\r
+:010d9500005d\r
+:010d9600005c\r
+:010d9700005b\r
+:010d9800005a\r
+:010d99000059\r
+:010d9a000058\r
+:010d9b000057\r
+:010d9c000056\r
+:010d9d000055\r
+:010d9e000054\r
+:010d9f000053\r
+:010da0000052\r
+:010da1000051\r
+:010da2000050\r
+:010da300004f\r
+:010da400004e\r
+:010da500004d\r
+:010da600004c\r
+:010da700004b\r
+:010da800004a\r
+:010da9000049\r
+:010daa000048\r
+:010dab000047\r
+:010dac000046\r
+:010dad000045\r
+:010dae000044\r
+:010daf000043\r
+:010db0000042\r
+:010db1000041\r
+:010db2000040\r
+:010db300003f\r
+:010db400003e\r
+:010db500003d\r
+:010db600003c\r
+:010db700003b\r
+:010db800003a\r
+:010db9000039\r
+:010dba000038\r
+:010dbb000037\r
+:010dbc000036\r
+:010dbd000035\r
+:010dbe000034\r
+:010dbf0090a3\r
+:010dc000032f\r
+:010dc1000031\r
+:010dc2000030\r
+:010dc300002f\r
+:010dc400002e\r
+:010dc500002d\r
+:010dc600002c\r
+:010dc700002b\r
+:010dc800002a\r
+:010dc9000029\r
+:010dca000028\r
+:010dcb000027\r
+:010dcc000026\r
+:010dcd000025\r
+:010dce000024\r
+:010dcf000023\r
+:010dd0000022\r
+:010dd1000021\r
+:010dd2000020\r
+:010dd300001f\r
+:010dd400001e\r
+:010dd500001d\r
+:010dd600001c\r
+:010dd700001b\r
+:010dd800001a\r
+:010dd9000019\r
+:010dda000018\r
+:010ddb000017\r
+:010ddc000016\r
+:010ddd000015\r
+:010dde000014\r
+:010ddf000013\r
+:010de0000012\r
+:010de1000011\r
+:010de2000010\r
+:010de300000f\r
+:010de400000e\r
+:010de500000d\r
+:010de600000c\r
+:010de700000b\r
+:010de800000a\r
+:010de9000009\r
+:010dea000008\r
+:010deb000007\r
+:010dec000006\r
+:010ded000005\r
+:010dee000004\r
+:010def000003\r
+:010df0000002\r
+:010df1000001\r
+:010df2000000\r
+:010df30000ff\r
+:010df40000fe\r
+:010df50000fd\r
+:010df60000fc\r
+:010df70000fb\r
+:010df80000fa\r
+:010df90000f9\r
+:010dfa0000f8\r
+:010dfb0000f7\r
+:010dfc0000f6\r
+:010dfd0000f5\r
+:010dfe0000f4\r
+:010dff009063\r
+:010e000003ee\r
+:010e010000f0\r
+:010e020000ef\r
+:010e030000ee\r
+:010e040000ed\r
+:010e050000ec\r
+:010e060000eb\r
+:010e070000ea\r
+:010e080000e9\r
+:010e090000e8\r
+:010e0a0000e7\r
+:010e0b0000e6\r
+:010e0c0000e5\r
+:010e0d0000e4\r
+:010e0e0000e3\r
+:010e0f0000e2\r
+:010e100000e1\r
+:010e110000e0\r
+:010e120000df\r
+:010e130000de\r
+:010e140000dd\r
+:010e150000dc\r
+:010e160000db\r
+:010e170000da\r
+:010e180000d9\r
+:010e190000d8\r
+:010e1a0000d7\r
+:010e1b0000d6\r
+:010e1c0000d5\r
+:010e1d0000d4\r
+:010e1e0000d3\r
+:010e1f0000d2\r
+:010e200000d1\r
+:010e210000d0\r
+:010e220000cf\r
+:010e230000ce\r
+:010e240000cd\r
+:010e250000cc\r
+:010e260000cb\r
+:010e270000ca\r
+:010e280000c9\r
+:010e290000c8\r
+:010e2a0000c7\r
+:010e2b0000c6\r
+:010e2c0000c5\r
+:010e2d0000c4\r
+:010e2e0000c3\r
+:010e2f0000c2\r
+:010e300000c1\r
+:010e310000c0\r
+:010e320000bf\r
+:010e330000be\r
+:010e340000bd\r
+:010e350000bc\r
+:010e360000bb\r
+:010e370000ba\r
+:010e380000b9\r
+:010e390000b8\r
+:010e3a0000b7\r
+:010e3b0000b6\r
+:010e3c0000b5\r
+:010e3d0000b4\r
+:010e3e0000b3\r
+:010e3f009022\r
+:010e400003ae\r
+:010e410000b0\r
+:010e420000af\r
+:010e430000ae\r
+:010e440000ad\r
+:010e450000ac\r
+:010e460000ab\r
+:010e470000aa\r
+:010e480000a9\r
+:010e490000a8\r
+:010e4a0000a7\r
+:010e4b0000a6\r
+:010e4c0000a5\r
+:010e4d0000a4\r
+:010e4e0000a3\r
+:010e4f0000a2\r
+:010e500000a1\r
+:010e510000a0\r
+:010e5200009f\r
+:010e5300009e\r
+:010e5400009d\r
+:010e5500009c\r
+:010e5600009b\r
+:010e5700009a\r
+:010e58000099\r
+:010e59000098\r
+:010e5a000097\r
+:010e5b000096\r
+:010e5c000095\r
+:010e5d000094\r
+:010e5e000093\r
+:010e5f000092\r
+:010e60000091\r
+:010e61000090\r
+:010e6200008f\r
+:010e6300008e\r
+:010e6400008d\r
+:010e6500008c\r
+:010e6600008b\r
+:010e6700008a\r
+:010e68000089\r
+:010e69000088\r
+:010e6a000087\r
+:010e6b000086\r
+:010e6c000085\r
+:010e6d000084\r
+:010e6e000083\r
+:010e6f000082\r
+:010e70000081\r
+:010e71000080\r
+:010e7200007f\r
+:010e7300007e\r
+:010e7400007d\r
+:010e7500007c\r
+:010e7600007b\r
+:010e7700007a\r
+:010e78000079\r
+:010e79000078\r
+:010e7a000077\r
+:010e7b000076\r
+:010e7c000075\r
+:010e7d000074\r
+:010e7e000073\r
+:010e7f0090e2\r
+:010e8000036e\r
+:010e81000070\r
+:010e8200006f\r
+:010e8300006e\r
+:010e8400006d\r
+:010e8500006c\r
+:010e8600006b\r
+:010e8700006a\r
+:010e88000069\r
+:010e89000068\r
+:010e8a000067\r
+:010e8b000066\r
+:010e8c000065\r
+:010e8d000064\r
+:010e8e000063\r
+:010e8f000062\r
+:010e90000061\r
+:010e91000060\r
+:010e9200005f\r
+:010e9300005e\r
+:010e9400005d\r
+:010e9500005c\r
+:010e9600005b\r
+:010e9700005a\r
+:010e98000059\r
+:010e99000058\r
+:010e9a000057\r
+:010e9b000056\r
+:010e9c000055\r
+:010e9d000054\r
+:010e9e000053\r
+:010e9f000052\r
+:010ea0000051\r
+:010ea1000050\r
+:010ea200004f\r
+:010ea300004e\r
+:010ea400004d\r
+:010ea500004c\r
+:010ea600004b\r
+:010ea700004a\r
+:010ea8000049\r
+:010ea9000048\r
+:010eaa000047\r
+:010eab000046\r
+:010eac000045\r
+:010ead000044\r
+:010eae000043\r
+:010eaf000042\r
+:010eb0000041\r
+:010eb1000040\r
+:010eb200003f\r
+:010eb300003e\r
+:010eb400003d\r
+:010eb500003c\r
+:010eb600003b\r
+:010eb700003a\r
+:010eb8000039\r
+:010eb9000038\r
+:010eba000037\r
+:010ebb000036\r
+:010ebc000035\r
+:010ebd000034\r
+:010ebe000033\r
+:010ebf0090a2\r
+:010ec000032e\r
+:010ec1000030\r
+:010ec200002f\r
+:010ec300002e\r
+:010ec400002d\r
+:010ec500002c\r
+:010ec600002b\r
+:010ec700002a\r
+:010ec8000029\r
+:010ec9000028\r
+:010eca000027\r
+:010ecb000026\r
+:010ecc000025\r
+:010ecd000024\r
+:010ece000023\r
+:010ecf000022\r
+:010ed0000021\r
+:010ed1000020\r
+:010ed200001f\r
+:010ed300001e\r
+:010ed400001d\r
+:010ed500001c\r
+:010ed600001b\r
+:010ed700001a\r
+:010ed8000019\r
+:010ed9000018\r
+:010eda000017\r
+:010edb000016\r
+:010edc000015\r
+:010edd000014\r
+:010ede000013\r
+:010edf000012\r
+:010ee0000011\r
+:010ee1000010\r
+:010ee200000f\r
+:010ee300000e\r
+:010ee400000d\r
+:010ee500000c\r
+:010ee600000b\r
+:010ee700000a\r
+:010ee8000009\r
+:010ee9000008\r
+:010eea000007\r
+:010eeb000006\r
+:010eec000005\r
+:010eed000004\r
+:010eee000003\r
+:010eef000002\r
+:010ef0000001\r
+:010ef1000000\r
+:010ef20000ff\r
+:010ef30000fe\r
+:010ef40000fd\r
+:010ef50000fc\r
+:010ef60000fb\r
+:010ef70000fa\r
+:010ef80000f9\r
+:010ef90000f8\r
+:010efa0000f7\r
+:010efb0000f6\r
+:010efc0000f5\r
+:010efd0000f4\r
+:010efe0000f3\r
+:010eff009062\r
+:010f000003ed\r
+:010f010000ef\r
+:010f020000ee\r
+:010f030000ed\r
+:010f040000ec\r
+:010f050000eb\r
+:010f060000ea\r
+:010f070000e9\r
+:010f080000e8\r
+:010f090000e7\r
+:010f0a0000e6\r
+:010f0b0000e5\r
+:010f0c0000e4\r
+:010f0d0000e3\r
+:010f0e0000e2\r
+:010f0f0000e1\r
+:010f100000e0\r
+:010f110000df\r
+:010f120000de\r
+:010f130000dd\r
+:010f140000dc\r
+:010f150000db\r
+:010f160000da\r
+:010f170000d9\r
+:010f180000d8\r
+:010f190000d7\r
+:010f1a0000d6\r
+:010f1b0000d5\r
+:010f1c0000d4\r
+:010f1d0000d3\r
+:010f1e0000d2\r
+:010f1f0000d1\r
+:010f200000d0\r
+:010f210000cf\r
+:010f220000ce\r
+:010f230000cd\r
+:010f240000cc\r
+:010f250000cb\r
+:010f260000ca\r
+:010f270000c9\r
+:010f280000c8\r
+:010f290000c7\r
+:010f2a0000c6\r
+:010f2b0000c5\r
+:010f2c0000c4\r
+:010f2d0000c3\r
+:010f2e0000c2\r
+:010f2f0000c1\r
+:010f300000c0\r
+:010f310000bf\r
+:010f320000be\r
+:010f330000bd\r
+:010f340000bc\r
+:010f350000bb\r
+:010f360000ba\r
+:010f370000b9\r
+:010f380000b8\r
+:010f390000b7\r
+:010f3a0000b6\r
+:010f3b0000b5\r
+:010f3c0000b4\r
+:010f3d0000b3\r
+:010f3e0000b2\r
+:010f3f009021\r
+:010f400003ad\r
+:010f410000af\r
+:010f420000ae\r
+:010f430000ad\r
+:010f440000ac\r
+:010f450000ab\r
+:010f460000aa\r
+:010f470000a9\r
+:010f480000a8\r
+:010f490000a7\r
+:010f4a0000a6\r
+:010f4b0000a5\r
+:010f4c0000a4\r
+:010f4d0000a3\r
+:010f4e0000a2\r
+:010f4f0000a1\r
+:010f500000a0\r
+:010f5100009f\r
+:010f5200009e\r
+:010f5300009d\r
+:010f5400009c\r
+:010f5500009b\r
+:010f5600009a\r
+:010f57000099\r
+:010f58000098\r
+:010f59000097\r
+:010f5a000096\r
+:010f5b000095\r
+:010f5c000094\r
+:010f5d000093\r
+:010f5e000092\r
+:010f5f000091\r
+:010f60000090\r
+:010f6100008f\r
+:010f6200008e\r
+:010f6300008d\r
+:010f6400008c\r
+:010f6500008b\r
+:010f6600008a\r
+:010f67000089\r
+:010f68000088\r
+:010f69000087\r
+:010f6a000086\r
+:010f6b000085\r
+:010f6c000084\r
+:010f6d000083\r
+:010f6e000082\r
+:010f6f000081\r
+:010f70000080\r
+:010f7100007f\r
+:010f7200007e\r
+:010f7300007d\r
+:010f7400007c\r
+:010f7500007b\r
+:010f7600007a\r
+:010f77000079\r
+:010f78000078\r
+:010f79000077\r
+:010f7a000076\r
+:010f7b000075\r
+:010f7c000074\r
+:010f7d000073\r
+:010f7e000072\r
+:010f7f0090e1\r
+:010f8000036d\r
+:010f8100006f\r
+:010f8200006e\r
+:010f8300006d\r
+:010f8400006c\r
+:010f8500006b\r
+:010f8600006a\r
+:010f87000069\r
+:010f88000068\r
+:010f89000067\r
+:010f8a000066\r
+:010f8b000065\r
+:010f8c000064\r
+:010f8d000063\r
+:010f8e000062\r
+:010f8f000061\r
+:010f90000060\r
+:010f9100005f\r
+:010f9200005e\r
+:010f9300005d\r
+:010f9400005c\r
+:010f9500005b\r
+:010f9600005a\r
+:010f97000059\r
+:010f98000058\r
+:010f99000057\r
+:010f9a000056\r
+:010f9b000055\r
+:010f9c000054\r
+:010f9d000053\r
+:010f9e000052\r
+:010f9f000051\r
+:010fa0000050\r
+:010fa100004f\r
+:010fa200004e\r
+:010fa300004d\r
+:010fa400004c\r
+:010fa500004b\r
+:010fa600004a\r
+:010fa7000049\r
+:010fa8000048\r
+:010fa9000047\r
+:010faa000046\r
+:010fab000045\r
+:010fac000044\r
+:010fad000043\r
+:010fae000042\r
+:010faf000041\r
+:010fb0000040\r
+:010fb100003f\r
+:010fb200003e\r
+:010fb300003d\r
+:010fb400003c\r
+:010fb500003b\r
+:010fb600003a\r
+:010fb7000039\r
+:010fb8000038\r
+:010fb9000037\r
+:010fba000036\r
+:010fbb000035\r
+:010fbc000034\r
+:010fbd000033\r
+:010fbe000032\r
+:010fbf0090a1\r
+:010fc000e050\r
+:010fc100e04f\r
+:010fc200e04e\r
+:010fc300e04d\r
+:010fc400e04c\r
+:010fc500e04b\r
+:010fc600e04a\r
+:010fc700e049\r
+:010fc800e048\r
+:010fc900e047\r
+:010fca00e046\r
+:010fcb00e045\r
+:010fcc00e044\r
+:010fcd00e043\r
+:010fce00e042\r
+:010fcf00e041\r
+:010fd000e040\r
+:010fd100e03f\r
+:010fd200e03e\r
+:010fd300e03d\r
+:010fd400e03c\r
+:010fd500e03b\r
+:010fd600e03a\r
+:010fd700e039\r
+:010fd800e038\r
+:010fd900e037\r
+:010fda00e036\r
+:010fdb00e035\r
+:010fdc00e034\r
+:010fdd00e033\r
+:010fde00e032\r
+:010fdf00e031\r
+:010fe000e030\r
+:010fe100e02f\r
+:010fe200e02e\r
+:010fe300e02d\r
+:010fe400e02c\r
+:010fe500e02b\r
+:010fe600e02a\r
+:010fe700e029\r
+:010fe800e028\r
+:010fe900e027\r
+:010fea00e026\r
+:010feb00e025\r
+:010fec00e024\r
+:010fed00e023\r
+:010fee00e022\r
+:010fef00e021\r
+:010ff000e020\r
+:010ff100e01f\r
+:010ff200e01e\r
+:010ff300e01d\r
+:010ff400e01c\r
+:010ff500e01b\r
+:010ff600e01a\r
+:010ff700e019\r
+:010ff800e018\r
+:010ff900e017\r
+:010ffa00e016\r
+:010ffb00e015\r
+:010ffc00e014\r
+:010ffd00e013\r
+:010ffe00e012\r
+:010fff00e011\r
+:00000001ff\r
--- /dev/null
+ -------------------------------------------------------------------------------\r
+-- Title : vga architecture\r
+-- Project : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File : vga.vhd\r
+-- Author : Thomas Handl\r
+-- Company : TU Wien\r
+-- Created : 2004-04-07\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: arch of top level module, the sub-modules are connected here\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions :\r
+-- Date Version Author Description\r
+-- 2004-04-07 1.0 handl Created\r
+-- 2006-02-24 2.0 ST revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all; -- include package\r
+\r
+-------------------------------------------------------------------------------\r
+-- ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
+\r
+architecture behav of vga is\r
+\r
+ attribute syn_preserve : boolean;\r
+ attribute syn_preserve of behav : architecture is true;\r
+\r
+\r
+-------------------------------------------------------------------------------\r
+-- component declarations for the modules\r
+-------------------------------------------------------------------------------\r
+\r
+ component vga_driver\r
+ port (\r
+ clk : in std_logic;\r
+ reset : in std_logic;\r
+ column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);\r
+ line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);\r
+ h_enable : out std_logic;\r
+ v_enable : out std_logic;\r
+ hsync : out std_logic; \r
+ vsync : out std_logic;\r
+ d_hsync_state : out hsync_state_type;\r
+ d_vsync_state : out vsync_state_type;\r
+ d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);\r
+ d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);\r
+ d_set_hsync_counter : out std_logic;\r
+ d_set_vsync_counter : out std_logic;\r
+ d_set_column_counter : out std_logic;\r
+ d_set_line_counter : out std_logic);\r
+ end component;\r
+\r
+\r
+ component vga_control\r
+ port (\r
+ clk : in std_logic;\r
+ reset : in std_logic;\r
+ column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0);\r
+ line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0);\r
+ h_enable : in std_logic;\r
+ v_enable : in std_logic;\r
+ toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0);\r
+ toggle : out std_logic;\r
+ r, g, b : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component board_driver\r
+ port (\r
+ reset : in std_logic;\r
+ seven_seg : out std_logic_vector(2*SEG_WIDTH-1 downto 0));\r
+ end component;\r
+\r
+\r
+-- declare signals needed for internal wiring of these components later\r
+ signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0);\r
+ signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);\r
+ signal h_enable_sig : std_logic;\r
+ signal v_enable_sig : std_logic;\r
+ signal r_sig, g_sig, b_sig : std_logic;\r
+ signal hsync_sig, vsync_sig : std_logic;\r
+ \r
+-- declare signals needed for prolongation of reset\r
+ signal dly_counter : std_logic_vector(1 downto 0);\r
+ signal dly_counter_next : std_logic_vector(1 downto 0);\r
+ constant MAX_DLY : std_logic_vector(1 downto 0) := "11";\r
+ signal reset_dly : std_logic; --\r
+ signal safe_reset : std_logic; \r
+\r
+\r
+-------------------------------------------------------------------------------\r
+-- prolong duration of reset to prevent glitches at power-up\r
+-------------------------------------------------------------------------------\r
+\r
+begin\r
+\r
+ DELAY_RESET_syn : process(clk_pin) -- synchronous capture\r
+ begin\r
+ if clk_pin'event and clk_pin = '1' then -- upon rising clock\r
+ dly_counter <= dly_counter_next; -- ... capture new counter value\r
+ end if;\r
+ end process;\r
+\r
+ DELAY_RESET_next : process(dly_counter, reset_pin) -- next state logic\r
+ begin\r
+ if reset_pin = RES_ACT then -- upon reset\r
+ dly_counter_next <= (others => '0'); -- ...clear dly counter\r
+ elsif dly_counter < MAX_DLY then -- if no oflo\r
+ dly_counter_next <= dly_counter + '1'; -- ...increment dly counter\r
+ else \r
+ dly_counter_next <= dly_counter; -- freeze dly counter when oflo\r
+ end if;\r
+ end process;\r
+ \r
+ DELAY_RESET_out: process(dly_counter)\r
+ begin\r
+ if dly_counter < MAX_DLY then -- until dly counter reaches maximum\r
+ reset_dly <= RES_ACT; -- ...activate delayed reset signal\r
+ else -- upon counter oflo \r
+ reset_dly <= not(RES_ACT); -- ...finally deactivate delayed reset\r
+ end if;\r
+ end process;\r
+\r
+\r
+\r
+ COMBINE_RESET: process(reset_pin, reset_dly) -- generate "safe" reset signal\r
+ begin\r
+ if reset_pin = RES_ACT or reset_dly = RES_ACT then -- ...by combining delayed reset with non-delayed reset input \r
+ safe_reset <= RES_ACT;\r
+ else\r
+ safe_reset <= not(RES_ACT);\r
+ end if;\r
+ end process;\r
+\r
+\r
+-------------------------------------------------------------------------------\r
+-- instantiate the components and connect to internal and external signals\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+board_driver_unit : board_driver\r
+ port map (\r
+ reset => safe_reset,\r
+ seven_seg => seven_seg_pin);\r
+\r
+\r
+vga_driver_unit : vga_driver\r
+ port map (\r
+ clk => clk_pin,\r
+ reset => safe_reset,\r
+ column_counter => column_counter_sig,\r
+ line_counter => line_counter_sig,\r
+ h_enable => h_enable_sig,\r
+ v_enable => v_enable_sig,\r
+ hsync => hsync_sig,\r
+ vsync => vsync_sig,\r
+ d_hsync_state => d_hsync_state,\r
+ d_vsync_state => d_vsync_state,\r
+ d_hsync_counter => d_hsync_counter,\r
+ d_vsync_counter => d_vsync_counter,\r
+ d_set_hsync_counter => d_set_hsync_counter,\r
+ d_set_vsync_counter => d_set_vsync_counter,\r
+ d_set_column_counter => d_set_column_counter,\r
+ d_set_line_counter => d_set_line_counter);\r
+\r
+-- make the wiring for hsync and vsync pins \r
+-- (pin is output only => internal _sig version required to allow readback of signal)\r
+ vsync_pin <= vsync_sig;\r
+ hsync_pin <= hsync_sig;\r
+\r
+\r
+ vga_control_unit : vga_control\r
+ port map (\r
+ clk => clk_pin,\r
+ reset => safe_reset,\r
+ column_counter => column_counter_sig,\r
+ line_counter => line_counter_sig,\r
+ h_enable => h_enable_sig,\r
+ v_enable => v_enable_sig,\r
+ toggle_counter => d_toggle_counter,\r
+ toggle => d_toggle,\r
+ r => r_sig,\r
+ g => g_sig,\r
+ b => b_sig);\r
+\r
+-- make the wiring for RGB pins: drive all pins for same color from one source ("8 color mode")\r
+ r0_pin <= r_sig; r1_pin <= r_sig; r2_pin <= r_sig;\r
+ g0_pin <= g_sig; g1_pin <= g_sig; g2_pin <= g_sig;\r
+ b0_pin <= b_sig; b1_pin <= b_sig;\r
+\r
+\r
+-- make extra pin connections for debug signals\r
+ d_hsync <= hsync_sig; -- make duplicate of signal for debug connector\r
+ d_vsync <= vsync_sig; -- make duplicate of signal for debug connector\r
+ d_column_counter <= column_counter_sig;\r
+ d_line_counter <= line_counter_sig;\r
+ d_h_enable <= h_enable_sig;\r
+ d_v_enable <= v_enable_sig;\r
+ d_r <= r_sig;\r
+ d_g <= g_sig;\r
+ d_b <= b_sig;\r
+ d_state_clk <= clk_pin; -- make duplicate of signal for debug connector\r
+\r
+ \r
+end behav;\r
+\r
+-------------------------------------------------------------------------------\r
+-- END ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : vga testbench
+-- Project :
+-------------------------------------------------------------------------------
+-- File : vga_tb.vhd
+-- Author : Thomas Handl
+-- Company : TU Wien
+-- Created : 2004-04-07
+-- Last update: 2006-09-29
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004 TU Wien
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2004-04-07 1.0 handl Created
+-------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- LIBRARIES
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use work.vga_pak.all;
+
+
+-------------------------------------------------------------------------------
+-- ENTITY
+-------------------------------------------------------------------------------
+entity vga_tb is
+
+end vga_tb;
+
+
+-------------------------------------------------------------------------------
+-- ARCHITECTURE
+-------------------------------------------------------------------------------
+architecture behaviour of vga_tb is
+
+ constant cc : time := 39.7 ns; -- test clock period
+ component vga
+ port (
+ clk_pin : in std_logic;
+ reset_pin : in std_logic;
+ r0_pin, r1_pin, r2_pin : out std_logic;
+ g0_pin, g1_pin, g2_pin : out std_logic;
+ b0_pin, b1_pin : out std_logic;
+ hsync_pin : out std_logic;
+ vsync_pin : out std_logic;
+ seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
+ d_hsync, d_vsync : out std_logic;
+ d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ d_set_column_counter, d_set_line_counter : out std_logic;
+ d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ d_set_hsync_counter, d_set_vsync_counter : out std_logic;
+ d_h_enable : out std_logic;
+ d_v_enable : out std_logic;
+ d_r, d_g, d_b : out std_logic;
+ d_hsync_state : out hsync_state_type;
+ d_vsync_state : out vsync_state_type;
+ d_state_clk : out std_logic;
+ d_toggle : out std_logic;
+ d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0));
+ end component;
+
+ signal clk_pin : std_logic;
+ signal reset_pin : std_logic;
+ signal r0_pin, r1_pin, r2_pin : std_logic;
+ signal g0_pin, g1_pin, g2_pin : std_logic;
+ signal b0_pin, b1_pin : std_logic;
+ signal hsync_pin : std_logic;
+ signal vsync_pin : std_logic;
+ signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0);
+ signal d_hsync, d_vsync : std_logic;
+ signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ signal d_set_column_counter, d_set_line_counter : std_logic;
+ signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ signal d_set_hsync_counter, d_set_vsync_counter : std_logic;
+ signal d_h_enable : std_logic;
+ signal d_v_enable : std_logic;
+ signal d_r, d_g, d_b : std_logic;
+ signal d_hsync_state : hsync_state_type;
+ signal d_vsync_state : vsync_state_type;
+ signal d_state_clk : std_logic;
+ signal d_toggle : std_logic;
+ signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0);
+
+
+begin
+
+ vga_unit: vga
+ port map (
+ clk_pin => clk_pin,
+ reset_pin => reset_pin,
+ r0_pin => r0_pin,
+ r1_pin => r1_pin,
+ r2_pin => r2_pin,
+ g0_pin => g0_pin,
+ g1_pin => g1_pin,
+ g2_pin => g2_pin,
+ b0_pin => b0_pin,
+ b1_pin => b1_pin,
+ hsync_pin => hsync_pin,
+ vsync_pin => vsync_pin,
+ seven_seg_pin => seven_seg_pin,
+ d_hsync => d_hsync,
+ d_vsync => d_vsync,
+ d_column_counter => d_column_counter,
+ d_line_counter => d_line_counter,
+ d_set_column_counter => d_set_column_counter,
+ d_set_line_counter => d_set_line_counter,
+ d_hsync_counter => d_hsync_counter,
+ d_vsync_counter => d_vsync_counter,
+ d_set_hsync_counter => d_set_hsync_counter,
+ d_set_vsync_counter => d_set_vsync_counter,
+ d_h_enable => d_h_enable,
+ d_v_enable => d_v_enable,
+ d_r => d_r,
+ d_g => d_g,
+ d_b => d_b,
+ d_hsync_state => d_hsync_state,
+ d_vsync_state => d_vsync_state,
+ d_state_clk => d_state_clk,
+ d_toggle => d_toggle,
+ d_toggle_counter => d_toggle_counter);
+
+
+-------------------------------------------------------------------------------
+-- generate simulation clock
+-------------------------------------------------------------------------------
+ CLKGEN : process
+ begin
+ clk_pin <= '1';
+ wait for cc/2;
+ clk_pin <= '0';
+ wait for cc/2;
+ end process CLKGEN;
+
+-------------------------------------------------------------------------------
+-- test the design
+-------------------------------------------------------------------------------
+ TEST_IT : process
+
+ -- wait for n clock cycles
+ procedure icwait(cycles : natural) is
+ begin
+ for i in 1 to cycles loop
+ wait until clk_pin = '1' and clk_pin'event;
+ end loop;
+ end;
+
+ begin
+ -----------------------------------------------------------------------------
+ -- initial reset
+ -----------------------------------------------------------------------------
+ reset_pin <= '0';
+ icwait(10);
+ reset_pin <= '1';
+ icwait(10000000);
+
+ ---------------------------------------------------------------------------
+ -- exit testbench
+ ---------------------------------------------------------------------------
+ assert false
+ report "Test finished"
+ severity error;
+
+ end process test_it;
+
+end behaviour;
+
+
+-------------------------------------------------------------------------------
+-- configuration
+-------------------------------------------------------------------------------
+configuration vga_conf_beh of vga_tb is
+ for behaviour
+ for vga_unit : vga use entity work.vga(behav);
+ end for;
+ end for;
+end vga_conf_beh;
+
+
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Title : vga_control architecture\r
+-- Project : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File : vga_control.vhd\r
+-- Author : Thomas Handl\r
+-- Company : TU Wien\r
+-- Created : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: generation of colors (RGB)\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions :\r
+-- Date Version Author Description\r
+-- 2004-12-15 1.0 handl Created\r
+-- 2006-02-24 2.0 ST revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
+\r
+architecture behav of vga_control is\r
+\r
+\r
+ attribute syn_preserve : boolean;\r
+ attribute syn_preserve of behav : architecture is true;\r
+\r
+\r
+ -- signal and constant declarations \r
+ signal r_next, g_next, b_next : std_logic; -- auxiliary signals for next state logic\r
+ signal toggle_sig : std_logic; -- auxiliary signal to allow read back of toggle\r
+ signal toggle_counter_sig : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal to allow read back of blinker\r
+ signal toggle_next : std_logic; -- auxiliary signal for next state logic\r
+ signal toggle_counter_next : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal for next state logic\r
+-- constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "1100000000010001111011000";
+ constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "0000101101110001101100000";\r
+ -- define half period of toggle frequency in clock ticks\r
+\r
+begin \r
+ -----------------------------------------------------------------------------\r
+ -- draw rectangle on screen\r
+ -----------------------------------------------------------------------------\r
+ \r
+ DRAW_SQUARE_syn: process(clk, reset)\r
+ begin\r
+ if (reset = RES_ACT) then -- draw black screen upon reset\r
+ r <= COLR_OFF;\r
+ g <= COLR_OFF;\r
+ b <= COLR_OFF;\r
+ elsif (clk'event and clk = '1') then -- synchronous capture\r
+ r <= r_next;\r
+ g <= g_next;\r
+ b <= b_next;\r
+ end if;\r
+ end process;\r
+\r
+\r
+ DRAW_SQUARE_next: process (column_counter, line_counter, v_enable, h_enable, toggle_sig)\r
+ begin\r
+ if v_enable = ENABLE and h_enable = ENABLE then \r
+ if (column_counter >= X_MIN and column_counter <= X_MAX and -- if pixel within the rectangle borders\r
+ line_counter >= Y_MIN and line_counter <= Y_MAX) then\r
+ r_next <= toggle_sig; -- ...red\r
+ g_next <= COLR_OFF; -- ...green\r
+ b_next <= not toggle_sig; -- ...blue\r
+ else -- if somewhere else on screen...\r
+ r_next <= COLR_OFF;\r
+ g_next <= COLR_OFF; -- ... draw background color\r
+ b_next <= COLR_OFF;\r
+ end if;\r
+ else -- if out of screen...\r
+ r_next <= COLR_OFF;\r
+ g_next <= COLR_OFF; -- ... do not activate any color\r
+ b_next <= COLR_OFF; -- (black screen)\r
+ end if;\r
+ end process;\r
+\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- control blinking of rectangle\r
+ -----------------------------------------------------------------------------\r
+\r
+ BLINKER_syn: process(clk, reset)\r
+ begin\r
+ if (reset = RES_ACT) then -- asyn reset\r
+ toggle_counter_sig <= (others => '0');\r
+ toggle_sig <= COLR_OFF;\r
+ elsif(clk'event and clk = '1') then -- synchronous capture\r
+ toggle_counter_sig <= toggle_counter_next;\r
+ toggle_sig <= toggle_next;\r
+ end if;\r
+ end process;\r
+\r
+\r
+ BLINKER_next : process(toggle_counter_sig, toggle_sig)\r
+ begin\r
+ if toggle_counter_sig >= HALFPERIOD then -- after half period ...\r
+ toggle_counter_next <= (others => '0'); -- ... clear counter\r
+ toggle_next <= not(toggle_sig); -- ... and toggle colour.\r
+ else -- before half period ...\r
+ toggle_counter_next <= toggle_counter_sig + '1'; -- ... increment counter\r
+ toggle_next <= toggle_sig; -- ... and hold colour\r
+ end if;\r
+ end process;\r
+\r
+\r
+-- assign auxiliary signals to module outputs\r
+toggle <= toggle_sig;\r
+toggle_counter <= toggle_counter_sig;\r
+\r
+end behav;\r
+\r
+-------------------------------------------------------------------------------\r
+-- END ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Title : vga_control architecture\r
+-- Project : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File : vga_control.vhd\r
+-- Author : Thomas Handl\r
+-- Company : TU Wien\r
+-- Created : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: generation of colors (RGB)\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions :\r
+-- Date Version Author Description\r
+-- 2004-12-15 1.0 handl Created\r
+-- 2006-02-24 2.0 ST revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
+\r
+architecture behav of vga_control is\r
+\r
+\r
+ attribute syn_preserve : boolean;\r
+ attribute syn_preserve of behav : architecture is true;\r
+\r
+\r
+ -- signal and constant declarations \r
+ signal r_next, g_next, b_next : std_logic; -- auxiliary signals for next state logic\r
+ signal toggle_sig : std_logic; -- auxiliary signal to allow read back of toggle\r
+ signal toggle_counter_sig : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal to allow read back of blinker\r
+ signal toggle_next : std_logic; -- auxiliary signal for next state logic\r
+ signal toggle_counter_next : std_logic_vector(TOG_CNT_WIDTH-1 downto 0); -- auxiliary signal for next state logic\r
+-- constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "1100000000010001111011000";
+ constant HALFPERIOD : std_logic_vector(TOG_CNT_WIDTH-1 downto 0) := "101101110001101100000";\r
+ -- define half period of toggle frequency in clock ticks\r
+\r
+begin \r
+ -----------------------------------------------------------------------------\r
+ -- draw rectangle on screen\r
+ -----------------------------------------------------------------------------\r
+ \r
+ DRAW_SQUARE_syn: process(clk, reset)\r
+ begin\r
+ if (reset = RES_ACT) then -- draw black screen upon reset\r
+ r <= COLR_OFF;\r
+ g <= COLR_OFF;\r
+ b <= COLR_OFF;\r
+ elsif (clk'event and clk = '1') then -- synchronous capture\r
+ r <= r_next;\r
+ g <= g_next;\r
+ b <= b_next;\r
+ end if;\r
+ end process;\r
+\r
+\r
+ DRAW_SQUARE_next: process (column_counter, line_counter, v_enable, h_enable, toggle_sig)\r
+ begin\r
+ if v_enable = ENABLE and h_enable = ENABLE then \r
+ if (column_counter >= X_MIN and column_counter <= X_MAX and -- if pixel within the rectangle borders\r
+ line_counter >= Y_MIN and line_counter <= Y_MAX) then\r
+ r_next <= toggle_sig; -- ...red\r
+ g_next <= COLR_OFF; -- ...green\r
+ b_next <= not toggle_sig; -- ...blue\r
+ else -- if somewhere else on screen...\r
+ r_next <= COLR_OFF;\r
+ g_next <= COLR_OFF; -- ... draw background color\r
+ b_next <= COLR_OFF;\r
+ end if;\r
+ else -- if out of screen...\r
+ r_next <= COLR_OFF;\r
+ g_next <= COLR_OFF; -- ... do not activate any color\r
+ b_next <= COLR_OFF; -- (black screen)\r
+ end if;\r
+ end process;\r
+\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- control blinking of rectangle\r
+ -----------------------------------------------------------------------------\r
+\r
+ BLINKER_syn: process(clk, reset)\r
+ begin\r
+ if (reset = RES_ACT) then -- asyn reset\r
+ toggle_counter_sig <= (others => '0');\r
+ toggle_sig <= COLR_OFF;\r
+ elsif(clk'event and clk = '1') then -- synchronous capture\r
+ toggle_counter_sig <= toggle_counter_next;\r
+ toggle_sig <= toggle_next;\r
+ end if;\r
+ end process;\r
+\r
+\r
+ BLINKER_next : process(toggle_counter_sig, toggle_sig)\r
+ begin\r
+ if toggle_counter_sig >= HALFPERIOD then -- after half period ...\r
+ toggle_counter_next <= (others => '0'); -- ... clear counter\r
+ toggle_next <= not(toggle_sig); -- ... and toggle colour.\r
+ else -- before half period ...\r
+ toggle_counter_next <= toggle_counter_sig + '1'; -- ... increment counter\r
+ toggle_next <= toggle_sig; -- ... and hold colour\r
+ end if;\r
+ end process;\r
+\r
+\r
+-- assign auxiliary signals to module outputs\r
+toggle <= toggle_sig;\r
+toggle_counter <= toggle_counter_sig;\r
+\r
+end behav;\r
+\r
+-------------------------------------------------------------------------------\r
+-- END ARCHITECTURE\r
+-------------------------------------------------------------------------------\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Title : vga_control entity\r
+-- Project : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File : vga_control_ent.vhd\r
+-- Author : Thomas Handl\r
+-- Company : TU Wien\r
+-- Created : 2004-12-15\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: generation of colors (RGB)\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions :\r
+-- Date Version Author Description\r
+-- 2004-12-15 1.0 handl Created\r
+-- 2006-02-24 2.0 ST revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+use work.vga_pak.all;\r
+\r
+-------------------------------------------------------------------------------\r
+-- ENTITY\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+entity vga_control is\r
+ port(clk : in std_logic;\r
+ reset : in std_logic;\r
+ column_counter : in std_logic_vector(COL_CNT_WIDTH-1 downto 0);\r
+ toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0);\r
+ toggle : out std_logic;\r
+ line_counter : in std_logic_vector(LINE_CNT_WIDTH-1 downto 0);\r
+ v_enable : in std_logic;\r
+ h_enable : in std_logic;\r
+ r, g, b : out std_logic\r
+ );\r
+\r
+end vga_control;\r
+\r
+-------------------------------------------------------------------------------\r
+-- END ENTITY\r
+-------------------------------------------------------------------------------\r
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : vga_driver architecture
+-- Project : LU Digital Design
+-------------------------------------------------------------------------------
+-- File : vga_driver.vhd
+-- Author : Thomas Handl
+-- Company : TU Wien
+-- Created : 2004-12-15
+-- Last update: 2006-01-24
+-------------------------------------------------------------------------------
+-- Description: generate hsync and vsync
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004 TU Wien
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2004-12-15 1.0 handl Created
+-- 2006-01-24 2.0 ST revised
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- LIBRARIES
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use work.vga_pak.all;
+
+-------------------------------------------------------------------------------
+-- ARCHITECTURE
+-------------------------------------------------------------------------------
+
+architecture behav of vga_driver is
+
+ attribute syn_preserve : boolean;
+ attribute syn_preserve of behav : architecture is true;
+
+ constant TIME_A : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100011111";
+ constant TIME_B : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0001011010";
+ constant TIME_BC : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "0010000111";
+ constant TIME_BCD : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1100000111";
+
+ constant TIME_O : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000001000";
+ constant TIME_P : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000000001";
+ constant TIME_PQ : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "0000100001";
+ constant TIME_PQR : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1000000001";
+
+ signal h_sync : std_logic;
+ signal h_sync_next : std_logic;
+
+ signal hsync_state : hsync_state_type;
+ signal hsync_state_next : hsync_state_type;
+
+ signal h_enable_sig : std_logic;
+ signal h_enable_next : std_logic;
+
+ signal set_hsync_counter : std_logic;
+ signal hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ signal hsync_counter_next : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ constant HSYN_CNT_MAX : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0) := "1111111111";
+
+ signal column_counter_sig : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ signal column_counter_next : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ signal set_column_counter : std_logic;
+
+ signal v_sync : std_logic;
+ signal v_sync_next : std_logic;
+
+ signal vsync_state : vsync_state_type;
+ signal vsync_state_next : vsync_state_type;
+
+ signal v_enable_sig : std_logic;
+ signal v_enable_next : std_logic;
+
+ signal set_vsync_counter : std_logic;
+ signal vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ signal vsync_counter_next : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ constant VSYN_CNT_MAX : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0) := "1111111111";
+
+ signal line_counter_sig : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ signal line_counter_next : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ signal set_line_counter : std_logic;
+
+
+
+begin
+
+----------------------------------------------------------------------------
+-- Column_Counter [0..639]: calculates column number for next pixel to be displayed
+----------------------------------------------------------------------------
+
+ COLUMN_COUNT_syn: process(clk, reset, column_counter_next)
+ begin
+ if clk'event and clk = '1' then
+ if reset = RES_ACT then -- synchronous reset
+ column_counter_sig <= (others => '0');
+ else
+ column_counter_sig <= column_counter_next; -- synchronous capture
+ end if;
+ end if;
+ end process;
+
+ COLUMN_COUNT_next: process(set_column_counter, column_counter_sig)
+ begin
+ if set_column_counter = ENABLE then -- reset counter
+ column_counter_next <= (others => '0');
+ else
+ if column_counter_sig < RIGHT_BORDER then
+ column_counter_next <= column_counter_sig + '1'; -- increment column
+ else
+ column_counter_next <= RIGHT_BORDER; -- ... but do not count beyond right border
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------
+-- Line_counter [0..479]: calculates line number for next pixel to be displayed
+----------------------------------------------------------------------------
+
+ LINE_COUNT_syn: process(clk, reset, line_counter_next)
+ begin
+ if clk'event and clk = '1' then
+ if reset = RES_ACT then -- synchronous reset
+ line_counter_sig <= (others => '0');
+ else
+ line_counter_sig <= line_counter_next; -- synchronous capture
+ end if;
+ end if;
+ end process;
+
+ LINE_COUNT_next: process(set_line_counter, line_counter_sig, set_hsync_counter)
+ begin
+ if set_line_counter = ENABLE then -- reset counter
+ line_counter_next <= (others => '0');
+ else
+ if line_counter_sig < BOTTOM_BORDER then
+ if set_hsync_counter = '1' then -- when enabled
+ line_counter_next <= line_counter_sig + '1'; -- ... increment line
+ else
+ line_counter_next <= line_counter_sig;
+ end if;
+ else
+ line_counter_next <= BOTTOM_BORDER; -- ... but do not count below bottom
+ end if;
+ end if;
+ end process;
+
+
+----------------------------------------------------------------------------
+-- Hsync_Counter: generates time base for HSYNC State Machine
+----------------------------------------------------------------------------
+
+ HSYNC_COUNT_syn: process(clk, reset, hsync_counter_next)
+ begin
+ if clk'event and clk = '1' then
+ if reset = RES_ACT then -- synchronous reset
+ hsync_counter <= (others => '0');
+ else
+ hsync_counter <= hsync_counter_next; -- synchronous capture
+ end if;
+ end if;
+ end process;
+
+ HSYNC_COUNT_next: process(set_hsync_counter, hsync_counter)
+ begin
+ if set_hsync_counter = ENABLE then -- reset counter
+ hsync_counter_next <= (others => '0');
+ else
+ if hsync_counter < HSYN_CNT_MAX then
+ hsync_counter_next <= hsync_counter + '1'; -- increment time
+ else
+ hsync_counter_next <= HSYN_CNT_MAX; -- ... but do not count beyond max period
+ end if;
+ end if;
+ end process;
+
+
+----------------------------------------------------------------------------
+-- HSYNC STATE MACHINE: generates hsync signal and controls hsync counter & column counter
+----------------------------------------------------------------------------
+
+ HSYNC_FSM_syn: process (clk, reset) -- synchronous capture
+ begin
+ if clk'event and clk = '1' then
+ if reset = RES_ACT then
+ hsync_state <= RESET_STATE;
+ h_sync <= '1';
+ v_enable_sig <= not(ENABLE);
+ else
+ hsync_state <= hsync_state_next;
+ h_sync <= h_sync_next;
+ v_enable_sig <= v_enable_next;
+ end if;
+ end if;
+ end process;
+
+ HSYNC_FSM_next : process(hsync_state, hsync_counter, h_sync, v_enable_sig) -- next-state logic
+ begin -- default assignments
+ hsync_state_next <= hsync_state; -- ... hold current state
+ h_sync_next <= h_sync; -- ... and values
+ v_enable_next <= v_enable_sig;
+
+ case hsync_state is
+ when RESET_STATE =>
+ h_sync_next <= '0'; -- next signal values are defined here
+ v_enable_next <= not(ENABLE);
+ hsync_state_next <= B_STATE; -- ... as well as state transitions
+ when B_STATE =>
+ h_sync_next <= '0';
+ if hsync_counter = TIME_B then
+ hsync_state_next <= C_STATE;
+ end if;
+ when C_STATE =>
+ h_sync_next <= '1';
+ if hsync_counter = TIME_BC then
+ hsync_state_next <= pre_D_STATE;
+ end if;
+ when pre_D_STATE =>
+ v_enable_next <= ENABLE;
+ hsync_state_next <= D_STATE;
+ when D_STATE =>
+ v_enable_next <= ENABLE;
+ if hsync_counter = TIME_BCD then
+ hsync_state_next <= E_STATE;
+ end if;
+ when E_STATE =>
+ v_enable_next <= not(ENABLE);
+ if hsync_counter = TIME_A then
+ hsync_state_next <= pre_B_STATE;
+ end if;
+ when pre_B_STATE =>
+ h_sync_next <= '0';
+ v_enable_next <= not(ENABLE);
+ hsync_state_next <= B_STATE;
+ when others =>
+ null;
+ end case;
+ end process;
+
+ HSYNC_FSM_out : process(hsync_state) -- output logic
+ begin
+ set_hsync_counter <= not(ENABLE); -- default assignments
+ set_column_counter <= not(ENABLE);
+
+ case hsync_state is
+ when RESET_STATE => -- outputs for each state are defined here
+ set_hsync_counter <= ENABLE;
+ when pre_D_STATE =>
+ set_column_counter <= ENABLE;
+ when pre_B_STATE =>
+ set_hsync_counter <= ENABLE;
+ when others =>
+ null;
+ end case;
+ end process;
+
+
+----------------------------------------------------------------------------
+-- Vsync_Counter: generates time base for VSYNC State Machine
+----------------------------------------------------------------------------
+
+ VSYNC_COUNT_syn: process(clk, reset, vsync_counter_next)
+ begin
+ if clk'event and clk = '1' then
+ if reset = RES_ACT then -- synchronous reset
+ vsync_counter <= (others => '0');
+ else
+ vsync_counter <= vsync_counter_next; -- synchronous capture
+ end if;
+ end if;
+ end process;
+
+ VSYNC_COUNT_next: process(set_vsync_counter, vsync_counter, set_hsync_counter)
+ begin
+ if set_vsync_counter = ENABLE then -- reset counter
+ vsync_counter_next <= (others => '0');
+ else
+ if vsync_counter < VSYN_CNT_MAX then
+ if set_hsync_counter = '1' then -- if enabled
+ vsync_counter_next <= vsync_counter + '1'; -- ... increment time
+ else
+ vsync_counter_next <= vsync_counter;
+ end if;
+ else
+ vsync_counter_next <= VSYN_CNT_MAX; -- ... but do not count beyond max period
+ end if;
+ end if;
+ end process;
+
+
+----------------------------------------------------------------------------
+-- VSYNC STATE MACHINE: generates vsync signal and controls vsync counter & line counter
+----------------------------------------------------------------------------
+
+ VSYNC_FSM_syn : process (clk, reset) -- synchronous capture
+ begin
+ if clk'event and clk = '1' then
+ if reset = RES_ACT then
+ vsync_state <= RESET_STATE;
+ v_sync <= '1';
+ h_enable_sig <= not(ENABLE);
+ else
+ vsync_state <= vsync_state_next;
+ v_sync <= v_sync_next;
+ h_enable_sig <= h_enable_next;
+ end if;
+ end if;
+ end process;
+
+ VSYNC_FSM_next : process(vsync_state, vsync_counter, v_sync, h_enable_sig)
+ begin -- next state logic
+ vsync_state_next <= vsync_state; -- default assignments
+ v_sync_next <= v_sync;
+ h_enable_next <= h_enable_sig;
+
+ case vsync_state is -- state transitions and next signals are defined here
+ when RESET_STATE =>
+ v_sync_next <= '0';
+ h_enable_next <= not(ENABLE);
+ vsync_state_next <= P_STATE;
+ when P_STATE =>
+ v_sync_next <= '0';
+ if vsync_counter = time_p then
+ vsync_state_next <= Q_STATE;
+ end if;
+ when Q_STATE =>
+ v_sync_next <= '1';
+ if vsync_counter = time_pq then
+ vsync_state_next <= pre_R_STATE;
+ end if;
+ when pre_R_STATE =>
+ h_enable_next <= ENABLE;
+ vsync_state_next <= R_STATE;
+ when R_STATE =>
+ h_enable_next <= ENABLE;
+ if vsync_counter = time_pqr then
+ vsync_state_next <= S_STATE;
+ end if;
+ when S_STATE =>
+ h_enable_next <= not(ENABLE);
+ if vsync_counter = time_o then
+ vsync_state_next <= pre_P_STATE;
+ end if;
+ when pre_P_STATE =>
+ v_sync_next <= '0';
+ h_enable_next <= not(ENABLE);
+ vsync_state_next <= P_STATE;
+ when others =>
+ null;
+ end case;
+ end process;
+
+ VSYNC_FSM_out : process(vsync_state)
+ begin -- output logic
+ set_vsync_counter <= not(ENABLE); -- output values for each state defined here
+ set_line_counter <= not(ENABLE);
+
+ case vsync_state is
+ when RESET_STATE =>
+ set_vsync_counter <= ENABLE;
+ when pre_R_STATE =>
+ set_line_counter <= ENABLE;
+ when pre_P_STATE =>
+ set_vsync_counter <= ENABLE;
+ when others =>
+ null;
+ end case;
+ end process;
+
+
+
+-- signal wiring for entity (introduced _sig to allow readback of output signals)
+
+ column_counter <= column_counter_sig;
+ v_enable <= v_enable_sig;
+ line_counter <= line_counter_sig;
+ h_enable <= h_enable_sig;
+
+
+ hsync <= h_sync;
+ vsync <= v_sync;
+
+ -----------------------------------------------------------------------------
+ -- debug signals
+ -----------------------------------------------------------------------------
+ d_hsync_state <= hsync_state;
+ d_vsync_state <= vsync_state;
+ d_hsync_counter <= hsync_counter;
+ d_vsync_counter <= vsync_counter;
+ d_set_hsync_counter <= set_hsync_counter;
+ d_set_vsync_counter <= set_vsync_counter;
+ d_set_column_counter <= set_column_counter;
+ d_set_line_counter <= set_line_counter;
+
+end behav;
+
+-------------------------------------------------------------------------------
+-- END ARCHITECTURE
+-------------------------------------------------------------------------------
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : vga_driver entity
+-- Project : LU Digital Design
+-------------------------------------------------------------------------------
+-- File : vga_driver_ent.vhd
+-- Author : Thomas Handl
+-- Company : TU Wien
+-- Created : 2004-12-15
+-- Last update: 2006-02-24
+-------------------------------------------------------------------------------
+-- Description: generate vsync and hsync
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004 TU Wien
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2004-12-15 1.0 handl Created
+-- 2006-02-24 2.0 ST revised
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- LIBRARIES
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use work.vga_pak.all;
+
+-------------------------------------------------------------------------------
+-- ENTITY
+-------------------------------------------------------------------------------
+
+
+entity vga_driver is
+ port(clk : in std_logic;
+ reset : in std_logic;
+ column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ h_enable : out std_logic;
+ v_enable : out std_logic;
+ hsync, vsync : out std_logic;
+
+ d_hsync_state : out hsync_state_type;
+ d_vsync_state : out vsync_state_type;
+ d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ d_set_hsync_counter : out std_logic;
+ d_set_vsync_counter : out std_logic;
+ d_set_column_counter : out std_logic;
+ d_set_line_counter : out std_logic
+ );
+
+end vga_driver;
+
+-------------------------------------------------------------------------------
+-- END ENTITY
+-------------------------------------------------------------------------------
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : vga entitiy
+-- Project : LU Digital Design
+-------------------------------------------------------------------------------
+-- File : vga_ent.vhd
+-- Author : Thomas Handl
+-- Company : TU Wien
+-- Created : 2004-04-07
+-- Last update: 2006-02-24
+-------------------------------------------------------------------------------
+-- Description: entity of top level module, external pins defined here
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004 TU Wien
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2004-04-07 1.0 handl Created
+-- 2006-02-24 2.0 ST revised
+-------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- LIBRARIES
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use work.vga_pak.all;
+
+
+-------------------------------------------------------------------------------
+-- ENTITY
+-------------------------------------------------------------------------------
+
+entity vga is
+ port(
+-- input pins from PCB board
+ clk_pin : in std_logic; -- clock pin
+ reset_pin : in std_logic; -- reset pins (from switch)
+-- output pins to RGB connector / VGA screen
+ r0_pin, r1_pin, r2_pin : out std_logic; -- to RGB connector "red"
+ g0_pin, g1_pin, g2_pin : out std_logic; -- to RGB connector "green"
+ b0_pin, b1_pin : out std_logic; -- to RGB connector "blue"
+ hsync_pin : out std_logic; -- to RGB connector "Hsync"
+ vsync_pin : out std_logic; -- to RGB connector "Vsync"
+-- output pins to 7-segment display
+ seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
+-- output pins provided for debugging only / logic analyzer
+ d_hsync, d_vsync : out std_logic; -- copy of hsync_pin, vsync_pin
+ d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ d_set_column_counter, d_set_line_counter : out std_logic;
+ d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ d_set_hsync_counter, d_set_vsync_counter : out std_logic;
+ d_h_enable : out std_logic;
+ d_v_enable : out std_logic;
+ d_r, d_g, d_b : out std_logic;
+ d_hsync_state : out hsync_state_type;
+ d_vsync_state : out vsync_state_type;
+ d_state_clk : out std_logic;
+ d_toggle : out std_logic;
+ d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0)
+ );
+
+end vga;
+
+-------------------------------------------------------------------------------
+-- END ENTITY
+-------------------------------------------------------------------------------
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Title : vga package\r
+-- Project : LU Digital Design\r
+-------------------------------------------------------------------------------\r
+-- File : vga_pak.vhd\r
+-- Author : Thomas Handl\r
+-- Company : TU Wien\r
+-- Created : 2004-08-19\r
+-- Last update: 2006-02-24\r
+-------------------------------------------------------------------------------\r
+-- Description: definitions of global constants and enumerated types\r
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2004 TU Wien\r
+-------------------------------------------------------------------------------\r
+-- Revisions :\r
+-- Date Version Author Description\r
+-- 2004-08-19 1.0 handl Created\r
+-- 2006-02-24 2.0 ST revised\r
+-------------------------------------------------------------------------------\r
+\r
+-------------------------------------------------------------------------------\r
+-- LIBRARIES\r
+-------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.std_logic_unsigned.all;\r
+use IEEE.std_logic_arith.all;\r
+\r
+\r
+-------------------------------------------------------------------------------\r
+-- PACKAGE\r
+-------------------------------------------------------------------------------\r
+\r
+package vga_pak is\r
+\r
+ constant RES_ACT : std_logic := '0'; -- define reset active LO\r
+ constant ENABLE : std_logic := '1'; -- define diverse enable HI\r
+ constant COLR_ON : std_logic := '1'; -- define VGA color on as HI\r
+ constant COLR_OFF : std_logic := '0'; -- define VGA color off as LO\r
+ constant SEG_WIDTH : integer := 7; -- display has 7 segments\r
+ constant BCD_WIDTH : integer := 4; -- BCD number has 4 bit\r
+ constant TOG_CNT_WIDTH : integer := 25; -- bitwidth of counter that controls blinking\r
+\r
+ constant COL_CNT_WIDTH : integer := 10; -- width of the column counter\r
+ constant LINE_CNT_WIDTH : integer := 9; -- width of the line counter\r
+ constant HSYN_CNT_WIDTH : integer := 10; -- width of the h-sync counter\r
+ constant VSYN_CNT_WIDTH : integer := 10; -- width of the v-sync counter\r
+\r
+ constant RIGHT_BORDER: std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "1001111111"; -- 640 columns (0...639)\r
+ constant BOTTOM_BORDER: std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "111011111"; -- 480 lines (0...479)\r
+\r
+ -- define coordinates of rectangle\r
+ constant X_MIN : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0001100100"; -- 100\r
+ constant X_MAX : std_logic_vector(COL_CNT_WIDTH-1 downto 0) := "0011001000"; -- 200\r
+ constant Y_MIN : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "001100100";\r
+ constant Y_MAX : std_logic_vector(LINE_CNT_WIDTH-1 downto 0) := "011001000";\r
+\r
+ -- define emumerated types for state machines\r
+ type hsync_state_type is (RESET_STATE, B_STATE, C_STATE, D_STATE, E_STATE,\r
+ pre_D_STATE, pre_B_STATE);\r
+ type vsync_state_type is (RESET_STATE, P_STATE, Q_STATE, R_STATE, S_STATE,\r
+ pre_R_STATE, pre_P_STATE);\r
+ \r
+ -- Definitions for 7-segment display gfedcba\r
+ constant DIGIT_ZERO : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000000";\r
+ constant DIGIT_ONE : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111001";\r
+ constant DIGIT_TWO : std_logic_vector(SEG_WIDTH-1 downto 0) := "0100100";\r
+ constant DIGIT_THREE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110000";\r
+ constant DIGIT_FOUR : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011001";\r
+ constant DIGIT_FIVE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0010010";\r
+ constant DIGIT_SIX : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000010";\r
+ constant DIGIT_SEVEN : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111000";\r
+ constant DIGIT_EIGHT : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000000";\r
+ constant DIGIT_NINE : std_logic_vector(SEG_WIDTH-1 downto 0) := "0011000";\r
+ constant DIGIT_MINUS : std_logic_vector(SEG_WIDTH-1 downto 0) := "0111111";\r
+ constant DIGIT_A : std_logic_vector(SEG_WIDTH-1 downto 0) := "0001000";\r
+ constant DIGIT_B : std_logic_vector(SEG_WIDTH-1 downto 0) := "0000011";\r
+ constant DIGIT_C : std_logic_vector(SEG_WIDTH-1 downto 0) := "0110001";\r
+ constant DIGIT_D : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000010";\r
+ constant DIGIT_E : std_logic_vector(SEG_WIDTH-1 downto 0) := "1001111";\r
+ constant DIGIT_F : std_logic_vector(SEG_WIDTH-1 downto 0) := "1000111";\r
+ constant DIGIT_OFF : std_logic_vector(SEG_WIDTH-1 downto 0) := "1111111";\r
+ \r
+end package;\r
--- /dev/null
+/*\r
+WARNING: Do NOT edit the input and output ports in this file in a text\r
+editor if you plan to continue editing the block that represents it in\r
+the Block Editor! File corruption is VERY likely to occur.\r
+*/\r
+/*\r
+Copyright (C) 1991-2006 Altera Corporation\r
+Your use of Altera Corporation's design tools, logic functions \r
+and other software and tools, and its AMPP partner logic \r
+functions, and any output files any of the foregoing \r
+(including device programming or simulation files), and any \r
+associated documentation or information are expressly subject \r
+to the terms and conditions of the Altera Program License \r
+Subscription Agreement, Altera MegaCore Function License \r
+Agreement, or other applicable license agreement, including, \r
+without limitation, that your use is for the sole purpose of \r
+programming logic devices manufactured by Altera and sold by \r
+Altera or its authorized distributors. Please refer to the \r
+applicable agreement for further details.\r
+*/\r
+(header "graphic" (version "1.3"))\r
+(pin\r
+ (input)\r
+ (rect 248 80 416 96)\r
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))\r
+ (text "board_clk" (rect 5 0 52 12)(font "Arial" ))\r
+ (pt 168 8)\r
+ (drawing\r
+ (line (pt 92 12)(pt 117 12)(line_width 1))\r
+ (line (pt 92 4)(pt 117 4)(line_width 1))\r
+ (line (pt 121 8)(pt 168 8)(line_width 1))\r
+ (line (pt 92 12)(pt 92 4)(line_width 1))\r
+ (line (pt 117 4)(pt 121 8)(line_width 1))\r
+ (line (pt 117 12)(pt 121 8)(line_width 1))\r
+ )\r
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))\r
+ (annotation_block (location)(rect 256 136 304 152))\r
+)\r
+(pin\r
+ (input)\r
+ (rect 544 96 712 112)\r
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))\r
+ (text "reset" (rect 5 0 29 12)(font "Arial" ))\r
+ (pt 168 8)\r
+ (drawing\r
+ (line (pt 92 12)(pt 117 12)(line_width 1))\r
+ (line (pt 92 4)(pt 117 4)(line_width 1))\r
+ (line (pt 121 8)(pt 168 8)(line_width 1))\r
+ (line (pt 92 12)(pt 92 4)(line_width 1))\r
+ (line (pt 117 4)(pt 121 8)(line_width 1))\r
+ (line (pt 117 12)(pt 121 8)(line_width 1))\r
+ )\r
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))\r
+ (annotation_block (location)(rect 512 176 560 192))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 256 1148 272)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_hsync" (rect 90 0 132 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1140 96 1188 112))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 272 1148 288)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_vsync" (rect 90 0 133 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1140 112 1188 128))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 288 1148 304)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_column_counter[9..0]" (rect 90 0 205 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1140 128 1188 272))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 320 1148 336)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_set_column_counter" (rect 90 0 200 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1140 160 1196 176))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 336 1148 352)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_set_line_counter" (rect 90 0 182 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1140 176 1188 192))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 352 1148 368)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_hsync_counter[9..0]" (rect 90 0 200 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1140 192 1196 248))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 368 1142 384)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_vsync_counter[9..0]" (rect 90 0 202 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1134 208 1182 264))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 384 1142 400)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_set_hsync_counter" (rect 90 0 196 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1134 224 1182 240))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 400 1142 416)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_set_vsync_counter" (rect 90 0 197 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1134 240 1182 256))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 448 1142 464)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_r" (rect 90 0 105 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1134 288 1182 304))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 464 1142 480)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_g" (rect 90 0 107 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1134 304 1182 320))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 480 1142 496)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_b" (rect 90 0 107 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1134 320 1182 336))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 496 1142 512)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_hsync_state[0..6]" (rect 90 0 189 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1216 480 1264 584))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 512 1136 528)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_vsync_state[0..6]" (rect 90 0 190 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1256 352 1312 456))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 304 1148 320)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_line_counter[8..0]" (rect 90 0 186 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1140 144 1188 272))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 416 1142 432)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_h_enable" (rect 90 0 145 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1134 256 1182 272))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 432 1142 448)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_v_enable" (rect 90 0 146 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1134 272 1182 288))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 528 1148 544)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_state_clk" (rect 90 0 146 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1404 88 1452 104))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 544 1148 560)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_toggle" (rect 90 0 131 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1468 112 1516 128))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 80 1104 96)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "r0_pin" (rect 90 0 119 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 400 1144 416))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 96 1104 112)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "r1_pin" (rect 90 0 119 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 416 1144 432))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 112 1104 128)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "r2_pin" (rect 90 0 119 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 432 1144 448))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 128 1104 144)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "g0_pin" (rect 90 0 121 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 448 1144 464))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 144 1104 160)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "g1_pin" (rect 90 0 121 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 464 1144 480))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 160 1104 176)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "g2_pin" (rect 90 0 121 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 480 1144 496))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 176 1104 192)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "b0_pin" (rect 90 0 121 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 496 1144 512))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 192 1104 208)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "b1_pin" (rect 90 0 121 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 512 1144 528))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 240 1148 256)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "seven_seg_pin[13..0]" (rect 90 0 196 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1508 472 1572 672))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 560 1148 576)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "d_toggle_counter[24..0]" (rect 90 0 205 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1492 128 1548 288))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 208 1104 224)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "hsync_pin" (rect 90 0 140 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 528 1144 544))\r
+)\r
+(pin\r
+ (output)\r
+ (rect 928 224 1104 240)\r
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))\r
+ (text "vsync_pin" (rect 90 0 141 12)(font "Arial" ))\r
+ (pt 0 8)\r
+ (drawing\r
+ (line (pt 0 8)(pt 52 8)(line_width 1))\r
+ (line (pt 52 4)(pt 78 4)(line_width 1))\r
+ (line (pt 52 12)(pt 78 12)(line_width 1))\r
+ (line (pt 52 12)(pt 52 4)(line_width 1))\r
+ (line (pt 78 4)(pt 82 8)(line_width 1))\r
+ (line (pt 82 8)(pt 78 12)(line_width 1))\r
+ (line (pt 78 12)(pt 82 8)(line_width 1))\r
+ )\r
+ (annotation_block (location)(rect 1096 544 1144 560))\r
+)\r
+(symbol\r
+ (rect 712 56 928 600)\r
+ (text "vga" (rect 5 0 23 12)(font "Arial" ))\r
+ (text "inst" (rect 8 528 25 540)(font "Arial" ))\r
+ (port\r
+ (pt 0 32)\r
+ (input)\r
+ (text "clk_pin" (rect 0 0 34 12)(font "Arial" ))\r
+ (text "clk_pin" (rect 21 27 55 39)(font "Arial" ))\r
+ (line (pt 0 32)(pt 16 32)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 0 48)\r
+ (input)\r
+ (text "reset_pin" (rect 0 0 44 12)(font "Arial" ))\r
+ (text "reset_pin" (rect 21 43 65 55)(font "Arial" ))\r
+ (line (pt 0 48)(pt 16 48)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 32)\r
+ (output)\r
+ (text "r0_pin" (rect 0 0 29 12)(font "Arial" ))\r
+ (text "r0_pin" (rect 166 27 195 39)(font "Arial" ))\r
+ (line (pt 216 32)(pt 200 32)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 48)\r
+ (output)\r
+ (text "r1_pin" (rect 0 0 29 12)(font "Arial" ))\r
+ (text "r1_pin" (rect 166 43 195 55)(font "Arial" ))\r
+ (line (pt 216 48)(pt 200 48)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 64)\r
+ (output)\r
+ (text "r2_pin" (rect 0 0 29 12)(font "Arial" ))\r
+ (text "r2_pin" (rect 166 59 195 71)(font "Arial" ))\r
+ (line (pt 216 64)(pt 200 64)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 80)\r
+ (output)\r
+ (text "g0_pin" (rect 0 0 31 12)(font "Arial" ))\r
+ (text "g0_pin" (rect 164 75 195 87)(font "Arial" ))\r
+ (line (pt 216 80)(pt 200 80)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 96)\r
+ (output)\r
+ (text "g1_pin" (rect 0 0 31 12)(font "Arial" ))\r
+ (text "g1_pin" (rect 164 91 195 103)(font "Arial" ))\r
+ (line (pt 216 96)(pt 200 96)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 112)\r
+ (output)\r
+ (text "g2_pin" (rect 0 0 31 12)(font "Arial" ))\r
+ (text "g2_pin" (rect 164 107 195 119)(font "Arial" ))\r
+ (line (pt 216 112)(pt 200 112)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 128)\r
+ (output)\r
+ (text "b0_pin" (rect 0 0 31 12)(font "Arial" ))\r
+ (text "b0_pin" (rect 164 123 195 135)(font "Arial" ))\r
+ (line (pt 216 128)(pt 200 128)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 144)\r
+ (output)\r
+ (text "b1_pin" (rect 0 0 31 12)(font "Arial" ))\r
+ (text "b1_pin" (rect 164 139 195 151)(font "Arial" ))\r
+ (line (pt 216 144)(pt 200 144)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 160)\r
+ (output)\r
+ (text "hsync_pin" (rect 0 0 50 12)(font "Arial" ))\r
+ (text "hsync_pin" (rect 145 155 195 167)(font "Arial" ))\r
+ (line (pt 216 160)(pt 200 160)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 176)\r
+ (output)\r
+ (text "vsync_pin" (rect 0 0 51 12)(font "Arial" ))\r
+ (text "vsync_pin" (rect 144 171 195 183)(font "Arial" ))\r
+ (line (pt 216 176)(pt 200 176)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 192)\r
+ (output)\r
+ (text "seven_seg_pin[13..0]" (rect 0 0 106 12)(font "Arial" ))\r
+ (text "seven_seg_pin[13..0]" (rect 89 187 195 199)(font "Arial" ))\r
+ (line (pt 216 192)(pt 200 192)(line_width 3))\r
+ )\r
+ (port\r
+ (pt 216 208)\r
+ (output)\r
+ (text "d_hsync" (rect 0 0 42 12)(font "Arial" ))\r
+ (text "d_hsync" (rect 153 203 195 215)(font "Arial" ))\r
+ (line (pt 216 208)(pt 200 208)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 224)\r
+ (output)\r
+ (text "d_vsync" (rect 0 0 43 12)(font "Arial" ))\r
+ (text "d_vsync" (rect 152 219 195 231)(font "Arial" ))\r
+ (line (pt 216 224)(pt 200 224)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 240)\r
+ (output)\r
+ (text "d_column_counter[9..0]" (rect 0 0 115 12)(font "Arial" ))\r
+ (text "d_column_counter[9..0]" (rect 80 235 195 247)(font "Arial" ))\r
+ (line (pt 216 240)(pt 200 240)(line_width 3))\r
+ )\r
+ (port\r
+ (pt 216 256)\r
+ (output)\r
+ (text "d_line_counter[8..0]" (rect 0 0 96 12)(font "Arial" ))\r
+ (text "d_line_counter[8..0]" (rect 99 251 195 263)(font "Arial" ))\r
+ (line (pt 216 256)(pt 200 256)(line_width 3))\r
+ )\r
+ (port\r
+ (pt 216 272)\r
+ (output)\r
+ (text "d_set_column_counter" (rect 0 0 110 12)(font "Arial" ))\r
+ (text "d_set_column_counter" (rect 85 267 195 279)(font "Arial" ))\r
+ (line (pt 216 272)(pt 200 272)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 288)\r
+ (output)\r
+ (text "d_set_line_counter" (rect 0 0 92 12)(font "Arial" ))\r
+ (text "d_set_line_counter" (rect 103 283 195 295)(font "Arial" ))\r
+ (line (pt 216 288)(pt 200 288)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 304)\r
+ (output)\r
+ (text "d_hsync_counter[9..0]" (rect 0 0 110 12)(font "Arial" ))\r
+ (text "d_hsync_counter[9..0]" (rect 85 299 195 311)(font "Arial" ))\r
+ (line (pt 216 304)(pt 200 304)(line_width 3))\r
+ )\r
+ (port\r
+ (pt 216 320)\r
+ (output)\r
+ (text "d_vsync_counter[9..0]" (rect 0 0 112 12)(font "Arial" ))\r
+ (text "d_vsync_counter[9..0]" (rect 83 315 195 327)(font "Arial" ))\r
+ (line (pt 216 320)(pt 200 320)(line_width 3))\r
+ )\r
+ (port\r
+ (pt 216 336)\r
+ (output)\r
+ (text "d_set_hsync_counter" (rect 0 0 106 12)(font "Arial" ))\r
+ (text "d_set_hsync_counter" (rect 89 331 195 343)(font "Arial" ))\r
+ (line (pt 216 336)(pt 200 336)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 352)\r
+ (output)\r
+ (text "d_set_vsync_counter" (rect 0 0 107 12)(font "Arial" ))\r
+ (text "d_set_vsync_counter" (rect 88 347 195 359)(font "Arial" ))\r
+ (line (pt 216 352)(pt 200 352)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 368)\r
+ (output)\r
+ (text "d_h_enable" (rect 0 0 55 12)(font "Arial" ))\r
+ (text "d_h_enable" (rect 140 363 195 375)(font "Arial" ))\r
+ (line (pt 216 368)(pt 200 368)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 384)\r
+ (output)\r
+ (text "d_v_enable" (rect 0 0 56 12)(font "Arial" ))\r
+ (text "d_v_enable" (rect 139 379 195 391)(font "Arial" ))\r
+ (line (pt 216 384)(pt 200 384)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 400)\r
+ (output)\r
+ (text "d_r" (rect 0 0 15 12)(font "Arial" ))\r
+ (text "d_r" (rect 180 395 195 407)(font "Arial" ))\r
+ (line (pt 216 400)(pt 200 400)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 416)\r
+ (output)\r
+ (text "d_g" (rect 0 0 17 12)(font "Arial" ))\r
+ (text "d_g" (rect 178 411 195 423)(font "Arial" ))\r
+ (line (pt 216 416)(pt 200 416)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 432)\r
+ (output)\r
+ (text "d_b" (rect 0 0 17 12)(font "Arial" ))\r
+ (text "d_b" (rect 178 427 195 439)(font "Arial" ))\r
+ (line (pt 216 432)(pt 200 432)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 448)\r
+ (output)\r
+ (text "d_hsync_state[0..6]" (rect 0 0 99 12)(font "Arial" ))\r
+ (text "d_hsync_state[0..6]" (rect 96 443 195 455)(font "Arial" ))\r
+ (line (pt 216 448)(pt 200 448)(line_width 3))\r
+ )\r
+ (port\r
+ (pt 216 464)\r
+ (output)\r
+ (text "d_vsync_state[0..6]" (rect 0 0 100 12)(font "Arial" ))\r
+ (text "d_vsync_state[0..6]" (rect 95 459 195 471)(font "Arial" ))\r
+ (line (pt 216 464)(pt 200 464)(line_width 3))\r
+ )\r
+ (port\r
+ (pt 216 480)\r
+ (output)\r
+ (text "d_state_clk" (rect 0 0 56 12)(font "Arial" ))\r
+ (text "d_state_clk" (rect 139 475 195 487)(font "Arial" ))\r
+ (line (pt 216 480)(pt 200 480)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 496)\r
+ (output)\r
+ (text "d_toggle" (rect 0 0 41 12)(font "Arial" ))\r
+ (text "d_toggle" (rect 154 491 195 503)(font "Arial" ))\r
+ (line (pt 216 496)(pt 200 496)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 216 512)\r
+ (output)\r
+ (text "d_toggle_counter[24..0]" (rect 0 0 115 12)(font "Arial" ))\r
+ (text "d_toggle_counter[24..0]" (rect 80 507 195 519)(font "Arial" ))\r
+ (line (pt 216 512)(pt 200 512)(line_width 3))\r
+ )\r
+ (drawing\r
+ (rectangle (rect 16 16 200 528)(line_width 1))\r
+ )\r
+)\r
+(symbol\r
+ (rect 416 56 512 152)\r
+ (text "vpll" (rect 5 0 22 12)(font "Arial" ))\r
+ (text "inst1" (rect 8 80 31 92)(font "Arial" ))\r
+ (port\r
+ (pt 0 32)\r
+ (input)\r
+ (text "inclk0" (rect 0 0 28 12)(font "Arial" ))\r
+ (text "inclk0" (rect 21 27 49 39)(font "Arial" ))\r
+ (line (pt 0 32)(pt 16 32)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 96 32)\r
+ (output)\r
+ (text "c0" (rect 0 0 11 12)(font "Arial" ))\r
+ (text "c0" (rect 64 27 75 39)(font "Arial" ))\r
+ (line (pt 96 32)(pt 80 32)(line_width 1))\r
+ )\r
+ (drawing\r
+ (rectangle (rect 16 16 80 80)(line_width 1))\r
+ )\r
+)\r
+(connector\r
+ (pt 512 88)\r
+ (pt 712 88)\r
+)\r
--- /dev/null
+# Copyright (C) 1991-2006 Altera Corporation\r
+# Your use of Altera Corporation's design tools, logic functions \r
+# and other software and tools, and its AMPP partner logic \r
+# functions, and any output files any of the foregoing \r
+# (including device programming or simulation files), and any \r
+# associated documentation or information are expressly subject \r
+# to the terms and conditions of the Altera Program License \r
+# Subscription Agreement, Altera MegaCore Function License \r
+# Agreement, or other applicable license agreement, including, \r
+# without limitation, that your use is for the sole purpose of \r
+# programming logic devices manufactured by Altera and sold by \r
+# Altera or its authorized distributors. Please refer to the \r
+# applicable agreement for further details.\r
+\r
+# Quartus II: Generate Tcl File for Project\r
+# File: vga_pll.tcl\r
+# Generated on: Fri Sep 29 09:31:24 2006\r
+\r
+# Load Quartus II Tcl Project package\r
+package require ::quartus::project\r
+package require ::quartus::flow\r
+\r
+set need_to_close_project 0\r
+set make_assignments 1\r
+\r
+# Check that the right project is open\r
+if {[is_project_open]} {\r
+ if {[string compare $quartus(project) "vga_pll"]} {\r
+ puts "Project vga_pll is not open"\r
+ set make_assignments 0\r
+ }\r
+} else {\r
+ # Only open if not already open\r
+ if {[project_exists vga_pll]} {\r
+ project_open -cmp vga_pll vga_pll\r
+ } else {\r
+ project_new -cmp vga_pll vga_pll\r
+ }\r
+ set need_to_close_project 1\r
+}\r
+\r
+# Make assignments\r
+if {$make_assignments} {\r
+ catch { set_global_assignment -name FAMILY Stratix } result\r
+ catch { set_global_assignment -name DEVICE EP1S25F672C6 } result\r
+ catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result\r
+ catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result\r
+ catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result\r
+ catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result\r
+ catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result\r
+ catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result\r
+ catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result\r
+ catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result\r
+ catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result\r
+ catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result\r
+ catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result\r
+ catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result\r
+ catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result\r
+\r
+ set_location_assignment PIN_E24 -to b0_pin\r
+ set_location_assignment PIN_T6 -to b1_pin\r
+ set_location_assignment PIN_N3 -to board_clk\r
+ set_location_assignment PIN_E23 -to g0_pin\r
+ set_location_assignment PIN_T5 -to g1_pin\r
+ set_location_assignment PIN_T24 -to g2_pin\r
+ set_location_assignment PIN_F1 -to hsync_pin\r
+ set_location_assignment PIN_E22 -to r0_pin\r
+ set_location_assignment PIN_T4 -to r1_pin\r
+ set_location_assignment PIN_T7 -to r2_pin\r
+ set_location_assignment PIN_A5 -to reset\r
+ set_location_assignment PIN_F2 -to vsync_pin\r
+ set_location_assignment PIN_Y5 -to d_hsync_state[0]\r
+ set_location_assignment PIN_F19 -to d_hsync_state[1]\r
+ set_location_assignment PIN_F17 -to d_hsync_state[2]\r
+ set_location_assignment PIN_Y2 -to d_hsync_state[3]\r
+ set_location_assignment PIN_F10 -to d_hsync_state[4]\r
+ set_location_assignment PIN_F9 -to d_hsync_state[5]\r
+ set_location_assignment PIN_F6 -to d_hsync_state[6]\r
+ set_location_assignment PIN_H4 -to d_hsync_counter[0]\r
+ set_location_assignment PIN_G25 -to d_hsync_counter[7]\r
+ set_location_assignment PIN_G22 -to d_hsync_counter[8]\r
+ set_location_assignment PIN_G18 -to d_hsync_counter[9]\r
+ set_location_assignment PIN_F5 -to d_vsync_state[0]\r
+ set_location_assignment PIN_F4 -to d_vsync_state[1]\r
+ set_location_assignment PIN_F3 -to d_vsync_state[2]\r
+ set_location_assignment PIN_M19 -to d_vsync_state[3]\r
+ set_location_assignment PIN_M18 -to d_vsync_state[4]\r
+ set_location_assignment PIN_M7 -to d_vsync_state[5]\r
+ set_location_assignment PIN_M4 -to d_vsync_state[6]\r
+ set_location_assignment PIN_G9 -to d_vsync_counter[0]\r
+ set_location_assignment PIN_G6 -to d_vsync_counter[7]\r
+ set_location_assignment PIN_G4 -to d_vsync_counter[8]\r
+ set_location_assignment PIN_G2 -to d_vsync_counter[9]\r
+ set_location_assignment PIN_K6 -to d_line_counter[0]\r
+ set_location_assignment PIN_K4 -to d_line_counter[1]\r
+ set_location_assignment PIN_J22 -to d_line_counter[2]\r
+ set_location_assignment PIN_M9 -to d_line_counter[3]\r
+ set_location_assignment PIN_M8 -to d_line_counter[4]\r
+ set_location_assignment PIN_M6 -to d_line_counter[5]\r
+ set_location_assignment PIN_M5 -to d_line_counter[6]\r
+ set_location_assignment PIN_L24 -to d_line_counter[7]\r
+ set_location_assignment PIN_L25 -to d_line_counter[8]\r
+ set_location_assignment PIN_L23 -to d_column_counter[0]\r
+ set_location_assignment PIN_L22 -to d_column_counter[1]\r
+ set_location_assignment PIN_L21 -to d_column_counter[2]\r
+ set_location_assignment PIN_L20 -to d_column_counter[3]\r
+ set_location_assignment PIN_L6 -to d_column_counter[4]\r
+ set_location_assignment PIN_L4 -to d_column_counter[5]\r
+ set_location_assignment PIN_L2 -to d_column_counter[6]\r
+ set_location_assignment PIN_K23 -to d_column_counter[7]\r
+ set_location_assignment PIN_K19 -to d_column_counter[8]\r
+ set_location_assignment PIN_K5 -to d_column_counter[9]\r
+ set_location_assignment PIN_L7 -to d_hsync\r
+ set_location_assignment PIN_L5 -to d_vsync\r
+ set_location_assignment PIN_F26 -to d_set_hsync_counter\r
+ set_location_assignment PIN_F24 -to d_set_vsync_counter\r
+ set_location_assignment PIN_F21 -to d_set_line_counter\r
+ set_location_assignment PIN_Y23 -to d_set_column_counter\r
+ set_location_assignment PIN_L3 -to d_r\r
+ set_location_assignment PIN_K24 -to d_g\r
+ set_location_assignment PIN_K20 -to d_b\r
+ set_location_assignment PIN_H18 -to d_v_enable\r
+ set_location_assignment PIN_J21 -to d_h_enable\r
+ set_location_assignment PIN_R8 -to seven_seg_pin[0]\r
+ set_location_assignment PIN_R9 -to seven_seg_pin[1]\r
+ set_location_assignment PIN_R19 -to seven_seg_pin[2]\r
+ set_location_assignment PIN_R20 -to seven_seg_pin[3]\r
+ set_location_assignment PIN_R21 -to seven_seg_pin[4]\r
+ set_location_assignment PIN_R22 -to seven_seg_pin[5]\r
+ set_location_assignment PIN_R23 -to seven_seg_pin[6]\r
+ set_location_assignment PIN_Y11 -to seven_seg_pin[7]\r
+ set_location_assignment PIN_N7 -to seven_seg_pin[8]\r
+ set_location_assignment PIN_N8 -to seven_seg_pin[9]\r
+ set_location_assignment PIN_R4 -to seven_seg_pin[10]\r
+ set_location_assignment PIN_R6 -to seven_seg_pin[11]\r
+ set_location_assignment PIN_AA11 -to seven_seg_pin[12]\r
+ set_location_assignment PIN_T2 -to seven_seg_pin[13]\r
+ set_location_assignment PIN_K3 -to d_state_clk\r
+ set_location_assignment PIN_H3 -to d_toggle\r
+ set_location_assignment PIN_H26 -to d_toggle_counter[0]\r
+ set_location_assignment PIN_G24 -to d_toggle_counter[15]\r
+ set_location_assignment PIN_G23 -to d_toggle_counter[16]\r
+ set_location_assignment PIN_G21 -to d_toggle_counter[17]\r
+ set_location_assignment PIN_G20 -to d_toggle_counter[18]\r
+ set_location_assignment PIN_G5 -to d_toggle_counter[19]\r
+ set_location_assignment PIN_G3 -to d_toggle_counter[20]\r
+ set_location_assignment PIN_G1 -to d_toggle_counter[21]\r
+ set_location_assignment PIN_F25 -to d_toggle_counter[22]\r
+ set_location_assignment PIN_F23 -to d_toggle_counter[23]\r
+ set_location_assignment PIN_T19 -to d_toggle_counter[24]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin\r
+\r
+\r
+ # Commit assignments\r
+ export_assignments\r
+\r
+execute_flow -compile\r
+\r
+ # Close project\r
+ if {$need_to_close_project} {\r
+ project_close\r
+ }\r
+}\r
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : vga testbench
+-- Project :
+-------------------------------------------------------------------------------
+-- File : vga_tb.vhd
+-- Author : Thomas Handl
+-- Company : TU Wien
+-- Created : 2004-04-07
+-- Last update: 2006-09-29
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004 TU Wien
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2004-04-07 1.0 handl Created
+-------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- LIBRARIES
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use work.vga_pak.all;
+
+
+-------------------------------------------------------------------------------
+-- ENTITY
+-------------------------------------------------------------------------------
+entity vga_pos_tb is
+
+end vga_pos_tb;
+
+
+-------------------------------------------------------------------------------
+-- ARCHITECTURE
+-------------------------------------------------------------------------------
+architecture structure of vga_pos_tb is
+
+ constant cc : time := 39.7 ns; -- test clock period
+
+ component vga
+ port (
+ clk_pin : in std_logic;
+ reset_pin : in std_logic;
+ r0_pin, r1_pin, r2_pin : out std_logic;
+ g0_pin, g1_pin, g2_pin : out std_logic;
+ b0_pin, b1_pin : out std_logic;
+ hsync_pin : out std_logic;
+ vsync_pin : out std_logic;
+ seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
+ d_hsync, d_vsync : out std_logic;
+ d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ d_set_column_counter, d_set_line_counter : out std_logic;
+ d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ d_set_hsync_counter, d_set_vsync_counter : out std_logic;
+ d_h_enable : out std_logic;
+ d_v_enable : out std_logic;
+ d_r, d_g, d_b : out std_logic;
+ d_hsync_state : out std_logic_vector(0 to 6);
+ d_vsync_state : out std_logic_vector(0 to 6);
+ d_state_clk : out std_logic;
+ d_toggle : out std_logic;
+ d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0));
+ end component;
+
+ signal clk_pin : std_logic;
+ signal reset_pin : std_logic;
+ signal r0_pin, r1_pin, r2_pin : std_logic;
+ signal g0_pin, g1_pin, g2_pin : std_logic;
+ signal b0_pin, b1_pin : std_logic;
+ signal hsync_pin : std_logic;
+ signal vsync_pin : std_logic;
+ signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0);
+ signal d_hsync, d_vsync : std_logic;
+ signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ signal d_set_column_counter, d_set_line_counter : std_logic;
+ signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ signal d_set_hsync_counter, d_set_vsync_counter : std_logic;
+ signal d_h_enable : std_logic;
+ signal d_v_enable : std_logic;
+ signal d_r, d_g, d_b : std_logic;
+ signal d_hsync_state : std_logic_vector(0 to 6);
+ signal d_vsync_state : std_logic_vector(0 to 6);
+ signal d_state_clk : std_logic;
+ signal d_toggle : std_logic;
+ signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0);
+ signal clk : std_logic;
+
+begin
+
+ vga_unit: vga
+ port map (
+ clk_pin => clk_pin,
+ reset_pin => reset_pin,
+ r0_pin => r0_pin,
+ r1_pin => r1_pin,
+ r2_pin => r2_pin,
+ g0_pin => g0_pin,
+ g1_pin => g1_pin,
+ g2_pin => g2_pin,
+ b0_pin => b0_pin,
+ b1_pin => b1_pin,
+ hsync_pin => hsync_pin,
+ vsync_pin => vsync_pin,
+ seven_seg_pin => seven_seg_pin,
+ d_hsync => d_hsync,
+ d_vsync => d_vsync,
+ d_column_counter => d_column_counter,
+ d_line_counter => d_line_counter,
+ d_set_column_counter => d_set_column_counter,
+ d_set_line_counter => d_set_line_counter,
+ d_hsync_counter => d_hsync_counter,
+ d_vsync_counter => d_vsync_counter,
+ d_set_hsync_counter => d_set_hsync_counter,
+ d_set_vsync_counter => d_set_vsync_counter,
+ d_h_enable => d_h_enable,
+ d_v_enable => d_v_enable,
+ d_r => d_r,
+ d_g => d_g,
+ d_b => d_b,
+ d_hsync_state => d_hsync_state,
+ d_vsync_state => d_vsync_state,
+ d_state_clk => d_state_clk,
+ d_toggle => d_toggle,
+ d_toggle_counter => d_toggle_counter);
+
+
+
+-------------------------------------------------------------------------------
+-- generate simulation clock
+-------------------------------------------------------------------------------
+ CLKGEN : process
+ begin
+ clk <= '1';
+ wait for cc/2;
+ clk <= '0';
+ wait for cc/2;
+ end process CLKGEN;
+
+-------------------------------------------------------------------------------
+-- test the design
+-------------------------------------------------------------------------------
+ TEST_IT : process
+
+ -- wait for n clock cycles
+ procedure icwait(cycles : natural) is
+ begin
+ for i in 1 to cycles loop
+ wait until clk = '1' and clk'event;
+ end loop;
+ end;
+
+ begin
+ -----------------------------------------------------------------------------
+ -- initial reset
+ -----------------------------------------------------------------------------
+ reset_pin <= '0';
+ icwait(10);
+ reset_pin <= '1';
+ icwait(1000000000);
+
+ ---------------------------------------------------------------------------
+ -- exit testbench
+ ---------------------------------------------------------------------------
+ assert false
+ report "Test finished"
+ severity error;
+
+ end process test_it;
+
+ clk_pin <= clk;
+
+end structure;
+
+-------------------------------------------------------------------------------
+-- configuration
+-------------------------------------------------------------------------------
+configuration vga_conf_pos of vga_pos_tb is
+ for structure
+ for vga_unit : vga use entity work.vga(structure);
+ end for;
+ end for;
+end vga_conf_pos;
+
+
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : vga testbench
+-- Project :
+-------------------------------------------------------------------------------
+-- File : vga_tb.vhd
+-- Author : Thomas Handl
+-- Company : TU Wien
+-- Created : 2004-04-07
+-- Last update: 2006-09-29
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004 TU Wien
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2004-04-07 1.0 handl Created
+-------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- LIBRARIES
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use work.vga_pak.all;
+
+
+-------------------------------------------------------------------------------
+-- ENTITY
+-------------------------------------------------------------------------------
+entity vga_pre_tb is
+
+end vga_pre_tb;
+
+
+-------------------------------------------------------------------------------
+-- ARCHITECTURE
+-------------------------------------------------------------------------------
+architecture structure of vga_pre_tb is
+
+ constant cc : time := 39.7 ns; -- test clock period
+
+ component vga
+ port (
+ clk_pin : in std_logic;
+ reset_pin : in std_logic;
+ r0_pin, r1_pin, r2_pin : out std_logic;
+ g0_pin, g1_pin, g2_pin : out std_logic;
+ b0_pin, b1_pin : out std_logic;
+ hsync_pin : out std_logic;
+ vsync_pin : out std_logic;
+ seven_seg_pin : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
+ d_hsync, d_vsync : out std_logic;
+ d_column_counter : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ d_line_counter : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ d_set_column_counter, d_set_line_counter : out std_logic;
+ d_hsync_counter : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ d_vsync_counter : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ d_set_hsync_counter, d_set_vsync_counter : out std_logic;
+ d_h_enable : out std_logic;
+ d_v_enable : out std_logic;
+ d_r, d_g, d_b : out std_logic;
+ d_hsync_state : out std_logic_vector(0 to 6);
+ d_vsync_state : out std_logic_vector(0 to 6);
+ d_state_clk : out std_logic;
+ d_toggle : out std_logic;
+ d_toggle_counter : out std_logic_vector(TOG_CNT_WIDTH-1 downto 0));
+ end component;
+
+ signal clk_pin : std_logic;
+ signal reset_pin : std_logic;
+ signal r0_pin, r1_pin, r2_pin : std_logic;
+ signal g0_pin, g1_pin, g2_pin : std_logic;
+ signal b0_pin, b1_pin : std_logic;
+ signal hsync_pin : std_logic;
+ signal vsync_pin : std_logic;
+ signal seven_seg_pin : std_logic_vector(2*SEG_WIDTH-1 downto 0);
+ signal d_hsync, d_vsync : std_logic;
+ signal d_column_counter : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
+ signal d_line_counter : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
+ signal d_set_column_counter, d_set_line_counter : std_logic;
+ signal d_hsync_counter : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
+ signal d_vsync_counter : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
+ signal d_set_hsync_counter, d_set_vsync_counter : std_logic;
+ signal d_h_enable : std_logic;
+ signal d_v_enable : std_logic;
+ signal d_r, d_g, d_b : std_logic;
+ signal d_hsync_state : std_logic_vector(0 to 6);
+ signal d_vsync_state : std_logic_vector(0 to 6);
+ signal d_state_clk : std_logic;
+ signal d_toggle : std_logic;
+ signal d_toggle_counter : std_logic_vector(TOG_CNT_WIDTH-1 downto 0);
+ signal clk : std_logic;
+
+begin
+
+ vga_unit: vga
+ port map (
+ clk_pin => clk_pin,
+ reset_pin => reset_pin,
+ r0_pin => r0_pin,
+ r1_pin => r1_pin,
+ r2_pin => r2_pin,
+ g0_pin => g0_pin,
+ g1_pin => g1_pin,
+ g2_pin => g2_pin,
+ b0_pin => b0_pin,
+ b1_pin => b1_pin,
+ hsync_pin => hsync_pin,
+ vsync_pin => vsync_pin,
+ seven_seg_pin => seven_seg_pin,
+ d_hsync => d_hsync,
+ d_vsync => d_vsync,
+ d_column_counter => d_column_counter,
+ d_line_counter => d_line_counter,
+ d_set_column_counter => d_set_column_counter,
+ d_set_line_counter => d_set_line_counter,
+ d_hsync_counter => d_hsync_counter,
+ d_vsync_counter => d_vsync_counter,
+ d_set_hsync_counter => d_set_hsync_counter,
+ d_set_vsync_counter => d_set_vsync_counter,
+ d_h_enable => d_h_enable,
+ d_v_enable => d_v_enable,
+ d_r => d_r,
+ d_g => d_g,
+ d_b => d_b,
+ d_hsync_state => d_hsync_state,
+ d_vsync_state => d_vsync_state,
+ d_state_clk => d_state_clk,
+ d_toggle => d_toggle,
+ d_toggle_counter => d_toggle_counter);
+
+
+-------------------------------------------------------------------------------
+-- generate simulation clock
+-------------------------------------------------------------------------------
+ CLKGEN : process
+ begin
+ clk <= '1';
+ wait for cc/2;
+ clk <= '0';
+ wait for cc/2;
+ end process CLKGEN;
+
+-------------------------------------------------------------------------------
+-- test the design
+-------------------------------------------------------------------------------
+ TEST_IT : process
+
+ -- wait for n clock cycles
+ procedure icwait(cycles : natural) is
+ begin
+ for i in 1 to cycles loop
+ wait until clk = '1' and clk'event;
+ end loop;
+ end;
+
+ begin
+ -----------------------------------------------------------------------------
+ -- initial reset
+ -----------------------------------------------------------------------------
+ reset_pin <= '0';
+ icwait(10);
+ reset_pin <= '1';
+ icwait(10000000);
+
+ ---------------------------------------------------------------------------
+ -- exit testbench
+ ---------------------------------------------------------------------------
+ assert false
+ report "Test finished"
+ severity error;
+
+ end process test_it;
+
+ clk_pin <= clk;
+
+end structure;
+
+-------------------------------------------------------------------------------
+-- configuration
+-------------------------------------------------------------------------------
+configuration vga_conf_pre of vga_pre_tb is
+ for structure
+ for vga_unit : vga use entity work.vga(beh);
+ end for;
+ end for;
+end vga_conf_pre;
+
+
+
--- /dev/null
+/*\r
+WARNING: Do NOT edit the input and output ports in this file in a text\r
+editor if you plan to continue editing the block that represents it in\r
+the Block Editor! File corruption is VERY likely to occur.\r
+*/\r
+/*\r
+Copyright (C) 1991-2004 Altera Corporation\r
+Any megafunction design, and related netlist (encrypted or decrypted),\r
+support information, device programming or simulation file, and any other\r
+associated documentation or information provided by Altera or a partner\r
+under Altera's Megafunction Partnership Program may be used only\r
+to program PLD devices (but not masked PLD devices) from Altera. Any\r
+other use of such megafunction design, netlist, support information,\r
+device programming or simulation file, or any other related documentation\r
+or information is prohibited for any other purpose, including, but not\r
+limited to modification, reverse engineering, de-compiling, or use with\r
+any other silicon devices, unless such use is explicitly licensed under\r
+a separate agreement with Altera or a megafunction partner. Title to the\r
+intellectual property, including patents, copyrights, trademarks, trade\r
+secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+support information, device programming or simulation file, or any other\r
+related documentation or information provided by Altera or a megafunction\r
+partner, remains with Altera, the megafunction partner, or their respective\r
+licensors. No other licenses, including any licenses needed under any third\r
+party's intellectual property, are provided herein.\r
+*/\r
+(header "symbol" (version "1.1"))\r
+(symbol\r
+ (rect 16 16 112 112)\r
+ (text "vpll" (rect 5 0 22 12)(font "Arial" ))\r
+ (text "inst" (rect 8 80 25 92)(font "Arial" ))\r
+ (port\r
+ (pt 0 32)\r
+ (input)\r
+ (text "inclk0" (rect 0 0 28 12)(font "Arial" ))\r
+ (text "inclk0" (rect 21 27 49 39)(font "Arial" ))\r
+ (line (pt 0 32)(pt 16 32)(line_width 1))\r
+ )\r
+ (port\r
+ (pt 96 32)\r
+ (output)\r
+ (text "c0" (rect 0 0 11 12)(font "Arial" ))\r
+ (text "c0" (rect 64 27 75 39)(font "Arial" ))\r
+ (line (pt 96 32)(pt 80 32)(line_width 1))\r
+ )\r
+ (drawing\r
+ (rectangle (rect 16 16 80 80)(line_width 1))\r
+ )\r
+)\r
--- /dev/null
+-- megafunction wizard: %ALTPLL%\r
+-- GENERATION: STANDARD\r
+-- VERSION: WM1.0\r
+-- MODULE: altpll \r
+\r
+-- ============================================================\r
+-- File Name: vpll.vhd\r
+-- Megafunction Name(s):\r
+-- altpll\r
+-- ============================================================\r
+-- ************************************************************\r
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+--\r
+-- 4.1 Build 181 06/29/2004 SJ Full Version\r
+-- ************************************************************\r
+\r
+\r
+--Copyright (C) 1991-2004 Altera Corporation\r
+--Any megafunction design, and related netlist (encrypted or decrypted),\r
+--support information, device programming or simulation file, and any other\r
+--associated documentation or information provided by Altera or a partner\r
+--under Altera's Megafunction Partnership Program may be used only\r
+--to program PLD devices (but not masked PLD devices) from Altera. Any\r
+--other use of such megafunction design, netlist, support information,\r
+--device programming or simulation file, or any other related documentation\r
+--or information is prohibited for any other purpose, including, but not\r
+--limited to modification, reverse engineering, de-compiling, or use with\r
+--any other silicon devices, unless such use is explicitly licensed under\r
+--a separate agreement with Altera or a megafunction partner. Title to the\r
+--intellectual property, including patents, copyrights, trademarks, trade\r
+--secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+--support information, device programming or simulation file, or any other\r
+--related documentation or information provided by Altera or a megafunction\r
+--partner, remains with Altera, the megafunction partner, or their respective\r
+--licensors. No other licenses, including any licenses needed under any third\r
+--party's intellectual property, are provided herein.\r
+\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.all;\r
+\r
+LIBRARY altera_mf;\r
+USE altera_mf.altera_mf_components.all;\r
+\r
+ENTITY vpll IS\r
+ PORT\r
+ (\r
+ inclk0 : IN STD_LOGIC := '0';\r
+-- pllena : IN STD_LOGIC := '1';\r
+-- areset : IN STD_LOGIC := '0';\r
+ c0 : OUT STD_LOGIC \r
+-- locked : OUT STD_LOGIC \r
+ );\r
+END vpll;\r
+\r
+\r
+ARCHITECTURE SYN OF vpll IS\r
+\r
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+ SIGNAL sub_wire1 : STD_LOGIC ;\r
+ SIGNAL sub_wire2 : STD_LOGIC ;\r
+ SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+ SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire6 : STD_LOGIC ;\r
+ SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);\r
+ SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0);\r
+\r
+signal pllena_int : std_logic;\r
+signal areset_int : std_logic;\r
+signal locked : std_logic;\r
+\r
+ COMPONENT altpll\r
+ GENERIC (\r
+ bandwidth_type : STRING;\r
+ clk0_duty_cycle : NATURAL;\r
+ lpm_type : STRING;\r
+ clk0_multiply_by : NATURAL;\r
+ invalid_lock_multiplier : NATURAL;\r
+ inclk0_input_frequency : NATURAL;\r
+ gate_lock_signal : STRING;\r
+ clk0_divide_by : NATURAL;\r
+ pll_type : STRING;\r
+ valid_lock_multiplier : NATURAL;\r
+ clk0_time_delay : STRING;\r
+ spread_frequency : NATURAL;\r
+ intended_device_family : STRING;\r
+ operation_mode : STRING;\r
+ compensate_clock : STRING;\r
+ clk0_phase_shift : STRING\r
+ );\r
+ PORT (\r
+ clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);\r
+ pllena : IN STD_LOGIC ;\r
+ extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0);\r
+ locked : OUT STD_LOGIC ;\r
+ areset : IN STD_LOGIC ;\r
+ clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+BEGIN\r
+ sub_wire3_bv(0 DOWNTO 0) <= "0";\r
+ sub_wire3 <= To_stdlogicvector(sub_wire3_bv);\r
+ sub_wire5_bv(0 DOWNTO 0) <= "0";\r
+ sub_wire5 <= NOT(To_stdlogicvector(sub_wire5_bv));\r
+ sub_wire1 <= sub_wire0(0);\r
+ c0 <= sub_wire1;\r
+ locked <= sub_wire2;\r
+ sub_wire4 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0);\r
+ sub_wire6 <= inclk0;\r
+ sub_wire7 <= sub_wire3(0 DOWNTO 0) & sub_wire6;\r
+ sub_wire8 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0);\r
+\r
+areset_int <= '0';\r
+pllena_int <= '1';\r
+\r
+ altpll_component : altpll\r
+ GENERIC MAP (\r
+ bandwidth_type => "AUTO",\r
+ clk0_duty_cycle => 50,\r
+ lpm_type => "altpll",\r
+ clk0_multiply_by => 5435,\r
+ invalid_lock_multiplier => 5,\r
+ inclk0_input_frequency => 30003,\r
+ gate_lock_signal => "NO",\r
+ clk0_divide_by => 6666,\r
+ pll_type => "AUTO",\r
+ valid_lock_multiplier => 1,\r
+ clk0_time_delay => "0",\r
+ spread_frequency => 0,\r
+ intended_device_family => "Stratix",\r
+ operation_mode => "NORMAL",\r
+ compensate_clock => "CLK0",\r
+ clk0_phase_shift => "0"\r
+ )\r
+ PORT MAP (\r
+ clkena => sub_wire4,\r
+ inclk => sub_wire7,\r
+ pllena => pllena_int,\r
+ extclkena => sub_wire8,\r
+ areset => areset_int,\r
+ clk => sub_wire0,\r
+ locked => sub_wire2\r
+ );\r
+\r
+\r
+\r
+END SYN;\r
+\r
+-- ============================================================\r
+-- CNX file retrieval info\r
+-- ============================================================\r
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"\r
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"\r
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"\r
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"\r
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"\r
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"\r
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"\r
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"\r
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"\r
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"\r
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"\r
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"\r
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330"\r
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"\r
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"\r
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"\r
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"\r
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"\r
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"\r
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"\r
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970"\r
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"\r
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330"\r
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175"\r
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"\r
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix"\r
+-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"\r
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"\r
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"\r
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"\r
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9"\r
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"\r
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"\r
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435"\r
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"\r
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003"\r
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"\r
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666"\r
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"\r
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"\r
+-- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"\r
+-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"\r
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"\r
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"\r
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"\r
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"\r
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"\r
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"\r
+-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"\r
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"\r
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"\r
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"\r
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0\r
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\r
+-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0\r
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE\r
--- /dev/null
+#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
+#install: /opt/synplify/fpga_c200906
+#OS: Linux
+#Hostname: ti12
+
+#Implementation: rev_1
+
+#Wed Oct 21 17:21:16 2009
+
+$ Start of Compile
+#Wed Oct 21 17:21:16 2009
+
+Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+
+@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
+VHDL syntax check successful!
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav
+@E: CD395 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd":50:73:50:95|Constant width 21 does not match context width 25
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav
+1 errors during synthesis
+@END
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:21:16 2009
+
+###########################################################]
--- /dev/null
+#### START OF AREA REPORT #####[
+
+Part: EP1S25FC672-6 (Altera)
+
+-------------------------------------------------------------------
+######## Utilization report for Top level view: vga ########
+===================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name Total elements Utilization Notes
+------------------------------------------------------
+REGISTERS 88 100 %
+======================================================
+Total SEQUENTIAL ATOMS in the block vga: 88 (29.43 % Utilization)
+
+
+COMBINATIONAL ATOMS
+*******************
+
+Name Total elements Utilization Notes
+------------------------------------------------------------
+ATOMS 72 100 %
+ARITHMETIC MODE 53 100 %
+============================================================
+Total COMBINATIONAL ATOMS in the block vga: 125 (41.81 % Utilization)
+
+
+RAMS
+****
+
+Name Total elements Number of bits Utilization Notes
+-------------------------------------------------------------------------
+SYNC RAMS 0 0 0 %
+LPMs 0 0 0 %
+=========================================================================
+Total RAMS in the block vga: 0 (0.00 % Utilization)
+
+
+DSPs
+****
+
+Name Total elements Utilization Notes
+-------------------------------------------------
+MACs 0 0 %
+=================================================
+Total DSPs in the block vga: 0 (0.00 % Utilization)
+
+
+Black Boxes
+***********
+
+Name Total elements Utilization Notes
+--------------------------------------------------------
+BLACK BOXES 0 0 %
+========================================================
+Total Black Boxes in the block vga: 0 (0.00 % Utilization)
+
+-----------------------------------------------------------------
+######## Utilization report for cell: vga_control ########
+Instance path: vga.vga_control
+=================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name Total elements Utilization Notes
+------------------------------------------------------
+REGISTERS 29 33 %
+======================================================
+Total SEQUENTIAL ATOMS in the block vga.vga_control: 29 (9.70 % Utilization)
+
+
+COMBINATIONAL ATOMS
+*******************
+
+Name Total elements Utilization Notes
+------------------------------------------------------------
+ATOMS 19 26.4 %
+ARITHMETIC MODE 19 35.8 %
+============================================================
+Total COMBINATIONAL ATOMS in the block vga.vga_control: 38 (12.71 % Utilization)
+
+
+RAMS
+****
+
+Name Total elements Number of bits Utilization Notes
+-------------------------------------------------------------------------
+SYNC RAMS 0 0 0 %
+LPMs 0 0 0 %
+=========================================================================
+Total RAMS in the block vga.vga_control: 0 (0.00 % Utilization)
+
+
+DSPs
+****
+
+Name Total elements Utilization Notes
+-------------------------------------------------
+MACs 0 0 %
+=================================================
+Total DSPs in the block vga.vga_control: 0 (0.00 % Utilization)
+
+
+Black Boxes
+***********
+
+Name Total elements Utilization Notes
+--------------------------------------------------------
+BLACK BOXES 0 0 %
+========================================================
+Total Black Boxes in the block vga.vga_control: 0 (0.00 % Utilization)
+
+----------------------------------------------------------------
+######## Utilization report for cell: vga_driver ########
+Instance path: vga.vga_driver
+================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name Total elements Utilization Notes
+------------------------------------------------------
+REGISTERS 57 64.8 %
+======================================================
+Total SEQUENTIAL ATOMS in the block vga.vga_driver: 57 (19.06 % Utilization)
+
+
+COMBINATIONAL ATOMS
+*******************
+
+Name Total elements Utilization Notes
+------------------------------------------------------------
+ATOMS 53 73.6 %
+ARITHMETIC MODE 34 64.2 %
+============================================================
+Total COMBINATIONAL ATOMS in the block vga.vga_driver: 87 (29.10 % Utilization)
+
+
+RAMS
+****
+
+Name Total elements Number of bits Utilization Notes
+-------------------------------------------------------------------------
+SYNC RAMS 0 0 0 %
+LPMs 0 0 0 %
+=========================================================================
+Total RAMS in the block vga.vga_driver: 0 (0.00 % Utilization)
+
+
+DSPs
+****
+
+Name Total elements Utilization Notes
+-------------------------------------------------
+MACs 0 0 %
+=================================================
+Total DSPs in the block vga.vga_driver: 0 (0.00 % Utilization)
+
+
+Black Boxes
+***********
+
+Name Total elements Utilization Notes
+--------------------------------------------------------
+BLACK BOXES 0 0 %
+========================================================
+Total Black Boxes in the block vga.vga_driver: 0 (0.00 % Utilization)
+
+
+##### END OF AREA REPORT #####]
+
--- /dev/null
+<html><head><title></title></head><body><a name=TopSummary>
+#### START OF AREA REPORT #####[<pre>
+Part: EP1S25FC672-6 (Altera)
+
+Click here to go to specific block report:
+<a href="rpt_vga_areasrr.htm#vga"><h5 align="center">vga</h5></a><br><a href="rpt_vga_areasrr.htm#vga.vga_driver"><h5 align="center">vga_driver</h5></a><br><a href="rpt_vga_areasrr.htm#vga.vga_control"><h5 align="center">vga_control</h5></a><br><a name=vga>
+-------------------------------------------------------------------
+######## Utilization report for Top level view: vga ########
+===================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name Total elements Utilization Notes
+------------------------------------------------------
+REGISTERS 88 100 %
+======================================================
+Total SEQUENTIAL ATOMS in the block vga: 88 (29.43 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+COMBINATIONAL ATOMS
+*******************
+
+Name Total elements Utilization Notes
+------------------------------------------------------------
+ATOMS 72 100 %
+ARITHMETIC MODE 53 100 %
+============================================================
+Total COMBINATIONAL ATOMS in the block vga: 125 (41.81 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+RAMS
+****
+
+Name Total elements Number of bits Utilization Notes
+-------------------------------------------------------------------------
+SYNC RAMS 0 0 0 %
+LPMs 0 0 0 %
+=========================================================================
+Total RAMS in the block vga: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+DSPs
+****
+
+Name Total elements Utilization Notes
+-------------------------------------------------
+MACs 0 0 %
+=================================================
+Total DSPs in the block vga: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+Black Boxes
+***********
+
+Name Total elements Utilization Notes
+--------------------------------------------------------
+BLACK BOXES 0 0 %
+========================================================
+Total Black Boxes in the block vga: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+<a name=vga.vga_control>
+-----------------------------------------------------------------
+######## Utilization report for cell: vga_control ########
+Instance path: vga.vga_control
+=================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name Total elements Utilization Notes
+------------------------------------------------------
+REGISTERS 29 33 %
+======================================================
+Total SEQUENTIAL ATOMS in the block vga.vga_control: 29 (9.70 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+COMBINATIONAL ATOMS
+*******************
+
+Name Total elements Utilization Notes
+------------------------------------------------------------
+ATOMS 19 26.4 %
+ARITHMETIC MODE 19 35.8 %
+============================================================
+Total COMBINATIONAL ATOMS in the block vga.vga_control: 38 (12.71 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+RAMS
+****
+
+Name Total elements Number of bits Utilization Notes
+-------------------------------------------------------------------------
+SYNC RAMS 0 0 0 %
+LPMs 0 0 0 %
+=========================================================================
+Total RAMS in the block vga.vga_control: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+DSPs
+****
+
+Name Total elements Utilization Notes
+-------------------------------------------------
+MACs 0 0 %
+=================================================
+Total DSPs in the block vga.vga_control: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+Black Boxes
+***********
+
+Name Total elements Utilization Notes
+--------------------------------------------------------
+BLACK BOXES 0 0 %
+========================================================
+Total Black Boxes in the block vga.vga_control: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+<a name=vga.vga_driver>
+----------------------------------------------------------------
+######## Utilization report for cell: vga_driver ########
+Instance path: vga.vga_driver
+================================================================
+
+SEQUENTIAL ATOMS
+****************
+
+Name Total elements Utilization Notes
+------------------------------------------------------
+REGISTERS 57 64.8 %
+======================================================
+Total SEQUENTIAL ATOMS in the block vga.vga_driver: 57 (19.06 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+COMBINATIONAL ATOMS
+*******************
+
+Name Total elements Utilization Notes
+------------------------------------------------------------
+ATOMS 53 73.6 %
+ARITHMETIC MODE 34 64.2 %
+============================================================
+Total COMBINATIONAL ATOMS in the block vga.vga_driver: 87 (29.10 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+RAMS
+****
+
+Name Total elements Number of bits Utilization Notes
+-------------------------------------------------------------------------
+SYNC RAMS 0 0 0 %
+LPMs 0 0 0 %
+=========================================================================
+Total RAMS in the block vga.vga_driver: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+DSPs
+****
+
+Name Total elements Utilization Notes
+-------------------------------------------------
+MACs 0 0 %
+=================================================
+Total DSPs in the block vga.vga_driver: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+Black Boxes
+***********
+
+Name Total elements Utilization Notes
+--------------------------------------------------------
+BLACK BOXES 0 0 %
+========================================================
+Total Black Boxes in the block vga.vga_driver: 0 (0.00 % Utilization)
+
+<a href="#TopSummary"><h5 align="right">Top</h5></a>
+
+##### END OF AREA REPORT #####]
+</a></body></html>
--- /dev/null
+#-- Synplicity, Inc.
+#-- Version C-2009.06
+#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/run_options.txt
+#-- Written on Wed Oct 21 17:26:30 2009
+
+
+#project files
+add_file -vhdl -lib work "../src/vga_pak.vhd"
+add_file -vhdl -lib work "../src/vga_ent.vhd"
+add_file -vhdl -lib work "../src/vga_arc.vhd"
+add_file -vhdl -lib work "../src/board_driver_ent.vhd"
+add_file -vhdl -lib work "../src/board_driver_arc.vhd"
+add_file -vhdl -lib work "../src/vga_control_ent.vhd"
+add_file -vhdl -lib work "../src/vga_control_arc.vhd"
+add_file -vhdl -lib work "../src/vga_driver_ent.vhd"
+add_file -vhdl -lib work "../src/vga_driver_arc.vhd"
+
+
+#implementation: "rev_1"
+impl -add rev_1 -type fpga
+
+#device options
+set_option -technology STRATIX
+set_option -part EP1S25
+set_option -package FC672
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "vga"
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# mapper_options
+set_option -frequency 25.175
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# Altera STRATIX
+set_option -run_prop_extract 1
+set_option -maxfan 500
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -quartus_version 9.0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./rev_1/vga.vqm"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "rev_1"
--- /dev/null
+#-- Synplicity, Inc.
+#-- Version C-2009.06
+#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/scratchproject.prs
+#-- Written on Wed Oct 21 17:26:30 2009
+
+
+#project files
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd"
+add_file -vhdl -lib work "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd"
+
+
+#implementation: "rev_1"
+impl -add /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1 -type fpga
+
+#device options
+set_option -technology STRATIX
+set_option -part EP1S25
+set_option -package FC672
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "vga"
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# mapper_options
+set_option -frequency 25.175
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# Altera STRATIX
+set_option -run_prop_extract 1
+set_option -maxfan 500
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -quartus_version 9.0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "rev_1"
--- /dev/null
+Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+Product Version C-2009.06
+@N: MF249 |Running in 32-bit mode.
+@N: MF257 |Gated clock conversion enabled
+@N|Running in logic synthesis mode without enhanced optimization
+@W|Ignoring synthesis effort setting for the design. This is not supported by the current technology.
+
+@N: BN225 |Writing default property annotation file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.sap.
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:26:30 2009
+
+###########################################################]
--- /dev/null
+<table border="0" cellpadding="0" cellspacing="2">
+<tr>
+<td nowrap class="content" valign="top">
+<body bgcolor="#e0e0ff">
+<font size=3><b>Log File Links:</b><br></font>
+<br><b>rev_1</b><br>
+<dt><a href="/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/rpt_vga.areasrr:@XP_FILE" target="srrFrame">Hierarchical Area Report (/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/rpt_vga)</a> (17:24 21-Oct)</dt><br>
+<br><br><a href="/homes/burban/stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br>
--- /dev/null
+@TM:1256138598
+@N: :"":0:0:0:-1|Running in logic synthesis mode without enhanced optimization
+@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
+@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
+@N: MF257 :"":0:0:0:-1|Gated clock conversion enabled
+@N: MF276 :"":0:0:0:-1|Gated clock conversion enabled, but no gated clocks found in design
+@N: MF333 :"":0:0:0:-1|Generated clock conversion enabled, but no generated clocks found in design
+@N: MT320 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
+@N: MT322 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
+@TM:1256138589
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|M
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|M
+@TM:1256138598
+@N: :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":158:4:158:5|M
+@N: :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":267:4:267:5|M
+@TM:1256138589
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|M
+@N: :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|M
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|M
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|M
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|M
+@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|M
--- /dev/null
+@P: Part : EP1S25FC672-6
+@P: Worst Slack : 34.458
+@P: vga|clk_pin - Estimated Frequency : 190.0 MHz
+@P: vga|clk_pin - Requested Frequency : 25.2 MHz
+@P: vga|clk_pin - Estimated Period : 5.264
+@P: vga|clk_pin - Requested Period : 39.722
+@P: vga|clk_pin - Slack : 34.458
+@P: vga Part : ep1s25fc672-6
+@P: vga I/O ATOMs : 117
+@P: vga Total LUTs: : 179 of 25660 ( 0%)
+@P: vga Logic resources : 181 ATOMs of 25660 ( 0%)
+@P: vga DSP Blocks : 0 (0 nine-bit DSP elements)
+@P: CPU Time : 0h:00m:04s
--- /dev/null
+source "/opt/synplify/fpga_c200906/lib/altera/quartus_cons.tcl"
+syn_create_and_open_prj vga
+source $::quartus(binpath)/prj_asd_import.tcl
+syn_create_and_open_csf vga
+syn_handle_cons vga
--- /dev/null
+<table border="0" cellpadding="0" cellspacing="2">
+<tr>
+<td nowrap class="content" valign="top">
+<body bgcolor="#e0e0ff">
+<font size=3><b>Log File Links:</b><br></font>
+<br><b>rev_1</b><br>
+<br><br><a href="/homes/burban/stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br>
--- /dev/null
+<table border="0" cellpadding="0" cellspacing="2">
+<tr>
+<td nowrap class="content" valign="top">
+<body bgcolor="#e0e0ff">
+<font size=3><b>Log File Links:</b><br></font>
+<br><b>rev_1</b><br>
+<dt><a href="/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/rpt_vga.areasrr:@XP_FILE" target="srrFrame">Hierarchical Area Report (/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/rpt_vga)</a> (17:26 21-Oct)</dt><br>
+<br><br><a href="/homes/burban/stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br>
--- /dev/null
+<html><body><samp><pre>
+<!@TC:1256138796>
+#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
+#install: /opt/synplify/fpga_c200906
+#OS: Linux
+#Hostname: ti12
+
+#Implementation: rev_1
+
+#Wed Oct 21 17:26:30 2009
+
+<a name=compilerReport1>$ Start of Compile</a>
+#Wed Oct 21 17:26:30 2009
+
+Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/opt/synplify/fpga_c200906/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1256138796> | Setting time resolution to ns
+@N: : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd:38:7:38:10:@N::@XP_MSG">vga_ent.vhd(38)</a><!@TM:1256138796> | Top entity is set to vga.
+VHDL syntax check successful!
+
+Compiler output is up to date. No re-compile necessary
+
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd:38:7:38:10:@N:CD630:@XP_MSG">vga_ent.vhd(38)</a><!@TM:1256138796> | Synthesizing work.vga.behav
+@N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd:60:24:60:26:@N:CD231:@XP_MSG">vga_pak.vhd(60)</a><!@TM:1256138796> | Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd:62:24:62:26:@N:CD231:@XP_MSG">vga_pak.vhd(62)</a><!@TM:1256138796> | Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd:37:7:37:18:@N:CD630:@XP_MSG">vga_control_ent.vhd(37)</a><!@TM:1256138796> | Synthesizing work.vga_control.behav
+Post processing for work.vga_control.behav
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd:37:7:37:17:@N:CD630:@XP_MSG">vga_driver_ent.vhd(37)</a><!@TM:1256138796> | Synthesizing work.vga_driver.behav
+@N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd:60:24:60:26:@N:CD231:@XP_MSG">vga_pak.vhd(60)</a><!@TM:1256138796> | Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd:62:24:62:26:@N:CD231:@XP_MSG">vga_pak.vhd(62)</a><!@TM:1256138796> | Using onehot encoding for type vsync_state_type (reset_state="1000000")
+Post processing for work.vga_driver.behav
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd:36:7:36:19:@N:CD630:@XP_MSG">board_driver_ent.vhd(36)</a><!@TM:1256138796> | Synthesizing work.board_driver.behav
+Post processing for work.board_driver.behav
+Post processing for work.vga.behav
+@END
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:26:30 2009
+
+###########################################################]
+<a name=mapperReport2>Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53</a>
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+Product Version C-2009.06
+@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1256138796> | Running in 32-bit mode.
+@N:<a href="@N:MF257:@XP_HELP">MF257</a> : <!@TM:1256138796> | Gated clock conversion enabled
+@N: : <!@TM:1256138796> | Running in logic synthesis mode without enhanced optimization
+
+Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
+Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
+
+Available hyper_sources - for debug and ip models
+ None Found
+
+Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+@N: : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd:267:4:267:6:@N::@XP_MSG">vga_driver_arc.vhd(267)</a><!@TM:1256138796> | Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
+@N: : <a href="/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd:158:4:158:6:@N::@XP_MSG">vga_driver_arc.vhd(158)</a><!@TM:1256138796> | Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
+
+
+
+#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
+
+======================================================================================
+ Instance:Pin Generated Clock Optimization Status
+======================================================================================
+
+
+##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
+
+Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 68MB)
+
+
+Writing Analyst data base /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.srm
+Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Writing Verilog Netlist and constraint files
+Writing .vqm output for Quartus
+Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.xrf
+Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Writing VHDL Simulation files
+Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+@N:<a href="@N:MF276:@XP_HELP">MF276</a> : <!@TM:1256138796> | Gated clock conversion enabled, but no gated clocks found in design
+Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+@N:<a href="@N:MF333:@XP_HELP">MF333</a> : <!@TM:1256138796> | Generated clock conversion enabled, but no generated clocks found in design
+Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Found clock vga|clk_pin with period 39.72ns
+
+
+<a name=timingReport3>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Wed Oct 21 17:26:36 2009
+#
+
+
+Top view: vga
+Requested Frequency: 25.2 MHz
+Wire load mode: top
+Paths requested: 5
+Constraint File(s):
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1256138796> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1256138796> | Clock constraints cover only FF-to-FF paths associated with the clock..
+
+
+
+<a name=performanceSummary4>Performance Summary </a>
+*******************
+
+
+Worst slack in design: 34.458
+
+ Requested Estimated Requested Estimated Clock Clock
+Starting Clock Frequency Frequency Period Period Slack Type Group
+----------------------------------------------------------------------------------------------------------------------
+vga|clk_pin 25.2 MHz 190.0 MHz 39.722 5.264 34.458 inferred Inferred_clkgroup_0
+======================================================================================================================
+
+
+
+
+
+<a name=clockRelationships5>Clock Relationships</a>
+*******************
+
+Clocks | rise to rise | fall to fall | rise to fall | fall to rise
+-----------------------------------------------------------------------------------------------------------------
+Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
+-----------------------------------------------------------------------------------------------------------------
+vga|clk_pin vga|clk_pin | 39.722 34.458 | No paths - | No paths - | No paths -
+=================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+ 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo6>Interface Information </a>
+*********************
+
+ No IO constraint found
+
+
+
+====================================
+<a name=clockReport7>Detailed Report for Clock: vga|clk_pin</a>
+====================================
+
+
+
+<a name=startingSlack8>Starting Points with Worst Slack</a>
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[6] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_6 0.176 34.458
+dly_counter[0] vga|clk_pin stratix_lcell_ff regout dly_counter[0] 0.176 34.465
+dly_counter[1] vga|clk_pin stratix_lcell_ff regout dly_counter[1] 0.176 34.584
+vga_control_unit.toggle_counter_sig[5] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_5 0.176 34.585
+vga_driver_unit.vsync_counter[6] vga|clk_pin stratix_lcell_ff regout vsync_counter_6 0.176 34.836
+vga_driver_unit.vsync_counter[7] vga|clk_pin stratix_lcell_ff regout vsync_counter_7 0.176 34.865
+vga_control_unit.toggle_counter_sig[8] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_8 0.176 34.921
+vga_driver_unit.vsync_counter[3] vga|clk_pin stratix_lcell_ff regout vsync_counter_3 0.176 34.992
+vga_driver_unit.vsync_counter[8] vga|clk_pin stratix_lcell_ff regout vsync_counter_8 0.176 34.992
+vga_control_unit.toggle_counter_sig[9] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_9 0.176 35.048
+======================================================================================================================================
+
+
+<a name=endingSlack9>Ending Points with Worst Slack</a>
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[0] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[1] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[2] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[3] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[4] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[5] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[6] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[7] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[8] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[9] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+====================================================================================================================================
+
+
+
+<a name=worstPaths10>Worst Path Information</a>
+<a href="/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.srr:fp:13902:16758:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 39.722
+ - Setup time: 0.792
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 38.930
+
+ - Propagation time: 4.472
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (critical) : 34.458
+
+ Number of logic level(s): 6
+ Starting point: vga_control_unit.toggle_counter_sig[6] / regout
+ Ending point: vga_control_unit.toggle_counter_sig[0] / sclr
+ The start point is clocked by vga|clk_pin [rising] on pin clk
+ The end point is clocked by vga|clk_pin [rising] on pin clk
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[6] stratix_lcell_ff regout Out 0.176 0.176 -
+toggle_counter_sig_6 Net - - 1.000 - 4
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6 stratix_lcell dataa In - 1.176 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6 stratix_lcell combout Out 0.459 1.635 -
+un1_toggle_counter_siglt6 Net - - 0.376 - 1
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9 stratix_lcell datad In - 2.011 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9 stratix_lcell combout Out 0.087 2.098 -
+un1_toggle_counter_siglto9 Net - - 0.376 - 1
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12 stratix_lcell datad In - 2.474 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12 stratix_lcell combout Out 0.087 2.561 -
+un1_toggle_counter_siglto12 Net - - 0.376 - 1
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15 stratix_lcell datad In - 2.938 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15 stratix_lcell combout Out 0.087 3.025 -
+un1_toggle_counter_siglto15 Net - - 0.376 - 1
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18 stratix_lcell datad In - 3.401 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18 stratix_lcell combout Out 0.087 3.488 -
+un1_toggle_counter_siglto18 Net - - 0.376 - 1
+vga_control_unit.toggle_sig_0_0_0_g1 stratix_lcell datad In - 3.864 -
+vga_control_unit.toggle_sig_0_0_0_g1 stratix_lcell combout Out 0.087 3.951 -
+toggle_sig_0_0_0_g1 Net - - 0.521 - 22(6)
+vga_control_unit.toggle_counter_sig[0] stratix_lcell_ff sclr In - 4.472 -
+=======================================================================================================================================
+Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.264 is 1.862(35.4%) logic and 3.402(64.6%) route.
+Fanout format: logic fanout (physical fanout)
+Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
+*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
+
+
+
+##### END OF TIMING REPORT #####]
+
+<a name=areaReport11>##### START OF AREA REPORT #####[</a>
+Design view:work.vga(behav)
+Selecting part EP1S25F672C6
+@N:<a href="@N:FA174:@XP_HELP">FA174</a> : <!@TM:1256138796> | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
+
+I/O ATOMs: 117
+
+Total LUTs: 179 of 25660 ( 0%)
+Logic resources: 181 ATOMs of 25660 ( 0%)
+
+Number of I/O registers
+ Output DDRs :0
+
+ATOM count by mode:
+ normal: 128
+ arithmetic: 53
+
+DSP Blocks: 0 (0 nine-bit DSP elements).
+DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
+ShiftTap: 0 (0 registers)
+MRAM: 0 (0% of 2)
+M4Ks: 0 (0% of 138)
+M512s: 0 (0% of 224)
+Total ESB: 0 bits
+
+ATOMs using regout pin: 88
+ also using enable pin: 12
+ also using combout pin: 1
+ATOMs using combout pin: 91
+Number of Inputs on ATOMs: 760
+Number of Nets: 54954
+
+##### END OF AREA REPORT #####]
+
+Mapper successful!
+Process took 0h:00m:05s realtime, 0h:00m:04s cputime
+# Wed Oct 21 17:26:36 2009
+
+###########################################################]
--- /dev/null
+<table border="0" cellpadding="0" cellspacing="2">
+<tr>
+<td nowrap class="content" valign="top">
+<body bgcolor="#e0e0ff">
+<dl>
+<font size=3><b>rev_1 (vga)</b><br></font>
+<b><a href="vga_srr.htm#compilerReport1" target="srrFrame">Compiler Report</a></b><br>
+<b><a href="vga_srr.htm#mapperReport2" target="srrFrame">Mapper Report</a></b><br>
+<b><a href="vga_srr.htm#timingReport3" target="srrFrame">Timing Report</a></b><br>
+<a href="vga_srr.htm#performanceSummary4" target="srrFrame">Performance Summary</a><br>
+<a href="vga_srr.htm#clockRelationships5" target="srrFrame">Clock Relationships</a><br>
+<a href="vga_srr.htm#interfaceInfo6" target="srrFrame">Interface Information</a><br>
+<a href="vga_srr.htm#clockReport7" target="srrFrame">Detailed Report for Clock: vga|clk_pin</a><br>
+ <a href="vga_srr.htm#startingSlack8" target="srrFrame">Starting Points with Worst Slack</a><br>
+ <a href="vga_srr.htm#endingSlack9" target="srrFrame">Ending Points with Worst Slack</a><br>
+ <a href="vga_srr.htm#worstPaths10" target="srrFrame">Worst Path Information</a><br>
+<b><a href="vga_srr.htm#areaReport11" target="srrFrame">Resource Utilization</a></b><br>
--- /dev/null
+#
+# Synplicity Verification Interface File
+# Generated using Synplify-pro
+#
+# Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+
+# All rights reserved
+#
+
+# Set logfile options
+vif_set_result_file vga.vlf
+
+# Set technology for TCL script
+vif_set_technology -architecture FPGA -vendor Altera
+
+# RTL and technology files
+vif_add_file -original -vhdl -lib work ../../src/vga_pak.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_ent.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_arc.vhd
+vif_add_file -original -vhdl -lib work ../../src/board_driver_ent.vhd
+vif_add_file -original -vhdl -lib work ../../src/board_driver_arc.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_control_ent.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_control_arc.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_driver_ent.vhd
+vif_add_file -original -vhdl -lib work ../../src/vga_driver_arc.vhd
+vif_set_top_module -original -top vga
+
+vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
+vif_add_file -translated -verilog vga.vqm
+vif_set_top_module -translated -top vga
+# Read FSM encoding
+
+# Memory map points
+
+# SRL map points
+
+# Compiler constant registers
+
+# Compiler constant latches
+
+# Compiler RTL sequential redundancies
+
+# RTL sequential redundancies
+
+# Technology sequential redundancies
+
+# Inversion map points
+
+# Port mappping and directions
+
+# Black box mapping
+
+
+# Other sequential cells, including multidimensional arrays
+vif_set_map_point -register -original vga_driver_unit/hsync_state[0] -translated vga_driver_unit/hsync_state_0_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[1] -translated vga_driver_unit/hsync_state_1_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[2] -translated vga_driver_unit/hsync_state_2_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[3] -translated vga_driver_unit/hsync_state_3_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[4] -translated vga_driver_unit/hsync_state_4_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[5] -translated vga_driver_unit/hsync_state_5_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[2] -translated vga_driver_unit/vsync_state_2_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[3] -translated vga_driver_unit/vsync_state_3_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[4] -translated vga_driver_unit/vsync_state_4_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[5] -translated vga_driver_unit/vsync_state_5_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[0] -translated vga_driver_unit/line_counter_sig_0_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[1] -translated vga_driver_unit/line_counter_sig_1_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[2] -translated vga_driver_unit/line_counter_sig_2_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[3] -translated vga_driver_unit/line_counter_sig_3_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[4] -translated vga_driver_unit/line_counter_sig_4_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[5] -translated vga_driver_unit/line_counter_sig_5_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[6] -translated vga_driver_unit/line_counter_sig_6_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[7] -translated vga_driver_unit/line_counter_sig_7_
+vif_set_map_point -register -original vga_driver_unit/line_counter_sig[8] -translated vga_driver_unit/line_counter_sig_8_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[6] -translated vga_driver_unit/vsync_state_6_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[1] -translated vga_driver_unit/vsync_state_1_
+vif_set_map_point -register -original vga_driver_unit/vsync_state[0] -translated vga_driver_unit/vsync_state_0_
+vif_set_map_point -register -original vga_driver_unit/hsync_state[6] -translated vga_driver_unit/hsync_state_6_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[0] -translated vga_driver_unit/column_counter_sig_0_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[1] -translated vga_driver_unit/column_counter_sig_1_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[2] -translated vga_driver_unit/column_counter_sig_2_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[3] -translated vga_driver_unit/column_counter_sig_3_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[4] -translated vga_driver_unit/column_counter_sig_4_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[5] -translated vga_driver_unit/column_counter_sig_5_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[6] -translated vga_driver_unit/column_counter_sig_6_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[7] -translated vga_driver_unit/column_counter_sig_7_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[8] -translated vga_driver_unit/column_counter_sig_8_
+vif_set_map_point -register -original vga_driver_unit/column_counter_sig[9] -translated vga_driver_unit/column_counter_sig_9_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[9] -translated vga_driver_unit/vsync_counter_9_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[8] -translated vga_driver_unit/vsync_counter_8_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[7] -translated vga_driver_unit/vsync_counter_7_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[6] -translated vga_driver_unit/vsync_counter_6_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[5] -translated vga_driver_unit/vsync_counter_5_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[4] -translated vga_driver_unit/vsync_counter_4_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[3] -translated vga_driver_unit/vsync_counter_3_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[2] -translated vga_driver_unit/vsync_counter_2_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[1] -translated vga_driver_unit/vsync_counter_1_
+vif_set_map_point -register -original vga_driver_unit/vsync_counter[0] -translated vga_driver_unit/vsync_counter_0_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[9] -translated vga_driver_unit/hsync_counter_9_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[8] -translated vga_driver_unit/hsync_counter_8_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[7] -translated vga_driver_unit/hsync_counter_7_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[6] -translated vga_driver_unit/hsync_counter_6_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[5] -translated vga_driver_unit/hsync_counter_5_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[4] -translated vga_driver_unit/hsync_counter_4_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[3] -translated vga_driver_unit/hsync_counter_3_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[2] -translated vga_driver_unit/hsync_counter_2_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[1] -translated vga_driver_unit/hsync_counter_1_
+vif_set_map_point -register -original vga_driver_unit/hsync_counter[0] -translated vga_driver_unit/hsync_counter_0_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[0] -translated vga_control_unit/toggle_counter_sig_0_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[1] -translated vga_control_unit/toggle_counter_sig_1_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[2] -translated vga_control_unit/toggle_counter_sig_2_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[3] -translated vga_control_unit/toggle_counter_sig_3_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[4] -translated vga_control_unit/toggle_counter_sig_4_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[5] -translated vga_control_unit/toggle_counter_sig_5_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[6] -translated vga_control_unit/toggle_counter_sig_6_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[7] -translated vga_control_unit/toggle_counter_sig_7_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[8] -translated vga_control_unit/toggle_counter_sig_8_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[9] -translated vga_control_unit/toggle_counter_sig_9_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[10] -translated vga_control_unit/toggle_counter_sig_10_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[11] -translated vga_control_unit/toggle_counter_sig_11_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[12] -translated vga_control_unit/toggle_counter_sig_12_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[13] -translated vga_control_unit/toggle_counter_sig_13_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[14] -translated vga_control_unit/toggle_counter_sig_14_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[15] -translated vga_control_unit/toggle_counter_sig_15_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[16] -translated vga_control_unit/toggle_counter_sig_16_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[17] -translated vga_control_unit/toggle_counter_sig_17_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[18] -translated vga_control_unit/toggle_counter_sig_18_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[19] -translated vga_control_unit/toggle_counter_sig_19_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[20] -translated vga_control_unit/toggle_counter_sig_20_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[21] -translated vga_control_unit/toggle_counter_sig_21_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[22] -translated vga_control_unit/toggle_counter_sig_22_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[23] -translated vga_control_unit/toggle_counter_sig_23_
+vif_set_map_point -register -original vga_control_unit/toggle_counter_sig[24] -translated vga_control_unit/toggle_counter_sig_24_
+vif_set_map_point -register -original dly_counter[0] -translated dly_counter_0_
+vif_set_map_point -register -original dly_counter[1] -translated dly_counter_1_
+
+# Constant Registers
+
+# Retimed Registers
+
+# Altera MAC annotations
+
--- /dev/null
+<html>
+<head>
+<title>syntmp/vga_srr.htm log file</title>
+</head>
+<frameset cols="20%, 80%">
+ <frameset rows="70%, 30%">
+ <frame src="syntmp/vga_toc.htm" name="tocFrame">
+ <frame src="syntmp/vga_flink.htm" name="linkFrame">
+ </frameset>
+ <frame src="syntmp/vga_srr.htm" name="srrFrame">
+</frameset>
+</html>
--- /dev/null
+%%% protect protected_file
--- /dev/null
+%%% protect protected_file
+@ER
+8P_oN8PsHCks_M;H0
+H
+oRCP_MDNLCH_#oN;
+HOR3D FORm"hh; "
+RNH3FODOC _8RoC"#sHC
+";N3HROODF M_CNCLDR:"MP_oN8PsHCks_M3H0k_M4EM#$O0_#N_0C6
+";N3HR#O$M_#sCC"0RMC:#P_CM#_CobrHMg;9"
+RobBN;
+bHR3#D_OFRO 4N;
+bOR3D FORm"hh; "
+RNb3FODOC _8RoC"#sHC
+";
+RoHEM_CNCLD_o#H;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"N;
+HOR3D FO_NCMLRDC"PM:o8N_sCHPsM_kHk03MP4_#O$M_N#006C_"N;
+H#R3$_MOsCC#0MR":P#CC#M_Cbo_HgMr9
+";oBbR;b
+NR#3H_FODO4 R;b
+NRD3OFRO "hhm
+";N3bROODF 8_Co"CRsCH#"
+;
+oOHRFlDkMF_OkCM0sH_#o:rgj
+9;N3HROODF hR"m"h ;H
+NRD3OF_O CC8oRH"s#;C"
+RobBN;
+bHR3#D_OFRO 4N;
+bOR3D FORm"hh; "
+RNb3FODOC _8RoC"#sHC
+";
+RoHEM#$O0_#Nr0Cj9:n;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"o;
+b;RB
+RNb3_H#OODF ;R4
+RNb3FODO" Rh mh"N;
+bOR3D FO_oC8CsR"H"#C;o
+
+H#RE$_MOOMFk0rCsg9:j;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"o;
+b;RB
+RNb3_H#OODF ;R4
+RNb3FODO" Rh mh"N;
+bOR3D FO_oC8CsR"H"#C;o
+
+H_RE#O$M;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"N;
+HOR3D FO_NCMLRDC"PM:o8N_sCHPsM_kHk03ME4_#O$M_N#00nC_"N;
+H#R3$_MO#RC0"#M:CMPC_o#C_MbHr"g9;b
+oR
+B;N3bRHO#_D FOR
+4;N3bROODF hR"m"h ;b
+NRD3OF_O CC8oRH"s#;C"
+H
+oR$P#M#O_0CN0rnj:9N;
+HOR3D FORm"hh; "
+RNH3FODOC _8RoC"#sHC
+";oBbR;b
+NR#3H_FODO4 R;b
+NRD3OFRO "hhm
+";N3bROODF 8_Co"CRsCH#"
+;
+oDHRH_MCOMFk0_Cs#rHoU9:j;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"o;
+b;RB
+RNb3_H#OODF ;R4
+RNb3FODO" Rh mh"N;
+bOR3D FO_oC8CsR"H"#C;o
+
+H#RP$_MOOMFk0rCsg9:j;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"o;
+b;RB
+RNb3_H#OODF ;R4
+RNb3FODO" Rh mh"N;
+bOR3D FO_oC8CsR"H"#C;o
+
+H_RP#O$M;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"N;
+HOR3D FO_NCMLRDC"PM:o8N_sCHPsM_kHk03MP4_#O$M_N#00nC_"N;
+H#R3$_MO#RC0"#M:CMPC_o#C_MbHr"g9;b
+oR
+B;N3bRHO#_D FOR
+4;N3bROODF hR"m"h ;b
+NRD3OF_O CC8oRH"s#;C"
+R
+8P_oNO0FMs_FDk0MH;o
+
+H;Ro
+RNH3FODO" Rh mh"N;
+HOR3D FO_oC8CsR"H"#C;H
+NR#3N$_MOsCC#0MR":P#CC#M_Cbo_HgMr9
+";oBbR;b
+NR#3H_FODO4 R;b
+NRD3OFRO "hhm
+";N3bROODF 8_Co"CRsCH#"
+;
+o0HRFDooCH_#oN;
+HOR3D FORm"hh; "
+RNH3FODOC _8RoC"#sHC
+";N3HROODF M_CNCLDR:"MP_oNO0FMs_FDk0MH34kM_o0Fo_DCOMFk0_Cs#"Ho;H
+NR#3N$_MOsCC#0MR":P#CC#M_Cbo_HgMr9
+";oBbR;b
+NR#3H_FODO4 R;b
+NRD3OFRO "hhm
+";N3bROODF 8_Co"CRsCH#"
+;
+oLHR;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"N;
+HNR3#O$M_#sCC"0RMC:#P_CM#_CobrHMg;9"
+RobBN;
+bHR3#D_OFRO 4N;
+bOR3D FORm"hh; "
+RNb3FODOC _8RoC"#sHC
+";
+RoHsN;
+HOR3D FORm"hh; "
+RNH3FODOC _8RoC"#sHC
+";N3HRNM#$OC_s#RC0"#M:CMPC_o#C_MbHr"g9;b
+oR
+B;N3bRHO#_D FOR
+4;N3bROODF hR"m"h ;b
+NRD3OF_O CC8oRH"s#;C"
+H
+oRo0Fo_DCOMFk0_Cs#rHo.jc:9N;
+HOR3D FORm"hh; "
+RNH3FODOC _8RoC"#sHC
+";N3HRNM#$OC_s#RC0"#M:CMPC_o#C_MbHr"g9;b
+oR
+B;N3bRHO#_D FOR
+4;N3bROODF hR"m"h ;b
+NRD3OF_O CC8oRH"s#;C"
+R
+MI FsRNPoRELCN
+P;
+RoH8_D$OMFk0rCs49:j;H
+NRD3OFRO "hhm
+";N3HROODF 8_Co"CRsCH#"o;
+b;RB
+RNb3_H#OODF ;R4
+RNb3FODO" Rh mh"N;
+bOR3D FO_oC8CsR"H"#C;P
+NR$3#MF_OlDbHCF_bHRM04N;
+POR3FHlbDbC_F0HM_lMNCoRPN
+;
+
--- /dev/null
+%%% protect protected_file
+@ERMRq pa)qq_uR XOCFs_RVVuv)Q;O
+NR 3#HPb_E_8DkR#C4N;
+PHR3#Hbsl;R4
+RNP#_$MVOFsCC_#Js_bH"lRO"D ;P
+NRE3P8#D_ RHb4F;
+R
+J;HDRO N;
+H$R#M#_HOODF ;R4
+OHRD
+s;N#HR$NM_#O$ME;R4
+bHRsCC#0N;
+H$R#M#_N$EMOR
+4;HMRCNH;
+R
+8;oOLRD
+ ;N#LR$oM_N80CO_D OODF M_CRM"CN
+";N#LR$oM_N80CO_D 8NN0_RHM";8"
+RNL#_$MoCN08 OD_08NNk_F0JR""b;
+Rj@@:44::.4:R:fjjsR0k0CRsRkC0Csk;R
+b@:@j4::44R:.fjj:RDVN#VCRNCD#RDVN#
+C;b@R@j::nj::n6jRf:8jRV#VsCRRJJRR8ORD ORDsb#sCCC0RM
+N;
+RMRq pa)qq_uR XV(Vdj._qqb.Rs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HNR80;NO
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_R6h_R ODR7thR7thRBeB;R
+bfjj:RPHMR08NNHL_R08NNHL_R08NN
+L;bjRf:FjRsjRo_NH_d_RhnNR80,NO8NN0L;_H
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:NjRMo8RjR_HhR_68NN0N_,hnN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XV(VdjU_qqbURs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HNR80;NO
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_R6h_R ODR7thR7thRBeB;R
+bfjj:RRFsoHd__RNdhR_n8NN0LN,80;NO
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:NjRMo8RdR_HhR_68NN0N_,hnN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XN_6.6666_UUUUsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LF;
+RkOF06Ro;R
+bfjj:R8NMRRo6o86RNN0N,08NN
+L;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReB
+;
+
+RMRq pa)qq_uR XN_6dnnnn_UUUUsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LF;
+RlOFL0FkR;on
+OFRFRk0o
+U;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjFRGsnRoRRon8NN0NN,80;NL
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:NjRMo8RUURoR08NN8N,NL0N;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+RMRq pa)qq_uR XN(4j(q_66Uq_jRUjblsH;P
+NRC3DVN_lOMsFNRlC" pBp;p"
+RNP3bH#sRHl4N;
+P8R3s_NIo#k0R
+4;N3PR8CFM#Rsl4H;
+RMOH;R
+H8NN0NH;
+R08NN
+L;FFROlkLF0gRo;R
+FO0FkR4o4;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:jGRFsoogRgHROMN,80;NN
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:NjRMo8R4o4R4O4RH8M,NN0N,08NN
+L;
+RMRq pa)qq_uR XN(4j(B_nnUB_jRUjblsH;P
+NRC3DVN_lOMsFNRlC" pBp;p"
+RNP3bH#sRHl4N;
+P8R3s_NIo#k0R
+4;N3PR8CFM#Rsl4H;
+RMOH;R
+H8NN0NH;
+R08NN
+L;FFROlkLF0_Rhn;_H
+OFRFRk0o;4n
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:HjRMhPR_H6_R6h__4H_R6h_;R
+bfjj:R8NMRno4_Nj_.4RonNR80,NLh__6H;_4
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:HjRMOPRHHM_RMOH_4H_RMOH;R
+bfjj:RPHMR08NNHN_R08NNHN__84RNN0N;R
+bfjj:RRFso_4nj._FR6h_R08NNHN__O4,HHM__
+4;N3HR#CNP_#HM0D_VN.o#R4n(jnUUcb;
+R:fjjMRHPNR80_NLHNR80_NLHNR80;NL
+fbRjR:jGRFso_4dj._GRnh__hHR_86,NL0N_
+H;N3HR#CNP_#HM0D_VN.o#R4n(jnUUc
+;
+
+RMRq pa)qq_uR XNc4j4q_66bqRs;Hl
+RNP3VDC_OlNsNFMl"CRppB p
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+P8R3F#MCs4lR;R
+HO;HM
+8HRNN0N;R
+FOLFlFRk0o;4U
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jGRFsoR4UoR4UO,HM8NN0Nb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;
+
+
+
+RMRq pa)qq_uR XN(4jdB_nnbBRs;Hl
+RNP3VDC_OlNsNFMl"CRppB p
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+P8R3F#MCs4lR;R
+HO;HM
+8HRNN0N;R
+H8NN0LF;
+RlOFL0FkR6h__
+H;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRHPHROMR_HO_HMHR_4O;HM
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jFosR.jj__RF.hR_c8NN0N__H4H,OM__H4N;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;R
+bfjj:RPHMR08NNHL_R08NNHL_R08NN
+L;bjRf:GjRFosR.jj__RG.h__6H_RhcN,80_NLHN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XN_6.jjjj_UUUUsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LF;
+RkOF0.Rodb;
+R:fjjMRN8.Rod.RodNR80,NN8NN0Lb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;
+
+
+
+RMRq pa)qq_uR XN_cg RHbslN;
+PDR3ClV_NFOsMCNlRB"p "pp;P
+NR#3HblsHR
+4;N3PR8IsN_0ok#;R4
+RNP3M8FCl#sR
+4;HNR80;NN
+8HRNL0N;R
+FOLFlFRk0o;.c
+fbRjR:jFosR.ocR.8cRNN0N,08NN
+L;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReB
+;
+
+RMRq pa)qq_uR XN4.c_jUjjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.
+6;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRN8.Ro6.Ro6NR80,NN8NN0LN,80,NO8NN08
+;
+
+RMRq pa)qq_uR XN4.c_jjj4sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.
+U;bjRf:HjRM8PRNL0N_8HRNL0N_4H_R08NN
+L;bjRf:HjRM8PRNN0N_8HRNN0N_4H_R08NN
+N;bjRf:HjRM8PRNO0N_8HRNO0N_4H_R08NN
+O;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRN8.RoU.RoUNR80_NNH,_48NN0L__H4N,80_NOH,_48NN08__H4
+;
+
+RMRq pa)qq_uR XNd44_jj44sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0dRo6b;
+R:fjjMRHPNR80_NLHNR80_NLHR_48NN0Lb;
+R:fjjMRHPNR80_NNHNR80_NNHR_48NN0Nb;
+R:fjjMRHPNR80_NOHNR80_NOHR_48NN0Ob;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:R8NMR6odR6odR08NNHN__84,NL0N_4H_,08NNHO__
+4;
+RMRq pa)qq_uR XNd44_((wwsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0cRojb;
+R:fjjMRHPNR80_NLHNR80_NLHR_48NN0Lb;
+R:fjjMRHPNR80_NNHNR80_NNHR_48NN0Nb;
+R:fjjMRHPNR80_NOHNR80_NOHR_48NN0Ob;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RRFsoRcjoRcj8NN0N__H4N,80_NLH,_48NN0O__H4
+;
+
+RMRq pa)qq_uR XN4.c_w(wwsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0Rc
+6;bjRf:HjRM8PRNL0N_8HRNL0N_4H_R08NN
+L;bjRf:HjRM8PRNN0N_8HRNN0N_4H_R08NN
+N;bjRf:HjRM8PRNO0N_8HRNO0N_4H_R08NN
+O;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjsRFR6ocR6ocR08NNHN__84,NL0N_4H_,08NNHO__84,N80N_4H_;
+
+
+
+RMRq pa)qq_uR XN4.c_.jjjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R6
+.;bjRf:HjRM8PRNL0N_8HRNL0N_4H_R08NN
+L;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRN86Ro.6Ro.NR80,NN8NN0ON,80_NLH,_48NN08__H4
+;
+
+RMRq pa)qq_uR XN4.c_UjjjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R6
+(;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRN86Ro(6Ro(NR80,NN8NN0LN,80,NO8NN08__H4
+;
+
+RMRq pa)qq_uR XNd44_jjUUsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0nRo4b;
+R:fjjMRHPNR80_NOHNR80_NOHR_48NN0Ob;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:R8NMR4onR4onR08NN8N,NL0N,08NNHO__
+4;
+RMRq pa)qq_uR XN4.c_jjjUsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0Rn
+c;bjRf:HjRM8PRNO0N_8HRNO0N_4H_R08NN
+O;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRN8nRocnRocNR80,NN8NN0LN,80_NOH,_48NN08__H4
+;
+
+RMRq pa)qq_uR XN4.c_4jjjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0Rn
+g;bjRf:HjRM8PRNL0N_8HRNL0N_4H_R08NN
+L;bjRf:HjRM8PRNN0N_8HRNN0N_4H_R08NN
+N;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRN8nRognRogNR80,NO8NN0N__H4N,80_NLH,_48NN08__H4
+;
+
+RMRq pa)qq_uR XN4.c_7BBUsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R(
+6;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjsRFR6o(_FH_c_RhnNR80,NN8NN08N;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;R
+bfjj:RGlkR6o(_lH_.(Ro6NR80RNO8NN0L_RhnN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XNd44_ww44sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0URojb;
+R:fjjMRHPNR80_NLHNR80_NLHR_48NN0Lb;
+R:fjjMRHPNR80_NNHNR80_NNHR_48NN0Nb;
+R:fjjMRN8URo4URo4NR80_NNH,_48NN0L__H4b;
+R:fjjsRFRjoURjoUR08NNoO,U
+4;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReB
+;
+
+RMRq pa)qq_uR XN_cgUUUURHbslN;
+PDR3ClV_NFOsMCNlRB"p "pp;P
+NR#3HblsHR
+4;N3PR8IsN_0ok#;R4
+RNP3M8FCl#sR
+4;HNR80;NN
+8HRNL0N;R
+FOLFlFRk0o;Uc
+fbRjR:jNRM8oRUcoRUc8NN0NN,80;NL
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;
+RMRq pa)qq_uR XN4.c_(wwwsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0RU
+6;bjRf:HjRM8PRNL0N_8HRNL0N_4H_R08NN
+L;bjRf:HjRM8PRNN0N_8HRNN0N_4H_R08NN
+N;bjRf:HjRM8PRNO0N_8HRNO0N_4H_R08NN
+O;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjsRFR6oUR6oUR08NN88,NN0N_4H_,08NNHL__84,NO0N_4H_;
+
+
+
+RMRq pa)qq_uR XNd44_UUjjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0gRo4b;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:R8NMR4ogR4ogR08NN8N,NL0N,08NN
+O;
+RMRq pa)qq_uR XNd44_44jjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0gRodb;
+R:fjjMRHPNR80_NLHNR80_NLHR_48NN0Lb;
+R:fjjMRHPNR80_NNHNR80_NNHR_48NN0Nb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:R8NMRdogRdogR08NN8O,NN0N_4H_,08NNHL__
+4;
+RMRq pa)qq_uR XN4.c_jjw(sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLkh0R_
+6;bjRf:HjRM8PRNL0N_8HRNL0N_.H_R08NN
+L;bjRf:HjRM8PRNN0N_8HRNN0N_.H_R08NN
+N;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRHPNR80_NOHNR80_NOHR_j8NN0Ob;
+R:fjjMRN8gRo(R_HhR_6h,_n8NN0O__HjN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;R
+bfjj:RRFso_g(Hd_NRnh_R08NN88,NN0N_.H_,08NNHL__
+.;
+RMRq pa)qq_uR XN4.c_www(sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;jd
+fbRjR:jHRMP8NN0LR_H8NN0L__H4NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:FjRs4RojodR4Rjd8NN0ON,80,N88NN0N__H4N,80_NLH;_4
+RMRq pa)qq_uR XN4.c_ww(wsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;jU
+fbRjR:jHRMP8NN0LR_H8NN0L__H4NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jHRMP8NN08R_H8NN08__H4NR80;N8
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:FjRs4RojoUR4RjU8NN0ON,80_NNH,_48NN0L__H4N,80_N8H;_4
+RMRq pa)qq_uR XN4.c_j4jjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;4c
+fbRjR:jHRMP8NN0LR_H8NN0L__H4NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:NjRMo8R4R4coc44R08NN8O,N80N,08NNHN__84,NL0N_4H_;
+
+
+
+RMRq pa)qq_uR XN4.c_q.qqsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLkh0R_
+6;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRHPNR80_N8HNR80_N8HNR80;N8
+fbRjR:jHRMP8NN0OR_H8NN0OR_H8NN0Ob;
+R:fjjMRHPNR80_NLHNR80_NLHNR80;NL
+fbRjR:jFosR4_4gHd_NRnh_R08NNHL_,08NNHO_,08NNH8_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jNRM8og44_hHR_86RNN0N,nh_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+RMRq pa)qq_uR XN4.c_j4wwsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;.d
+fbRjR:jHRMP8NN0LR_H8NN0L__H.NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H.NR80;NN
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:HjRM8PRNO0N_8HRNO0N_.H_R08NN
+O;bjRf:FjRs4Ro.jd_R.o4d_Rh6N,80_NOH;_.
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:NjRMo8R4_.djd_NR6h_R08NN88,NN0N_.H_,08NNHL__
+.;
+RMRq pa)qq_uR XN4.c_4jwwsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;.g
+fbRjR:jHRMP8NN0LR_H8NN0L__H.NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H.NR80;NN
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:HjRM8PRN80N_8HRN80N_.H_R08NN
+8;bjRf:HjRM8PRNO0N_8HRNO0N_.H_R08NN
+O;bjRf:FjRs4Ro.jg_R.o4g_Rh6N,80_NOH;_.
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:NjRMo8R4_.gjd_NR6h_R08NNHN__8.,NL0N_.H_,08NNH8__
+.;
+RMRq pa)qq_uR XN4.c_w(jjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLkh0R_
+6;bjRf:HjRM8PRNL0N_8HRNL0N_.H_R08NN
+L;bjRf:HjRM8PRNN0N_8HRNN0N_.H_R08NN
+N;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRHPNR80_N8HNR80_N8HNR80;N8
+fbRjR:jNRM8o64d_hHR_86RNO0N,nh_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jFosR4_d6Hd_NRnh_R08NNHN__8.,NL0N_.H_,08NNH8_;
+
+
+
+RMRq pa)qq_uR XNd44_..qqsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0_Rh6b;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RPHMR08NNHO_R08NNHO_R08NN
+O;bjRf:HjRM8PRNL0N_8HRNL0N_8HRNL0N;R
+bfjj:RRFsoj4c_NH_d_RhnNR80_NLHN,80_NOHN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;R
+bfjj:R8NMRco4jR_HhR_68NN0N_,hnN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XN4.c_w7jjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLkh0R_
+6;bjRf:HjRM8PRNN0N_8HRNN0N_.H_R08NN
+N;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRHPNR80_N8HNR80_N8HNR80;N8
+fbRjR:jNRM8od4c_hHR_86RNO0N,nh_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jFosR4_cdHd_NRnh_R08NN8L,NN0N_.H_,08NNH8_;
+
+
+
+RMRq pa)qq_uR XN4.c_.wwqsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;c(
+fbRjR:jFosR4Rc(o(4cR08NNh8,_
+6;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRHPNR80_NOHNR80_NOHNR80;NO
+fbRjR:jHRMP8NN0LR_H8NN0L__HjNR80;NL
+fbRjR:jFosR4_cUHd_NRnh_R08NNHL__8j,NO0N_
+H;N3HR#CNP_#HM0D_VN.o#R4n(jnUUcb;
+R:fjjMRN84RocHU_R6h_R08NNhN,_
+n;N3HR#CNP_#HM0D_VN.o#R4n(jnUUc
+;
+
+RMRq pa)qq_uR XN4.c_Bjq sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;64
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:NjRMo8R4_64jd_NRch_R08NN8L,N80N_4H_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jHRMP8NN0OR_H8NN0O__H4NR80;NO
+fbRjR:jNRM8o446_Nj_dR_jhR_68NN0NN,80_NOH;_4
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:FjRs4Ro6j4_R6o44_Rh6_,hcN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XN4.c_wwj4sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;6n
+fbRjR:jHRMP8NN0LR_H8NN0L__H.NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H.NR80;NN
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:HjRM8PRN80N_8HRN80N_.H_R08NN
+8;bjRf:FjRs4Ro6jn_R6o4nNR80,NOh;_6
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:NjRMo8R4_6njd_NR6h_R08NNHN__8.,NL0N_.H_,08NNH8__
+.;
+RMRq pa)qq_uR XN4.c_qqqAsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R4;n4
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:HjRM8PRNO0N_8HRNO0N_4H_R08NN
+O;bjRf:HjRM8PRNL0N_8HRNL0N_4H_R08NN
+L;bjRf:NjRMo8R4_n4jd_NR6h_R08NNHL__84,NO0N_4H_,08NNH8__
+4;N3HR#CNP_#HM0D_VN.o#R4n(jnUUcb;
+R:fjjsRFRno44R_jo44nR08NNhN,_
+6;N3HR#CNP_#HM0D_VN.o#R4n(jnUUc
+;
+
+RMRq pa)qq_uR XVjVg4Uj_URUUblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+H#sOD;R
+HC;MN
+sFRCkoF0_Rh4o;
+M_Rh4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_
+.;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jNRM8o64nRno46NR80,NN8NN0Lb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_h4R_O.RDt Rht7RhC7RM
+N;bjRf:HjRM#PRO_DsHOR#DHs__#.RO;Ds
+fbRjR:jNRM8#sODR.h_Rno46O,#DHs__
+.;
+RMRq pa)qq_uR XV.VgjU._jRjjblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+8HRNO0N;R
+H8NN08H;
+R OD;H
+NRM#$_OH#D FOR
+4;HOR#D
+s;HMRCNF;
+RosCFRk0h;_4
+RoMh;_4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR.h_;M
+NRN3#PMC_CV0_D#No46R.nb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_h4R_O.RDt Rht7RhC7RM
+N;bjRf:HjRM#PRO_DsHOR#DHs__#.RO;Ds
+fbRjR:jNRM8#sODR.h_Rno4nO,#DHs__
+.;bjRf:NjRMo8R4Rnnon4nR08NN8N,NL0N,08NN8O,N80N;
+
+
+
+RMRq pa)qq_uR XVgVU(qU_qRqqblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HDRO N;
+H$R#M#_HOODF ;R4
+#HRO;Ds
+CHRM
+N;FCRso0FkR4h_;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rh.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjVR8VCs#RRwwhR_4hR_.ORD tRh7tRh7C;MN
+fbRjR:jHRMP#sOD_#HRO_DsHR_.#sOD;R
+bfjj:R8NMRD#Os_Rh.NR80,NN#sOD_.H_;
+
+
+
+RMRq pa)qq_uR XVjVg4 j_ R blsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+H#sOD;R
+HC;MN
+sFRCkoF0_Rh4o;
+M_Rh4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_
+.;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jFosR4Rngog4nR08NN8N,NL0N;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:j8sVV#wCRw_Rh4_Rh.DRO hRt7hRt7MRCNb;
+R:fjjMRHPOR#DHs_RD#Os__H.OR#D
+s;bjRf:NjRM#8RORDshR_.og4n,D#Os__H.
+;
+
+RMRq pa)qq_uR XV.Vgj.._jRjjblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+8HRNO0N;R
+H8NN08H;
+R OD;H
+NRM#$_OH#D FOR
+4;HOR#D
+s;HMRCNF;
+RosCFRk0h;_4
+RoMh;_4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR.h_;M
+NRN3#PMC_CV0_D#No46R.nb;
+R:fjjMRHPNR80_NLHNR80_NLHR_48NN0Lb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_h4R_O.RDt Rht7RhC7RM
+N;bjRf:HjRM#PRO_DsHOR#DHs__#.RO;Ds
+fbRjR:jNRM8#sODR.h_R(o4jO,#DHs__
+.;bjRf:NjRMo8R4R(joj4(R08NN8N,NO0N,08NN88,NL0N_4H_;
+
+
+
+RMRq pa)qq_uR XVgVcUw_w(bwRs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HNR80;NO
+8HRN80N;R
+HO;D
+RNH#_$MHD#OFRO 4F;
+RosCFRk0h;_4
+RoMh;_4
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RPHMR08NNHL_R08NNHL__84RNL0N;R
+bfjj:RPHMR08NNHN_R08NNHN__84RNN0N;R
+bfjj:RPHMR08NNHO_R08NNHO__84RNO0N;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:j8sVV#wCRw_Rh44Ro(OcRDt Rht7Rhe7RB
+B;bjRf:FjRs4Ro(ocR4R(c8NN08N,80_NNH,_48NN0L__H4N,80_NOH;_4
+RMRq pa)qq_uR XVcVUgAU_ARAAblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+H#sOD;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh;_.
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RPHMR08NNHL_R08NNHL__84RNL0N;R
+bfjj:RRFsoj4URUo4jNR80,NN8NN0L__H4b;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_h4R_O.RDt Rht7Rhe7RB
+B;bjRf:HjRM#PRO_DsHOR#DHs__#.RO;Ds
+fbRjR:jNRM8#sODR.h_RUo4jO,#DHs__
+.;
+RMRq pa)qq_uR XVcVUg7U_7R77blsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+H#sOD;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh;_.
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RPHMR08NNHN_R08NNHN__84RNN0N;R
+bfjj:RRFso.4URUo4.NR80,NL8NN0N__H4b;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_h4R_O.RDt Rht7Rhe7RB
+B;bjRf:HjRM#PRO_DsHOR#DHs__#.RO;Ds
+fbRjR:jNRM8#sODR.h_RUo4.O,#DHs__
+.;
+RMRq pa)qq_uR XV(Vdjj_UUbjRs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HNR80;NO
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_RUo4cDRO hRt7hRt7BReBb;
+R:fjjMRN84RoUocR4RUc8NN0NN,80,NL8NN0O
+;
+
+RMRq pa)qq_uR XV(Vd4w_((bwRs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HNR80;NO
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+FOLFlFRk0on4U;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jHRMP8NN0LR_H8NN0L__H4NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jHRMP8NN0OR_H8NN0O__H4NR80;NO
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_RUo4nDRO hRt7hRt7BReBb;
+R:fjjsRFRUo4n4RoU8nRNN0N_4H_,08NNHL__84,NO0N_4H_;
+
+
+
+RMRq pa)qq_uR XVgVcUj_jUbjRs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HNR80;NO
+8HRN80N;R
+HO;D
+RNH#_$MHD#OFRO 4F;
+RosCFRk0h;_4
+RoMh;_4
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RPHMR08NNH8_R08NNH8__84RN80N;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:j8sVV#wCRw_Rh44RogO4RDt Rht7Rhe7RB
+B;bjRf:NjRMo8R4Rg4o44gR08NN8N,NL0N,08NN8O,N80N_4H_;
+
+
+
+RMRq pa)qq_uR XVgVcUB_jqb Rs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HNR80;NO
+8HRN80N;R
+HO;D
+RNH#_$MHD#OFRO 4F;
+RosCFRk0h;_4
+RoMh;_4
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:j8sVV#wCRw_Rh44RogO6RDt Rht7Rhe7RB
+B;bjRf:HjRM8PRN80N_8HRN80N_4H_R08NN
+8;bjRf:NjRMo8R4_g6jd_NRch_R08NN8N,N80N_4H_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jHRMP8NN0OR_H8NN0O__H4NR80;NO
+fbRjR:jNRM8o64g_Nj_dR_jhR_68NN0LN,80_NOH;_4
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:FjRs4Rogj6_Rgo46_Rh6_,hcN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XVUVdnw_wjbjRs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN08H;
+R OD;H
+NRM#$_OH#D FOR
+4;FCRso0FkR4h_;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.nb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_84RN80NR ODR7thR7thRBeB;
+
+
+
+RMRq pa)qq_uR XVcVUg(U_(R((blsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+H#sOD;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh;_.
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RPHMR08NNHL_R08NNHL__84RNL0N;R
+bfjj:RPHMR08NNHN_R08NNHN__84RNN0N;R
+bfjj:RRFsoj.jRjo.jNR80_NNH,_48NN0L__H4b;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_h4R_O.RDt Rht7Rhe7RB
+B;bjRf:HjRM#PRO_DsHOR#DHs__#.RO;Ds
+fbRjR:jNRM8#sODR.h_Rjo.jO,#DHs__
+.;
+RMRq pa)qq_uR XO.M06Ugd_66qqsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p_"ww;P
+NR#3HblsHR
+4;N3PR8IsN_0ok#;R4
+RNP3_H#V4VR;P
+NRF38MsC#l;R4
+OHRH
+M;HNR80;NN
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+H#sOD;R
+H#NDF8F;
+RosCFRk0h;_4
+8HRNO0N;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rh.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jGRFsod.jRjo.dHROMN,80;NN
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_Rdh_R ODR7thR7thRBeB;R
+bfjj:RGlkRF#DNh8R_o.R.Rjd8NN0ODR#F;N8
+fbRjR:jHRMP#sOD_#HRO_DsHR_.#sOD;R
+bfjj:R8NMRD#Os_Rhd_Rh.O,#DHs__
+.;
+RMRq pa)qq_uR XO.M06.gc_66qqj_qqbjRs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+HO;HM
+8HRNN0N;R
+HO;D
+RNH#_$MHD#OFRO 4H;
+RD#OsH;
+RF#DN
+8;FCRso0FkR4h_;R
+FO0FkRjo.(H;
+R08NN
+O;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh;_.
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRdh_;M
+NRN3#PMC_CV0_D#No46R.nb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_h4R_OdRDt Rht7Rhe7RB
+B;bjRf:ljRk#GRD8FNR.h_Rjo.6NR80RNO#NDF8b;
+R:fjjMRHPOR#DHs_RD#Os__H.OR#D
+s;bjRf:NjRM#8RORDshR_dh,_.#sOD_.H_;R
+bfjj:RsGFRjo.6.RojO6RH8M,NN0N;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jNRM8o(.jRjo.(HROMN,80;NN
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;
+RMRq pa)qq_uR XO.M0cjg6_nnnnU_UUbURs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R08NN
+L;HDRO N;
+H$R#M#_HOODF ;R4
+#HRO;Ds
+#HRD8FN;R
+FsFCokh0R_
+4;FFROko0R.;4j
+8HRNO0N;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rh.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_Rdh_R ODR7thR7thRBeB;R
+bfjj:RGlkRF#DNh8R_o.R.RjU8NN0ODR#F;N8
+fbRjR:jHRMP#sOD_#HRO_DsHR_.#sOD;R
+bfjj:R8NMRD#Os_Rhd_Rh.O,#DHs__
+.;bjRf:GjRFosR.RjUoU.jR08NN8N,NL0N;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jNRM8oj.4R4o.jNR80,NN8NN0LN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XO.M0cjg6_6666q_qqbqRs;Hl
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NR#3H_RVV4N;
+P8R3F#MCs4lR;R
+H8NN0NH;
+R OD;H
+NRM#$_OH#D FOR
+4;HOR#D
+s;HDR#F;N8
+sFRCkoF0_Rh4F;
+RkOF0NR80;NN
+8HRNO0N;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rh.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_Rdh_R ODR7thR7thRBeB;R
+bfjj:RPHMR08NNHN_R08NNHN__84RNN0N;R
+bfjj:RGlkRF#DNh8R_8.RNN0N_4H_R08NN#ORD8FN;R
+bfjj:RPHMRD#OsR_H#sOD_.H_RD#Osb;
+R:fjjMRN8OR#DhsR_hdR_#.,O_DsH;_.
+RMRq pa)qq_uR XN_cg((((RHbslN;
+PDR3ClV_NFOsMCNlRB"p "pp;P
+NR#3HblsHR
+4;N3PR8IsN_0ok#;R4
+RNP3M8FCl#sR
+4;HNR80;NN
+8HRNL0N;R
+FOLFlFRk0o..4;R
+bfjj:RPHMR08NNHL_R08NNHL__84RNL0N;R
+bfjj:RPHMR08NNHN_R08NNHN__84RNN0N;R
+bfjj:RRFso..4R4o..NR80_NNH,_48NN0L__H4b;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;
+
+
+
+RMRq pa)qq_uR XN_cg4444RHbslN;
+PDR3ClV_NFOsMCNlRB"p "pp;P
+NR#3HblsHR
+4;N3PR8IsN_0ok#;R4
+RNP3M8FCl#sR
+4;HNR80;NN
+8HRNL0N;R
+FOLFlFRk0o6.4;R
+bfjj:RPHMR08NNHL_R08NNHL__84RNL0N;R
+bfjj:RPHMR08NNHN_R08NNHN__84RNN0N;R
+bfjj:R8NMR4o.6.Ro486RNN0N_4H_,08NNHL__
+4;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReB
+;
+
+RMRq pa)qq_uR XNd44_ww sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0.Ro4
+U;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjsRFR4o.U.Ro48URNN0N,08NN8L,NO0N;
+
+
+
+RMRq pa)qq_uR XN4.c_jjjcsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.;.j
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jHRMP8NN0OR_H8NN0O__H4NR80;NO
+fbRjR:jHRMP8NN08R_H8NN08__H4NR80;N8
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:NjRMo8R.R.joj..R08NN8L,NN0N_4H_,08NNHO__84,N80N_4H_;
+
+
+
+RMRq pa)qq_uR XN4.c_www sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.;.n
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:FjRs.Ro.onR.R.n8NN0NN,80,NL8NN0ON,80;N8
+RMRq pa)qq_uR XN4.c_jw jsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.;.g
+fbRjR:jNRM8og..R.o.gNR80,N8oj.d;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:jFosR.Rdjoj.dR08NN8N,NL0N,08NN
+O;
+RMRq pa)qq_uR XN4.c_((w(sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.;d.
+fbRjR:jHRMP8NN0LR_H8NN0L__H.NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H.NR80;NN
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:HjRM8PRNO0N_8HRNO0N_.H_R08NN
+O;bjRf:NjRMo8R._d.jd_NR6h_R08NN88,NO0N_.H_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jFosR._d.j.Rodh.R_86,NN0N_.H_,08NNHL__
+.;
+RMRq pa)qq_uR XNd44_ww((sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;FFROlkLF0.Rod
+U;bjRf:HjRM8PRNL0N_8HRNL0N_4H_R08NN
+L;bjRf:HjRM8PRNN0N_8HRNN0N_4H_R08NN
+N;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjsRFRdo.U.Rod8URNO0N,08NNHN__84,NL0N_4H_;
+
+
+
+RMRq pa)qq_uR XN4.c_jj4jsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.;c.
+fbRjR:jHRMP8NN0LR_H8NN0L__H4NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jHRMP8NN0OR_H8NN0O__H4NR80;NO
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:NjRMo8R.Rc.o..cR08NN88,NN0N_4H_,08NNHL__84,NO0N_4H_;
+
+
+
+RMRq pa)qq_uR XN4.c_ w sRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.;cU
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:NjRMo8R._cUjd_NR6h_R08NN8O,N80N;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jFosR._cUj.Roc8URNN0N,08NNhL,_
+6;
+RMRq pa)qq_uR XN4.c_w jjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLkh0R_
+6;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRHPNR80_N8HNR80_N8HNR80;N8
+fbRjR:jNRM8o4.6_hHR_86RNO0N,nh_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jFosR._64Hd_NRnh_R08NN8N,NL0N,08NNH8_;
+
+
+
+RMRq pa)qq_uR XN4.c_. wdsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLkh0R_
+c;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjkRlGdRlRch_R.h_R08NN88RNL0N;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jHRMP8NN0OR_H8NN0OR_H8NN0Ob;
+R:fjjsRFR_l4C_Rh.NR80,NN8NN0O;_H
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;
+RMRq pa)qq_uR XN4.c_j(wjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLko0R.;n4
+fbRjR:jHRMP8NN0LR_H8NN0L__H4NR80;NL
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jHRMP8NN0OR_H8NN0O__H4NR80;NO
+fbRjR:jNRM8o4.nRno.4NR80,N8o..n;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:jFosR.Rn.o..nR08NNHN__84,NL0N_4H_,08NNHO__
+4;
+RMRq pa)qq_uR XN4.c_jj(dsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p"N;
+PHR3#Hbsl;R4
+RNP3N8sIk_o04#R;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R08NN
+O;HNR80;N8
+OFRFFlLkh0R_
+6;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjMRHPNR80_NLHNR80_NLHNR80;NL
+fbRjR:jFosR._n(Hd_NR(h_Rnh_,08NNHL_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jHRMP8NN0OR_H8NN0OR_H8NN0Ob;
+R:fjjMRN8.RonH(_R6h_R08NNHO_,(h_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jHRMP8NN0NR_H8NN0NR_H8NN0Nb;
+R:fjjMRN8.RonH(__RFdhR_n8NN08N,80_NNHN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XVcVcUw._wRjjblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+8;HDRO N;
+H$R#M#_HOODF ;R4
+NHRO;Ds
+sFRCkoF0_Rh4o;
+M_Rh4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjVR8VCs#RRwwhR_48NN08DRO ORNDtsRhe7RB
+B;
+RMRq pa)qq_uR XV6Vcgcc_jRjjblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+8HRNO0N;R
+H8NN08H;
+R OD;H
+NRM#$_OH#D FOR
+4;HORND
+s;FCRso0FkR4h_;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.nb;
+R:fjjMRHPNR80_NNHNR80_NNHR_48NN0Nb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_o4R.R(cORD NsODR7thRBeB;R
+bfjj:R8NMR(o.c.Ro(8cRNL0N,08NN8O,N80N,08NNHN__
+4;
+RMRq pa)qq_uR XV6VcgUc_jRjjblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+8HRNO0N;R
+H8NN08H;
+R OD;H
+NRM#$_OH#D FOR
+4;HORND
+s;FCRso0FkR4h_;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.nb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_o4R.R(UORD NsODR7thRBeB;R
+bfjj:R8NMR(o.U.Ro(8URNN0N,08NN8L,NO0N,08NN
+8;
+RMRq pa)qq_uR XVcVcjg._gRggblsH;P
+NRC3DVN_lOMsFNRlC" pBpwp_w
+";N3PRHs#bH4lR;P
+NRs38NoI_kR0#4N;
+PHR3#V_VR
+4;N3PR8CFM#Rsl4H;
+R08NN
+N;HNR80;NL
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+HNsOD;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jGRFso4.URUo.4NR80,NL8NN0N__H4b;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;R
+bfjj:RV8VsR#CwhwR_o4R.RU4ORD NsODR7thRBeB;
+
+
+
+RMRq pa)qq_uR XV.V46_n.6666RHbslN;
+PDR3ClV_NFOsMCNlRB"p _ppw;w"
+RNP3bH#sRHl4N;
+P8R3s_NIo#k0R
+4;N3PRHV#_V;R4
+RNP3M8FCl#sR
+4;HNR80;NN
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+HNsOD;R
+H#sOD;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh;_.
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:j8sVV#wCRw_Rh4_Rh.DRO ORNDtsRhe7RB
+B;bjRf:HjRM#PRO_DsHOR#DHs__#.RO;Ds
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jNRM8#sODR.h_R08NNHN__#4,O_DsH;_.
+RMRq pa)qq_uR XV.V46_gUnnnn_UUUUsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p_"ww;P
+NR#3HblsHR
+4;N3PR8IsN_0ok#;R4
+RNP3_H#V4VR;P
+NRF38MsC#l;R4
+8HRNN0N;R
+H8NN0LH;
+R OD;H
+NRM#$_OH#D FOR
+4;HORND
+s;HOR#D
+s;FCRso0FkR4h_;R
+FO0FkRUo.no;
+M_Rh4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_
+.;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_R.h_R ODRDNOshRt7BReBb;
+R:fjjMRHPOR#DHs_RD#Os__H.OR#D
+s;bjRf:NjRM#8RORDshR_.oc.U,D#Os__H.b;
+R:fjjFRGs.RoUocR.RUc8NN0NN,80;NL
+RNH3P#NCM_H#V0_D#No.(Rn4UjUn
+c;bjRf:NjRMo8R.RUnon.UR08NN8N,NL0N;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+RMRq pa)qq_uR XVdV4n_..6qq6_UUjjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p_"ww;P
+NR#3HblsHR
+4;N3PR8IsN_0ok#;R4
+RNP3_H#V4VR;P
+NRF38MsC#l;R4
+OHRH
+M;HNR80;NN
+8HRNL0N;R
+HO;D
+RNH#_$MHD#OFRO 4H;
+RDNOsH;
+RD#OsF;
+RosCFRk0h;_4
+OFRFRk0og.U;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rh.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjVR8VCs#RRwwhR_4hR_.ORD NsODR7thRBeB;R
+bfjj:RPHMRD#OsR_H#sOD_.H_RD#Osb;
+R:fjjMRN8OR#DhsR_o.R.,U(#sOD_.H_;R
+bfjj:RsGFRUo.(.RoUO(RH8M,NN0N;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jNRM8og.URUo.gHROMN,80,NN8NN0L
+;
+
+RMRq pa)qq_uR XVdV4n_..nBBn_UUjjsRbH
+l;N3PRD_CVlsNOFlMNCpR"Bp p_"ww;P
+NR#3HblsHR
+4;N3PR8IsN_0ok#;R4
+RNP3_H#V4VR;P
+NRF38MsC#l;R4
+OHRH
+M;HNR80;NN
+8HRNL0N;R
+HO;D
+RNH#_$MHD#OFRO 4H;
+RDNOsH;
+RD#OsF;
+RosCFRk0h;_4
+OFRFRk0oc.g;M
+oR4h_;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rh.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;bjRf:VjRNCD#R7thR7th;R
+bfjj:Rk0sCBReBBReBb;
+R:fjjVR8VCs#RRwwhR_4hR_.ORD NsODR7thRBeB;R
+bfjj:RPHMRD#OsR_H#sOD_.H_RD#Osb;
+R:fjjMRN8OR#DhsR_h.R_Hn_,D#Os__H.b;
+R:fjjMRHP_Rh6R_Hh__6HR_4h;_6
+fbRjR:jNRM8oc.g_Nj_..Rog8cRNL0N,6h__4H_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jHRMPO_HMHHROM__H4HROMb;
+R:fjjMRHPNR80_NNHNR80_NNHR_48NN0Nb;
+R:fjjsRFRgo.c__jFh.R_86RNN0N_4H_,MOH_4H_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jHRMP8NN0LR_H8NN0LR_H8NN0Lb;
+R:fjjFRGs.Rogj4__RG.h__nH_Rh6N,80_NLHN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XVdV4n_4UnBBnRHbslN;
+PDR3ClV_NFOsMCNlRB"p _ppw;w"
+RNP3bH#sRHl4N;
+P8R3s_NIo#k0R
+4;N3PRHV#_V;R4
+RNP3M8FCl#sR
+4;HHROMH;
+R08NN
+N;HNR80;NL
+OHRD
+ ;N#HR$HM_#FODO4 R;R
+HNsOD;R
+H#sOD;R
+FsFCokh0R_
+4;ohMR_
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh;_.
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+bfjj:RDVN#tCRht7Rh
+7;bjRf:0jRsRkCeRBBe;BB
+fbRjR:j8sVV#wCRw_Rh4_Rh.DRO ORNDtsRhe7RB
+B;bjRf:HjRM#PRO_DsHOR#DHs__#.RO;Ds
+fbRjR:jNRM8#sODR.h_R6h__#H,O_DsH;_.
+fbRjR:jHRMPO_HMHHROM__H4HROMb;
+R:fjjMRHPNR80_NNHNR80_NNHR_48NN0Nb;
+R:fjjsRFRgo.n__jFh.R_8cRNN0N_4H_,MOH_4H_;H
+NRN3#PHC_M_#0VoDN#n.R(U4jU;nc
+fbRjR:jHRMP8NN0LR_H8NN0LR_H8NN0Lb;
+R:fjjFRGs.Rogjn__RG.h__6H_RhcN,80_NLHN;
+H#R3N_PCH0M#_NVDoR#.nj(4UcUn;
+
+
+
+RMRq pa)qq_uR XVdV46_Un6qq6RHbslN;
+PDR3ClV_NFOsMCNlRB"p _ppw;w"
+RNP3bH#sRHl4N;
+P8R3s_NIo#k0R
+4;N3PRHV#_V;R4
+RNP3M8FCl#sR
+4;HHROMH;
+R08NN
+N;HDRO N;
+H$R#M#_HOODF ;R4
+NHRO;Ds
+#HRO;Ds
+sFRCkoF0_Rh4o;
+M_Rh4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_
+.;N3MR#CNP_0MC_NVDoR#4.;6n
+fbRjR:jHRMP8NN0NR_H8NN0N__H4NR80;NN
+fbRjR:jGRFsog.gRgo.gHROMN,80;NN
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;bjRf:8jRV#VsCwRwR4h_R.h_R ODRDNOshRt7BReBb;
+R:fjjMRHPOR#DHs_RD#Os__H.OR#D
+s;bjRf:NjRM#8RORDshR_.og.g,D#Os__H.
+;
+
+RMRvB )z_)YpRQA#N0s0_HGHuF_7bjRs;Hl
+RNP3VDC_OlNsNFMl"CRQ;m"
+RNP3bH#N48R;P
+NR#3HblsHR
+4;N3PR8CFM#Rsl4H;
+R08NN;HM
+bLRNF8H;H
+NRM#$_H0s#00NC;R4
+fbRjR:jV#NDChRt7hRt7b;
+R:fjjsR0keCRBeBRB
+B;b@R@nc:c:c(:c.:4:_sjbRHMfjj:RH0sR4Q_3H0sR8bNH8FRNH0NMBReB
+;
+
+RMRvB )z_)YpRQA#N0s0_HGHmF_uRajblsH;P
+NRC3DVN_lOMsFNRlC""Qm;P
+NR#3HbRN84N;
+PHR3#Hbsl;R4
+RNP3M8FCl#sR
+4;FFROlkLF0NRb8;HF
+bHRNF8H;H
+NRM#$_H0s#00NC;R4
+FHRCb;
+R:fjjNRVDR#CtRh7t;h7
+fbRjR:j0CskRBeBRBeB;
+
+
+
+"VRMNFMl;C"RHyVDjCR
+"VR/0Fb/M#$bVDH$b/VoON_.gjjjDn/HPL/E#8/0P83E;8"RHyVD4CR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_ bN38PE"y;RVCHDRN.
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/8#04c4n38PE"y;RVCHDRNd
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/#kMHCoM8E3P8R";yDVHC
+RcNRVR3_H#PDE8R
+4;V/R"F/b0#b$MD$HV/oVbN._OjjjgnH/DLE/P8s/NH30EP"E8;VRyHRDC6V
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8R";yDVHC
+RnNRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
+V3RRHP#_ER8D4V;
+RE"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E;8"RHyVDUCR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P"E8;VRyHRDCgV
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNs_NOE3P8R";yDVHCjR4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_MOF0DsF_ONs38PE"y;RVCHDR
+4.NRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCNs_sPO3E;8"RHyVD4CRdV
+NRHR3#E_P84DR;R
+MRaqp _)qqXu Rs#0NG0H_CDODuDR);Qv
+RNO30CGCNsMD8_CHMV_NRlC"s#0NG0H_CDOD;D"
+RNP3VDC_OlNsNFMl"CRppB p
+";N3PRHs#bH4lR;P
+NRH3#lV8CN0kDRC'8PsbF,P8COMDs'N;
+PbR3E#$_HR0C"apz"N;
+PPR3E_8D#b HR
+4;N3PRCCG0sDMN_sPCHoDF_lMNC#R"00sNHDG_ODCD"N;
+PCR3Gs0CM_NDPDE8_lMNC#R"00sNHDG_ODCD"F;
+RlOFL0Fk;H
+NRH3#lV8CN0kDRz'hp;p'
+sFRCkoF0N;
+H#R3HCl8VDNk0hR'z'pp;R
+FO0Fk;H
+NRH3#lV8CN0kDRz'hp;p'
+OFRNF#Ok
+0;HDRO N;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'7th'H;
+R08NN
+N;N3HR#8HlCkVND'0Re'BB;H
+NRJ3PlV8CN0kDRB'eB
+';HNR80;NL
+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+8HRNO0N;H
+NRH3#lV8CN0kDRB'eB
+';N3HRP8JlCkVND'0Re'BB;R
+H8NN08N;
+H#R3HCl8VDNk0eR'B;B'
+RNH3lPJ8NCVkRD0'BeB'H;
+RDNOsN;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'7th'N;
+H$R#M#_N$EMOR
+4;HOR#D
+s;N3HR#8HlCkVND'0Rt'h7;H
+NRJ3PlV8CN0kDRh't7
+';HDR#F;N8
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+CHRM
+N;N3HR#8HlCkVND'0Re'BB;H
+NRJ3PlV8CN0kDRB'eB
+';HHROMN;
+H#R3HCl8VDNk0tR'h;7'
+HHRMsPC0
+N;N3HR#8HlCkVND'0Rt'h7;H
+NRJ3PlV8CN0kDRh't7
+';HDRNF;N8
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+RNH#_$MNM#$O4ER;R
+HsOCoNH#OMN;
+H#R3HCl8VDNk0hR'z'pp;H
+NRJ3PlV8CN0kDRh't7
+';
+"VRMNFMl;C"RHyVDjCR
+"VR/0Fb/M#$bVDH$b/VoON_.gjjjDn/HPL/E#8/0P83E;8"RHyVD4CR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_ bN38PE"y;RVCHDRN.
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/8#04c4n38PE"y;RVCHDRNd
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/#kMHCoM8E3P8R";yDVHC
+RcNRVR3_H#PDE8R
+4;V/R"F/b0#b$MD$HV/oVbN._OjjjgnH/DLE/P8s/NH30EP"E8;VRyHRDC6V
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8R";yDVHC
+RnNRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
+V3RRHP#_ER8D4V;
+RE"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E;8"RHyVDUCR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P"E8;VRyHRDCgV
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNs_NOE3P8R";yDVHCjR4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_MOF0DsF_ONs38PE"y;RVCHDR
+4.NRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCNs_sPO3E;8"RHyVD4CRdV
+NRHR3#E_P84DR;R
+MRaqp _)qqXu Rs#0NG0H_CDODVD_V)RuQ
+v;N3ORCCG0sDMN_HC8VN_Ml"CR#N0s0_HGDDOCD
+";N3OR#b H_8PED#_kC;R4
+RNP3VDC_OlNsNFMl"CRppB pw_w"N;
+PHR3#Hbsl;R4
+RNP30CGCNsMDC_PsFHDoN_Ml"CR#N0s0_HGDDOCD
+";N3PRCCG0sDMN_8PEDN_Ml"CR#N0s0_HGDDOCD
+";N3PR#8HlCkVND'0R8bCPF8s,CDPOs;M'
+RNP3$bE_0#HCwR"w
+";N3PRPDE8_H# b;R4
+OFRFFlLk
+0;N3HR#8HlCkVND'0Rhpzp'F;
+RosCF;k0
+RNH3l#H8NCVkRD0'phzp
+';N3HRHN#DM#8_CCJkMN0HDH_bM;R4
+OFRF;k0
+RNH3l#H8NCVkRD0'phzp
+';FNRO#kOF0H;
+R OD;H
+NRH3#lV8CN0kDRh't7
+';N3HRP8JlCkVND'0Rt'h7;H
+NRM#$_OH#D FOR
+4;HNR80;NN
+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+8HRNL0N;H
+NRH3#lV8CN0kDRB'eB
+';N3HRP8JlCkVND'0Re'BB;R
+H8NN0ON;
+H#R3HCl8VDNk0eR'B;B'
+RNH3lPJ8NCVkRD0'BeB'H;
+R08NN
+8;N3HR#8HlCkVND'0Re'BB;H
+NRJ3PlV8CN0kDRB'eB
+';HORND
+s;N3HR#8HlCkVND'0Rt'h7;H
+NRJ3PlV8CN0kDRh't7
+';N3HRl Ns_$N#MsO_C0#CR
+4;N#HR$NM_#O$ME;R4
+#HRO;Ds
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+#HRD8FN;H
+NRH3#lV8CN0kDRh't7
+';N3HRP8JlCkVND'0Rt'h7;H
+NRN3ls# _$_MOsCC#0;R4
+CHRM
+N;N3HR#8HlCkVND'0Re'BB;H
+NRJ3PlV8CN0kDRB'eB
+';N3HRl Ns_FODOC _MDNLC;R4
+OHRH
+M;N3HR#8HlCkVND'0Rt'h7;R
+HHCMPs;0N
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+NHRD8FN;H
+NRH3#lV8CN0kDRh't7
+';N3HRP8JlCkVND'0Rt'h7;H
+NRM#$_$N#MROE4H;
+RosCOON#H
+M;N3HR#8HlCkVND'0Rhpzp'N;
+HPR3JCl8VDNk0tR'h;7'
+"VRMNFMl;C"RHyVDjCR
+"VR/0Fb/M#$bVDH$b/VoON_.gjjjDn/HPL/E#8/0P83E;8"RHyVD4CR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_ bN38PE"y;RVCHDRN.
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/8#04c4n38PE"y;RVCHDRNd
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/#kMHCoM8E3P8R";yDVHC
+RcNRVR3_H#PDE8R
+4;V/R"F/b0#b$MD$HV/oVbN._OjjjgnH/DLE/P8s/NH30EP"E8;VRyHRDC6V
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8R";yDVHC
+RnNRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
+V3RRHP#_ER8D4V;
+RE"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E;8"RHyVDUCR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P"E8;VRyHRDCgV
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNs_NOE3P8R";yDVHCjR4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_MOF0DsF_ONs38PE"y;RVCHDR
+4.NRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCNs_sPO3E;8"RHyVD4CRdV
+NRHR3#E_P84DR;R
+MRaqp _)qqXu Rs#0NG0H_RHFuv)Q;O
+NRG3C0MCsNCD_8_HVMCNlR0"#sHN0GF_H"N;
+PDR3ClV_NFOsMCNlRm"Q"N;
+PHR3#Hbsl;R4
+RNP3bH#N48R;P
+NRH3#lV8CN0kDRC'8PsbF,P8COMDs,P8CF;C'
+RNP3$bE_0#HCQR"mwAz"N;
+PHR3FH_PC4IR;P
+NRE3P8#D_ RHb4N;
+PCR3Gs0CM_NDPHCsD_FoMCNlR0"#sHN0GF_H"N;
+PCR3Gs0CM_NDPDE8_lMNC#R"00sNHHG_F
+";LNRb8;HF
+RNH3bH#N48R;H
+NRM#$_H0s#00NC;R4
+sFRCkoF0N;
+H#R3HCl8VDNk0hR'z'pp;R
+FOLFlF;k0
+RNH3l#H8NCVkRD0'phzp
+';F8R8HCFso0Fk;H
+NRH3#lV8CN0kDRz'hp;p'
+8HRNH0NMN;
+H#R3HCl8VDNk0hR'z'pp;H
+NRJ3PlV8CN0kDRh't7
+';H8R8HNF80MNH;H
+NRH3#lV8CN0kDRz'hp;p'
+FHRCN;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'BeB'H;
+R0FkO;D
+RNH3l#H8NCVkRD0'phzp
+';N3HRP8JlCkVND'0Rt'h7;R
+HFOk0DM CNN;
+H#R3HCl8VDNk0eR'B;B'
+RNH3lPJ8NCVkRD0'BeB'H;
+ROFCDM CNH;
+ROHMD
+ ;N3HR#8HlCkVND'0Rhpzp'N;
+HPR3JCl8VDNk0tR'h;7'
+HHRM ODC;MN
+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+NHRsCC#0N;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'7th'N;
+HlR3N_s NM#$OC_s#RC04H;
+RC#s#;C0
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+RNH3slN $_#MsO_C0#CR
+4;FVR8VN_80FN_k
+0;
+"VRMNFMl;C"RHyVDjCR
+"VR/0Fb/M#$bVDH$b/VoON_.gjjjDn/HPL/E#8/0P83E;8"RHyVD4CR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_ bN38PE"y;RVCHDRN.
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/8#04c4n38PE"y;RVCHDRNd
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/#kMHCoM8E3P8R";yDVHC
+RcNRVR3_H#PDE8R
+4;V/R"F/b0#b$MD$HV/oVbN._OjjjgnH/DLE/P8s/NH30EP"E8;VRyHRDC6V
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8R";yDVHC
+RnNRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
+V3RRHP#_ER8D4V;
+RE"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E;8"RHyVDUCR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P"E8;VRyHRDCgV
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNs_NOE3P8R";yDVHCjR4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_MOF0DsF_ONs38PE"y;RVCHDR
+4.NRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCNs_sPO3E;8"RHyVD4CRdV
+NRHR3#E_P84DR;R
+MRaqp _)qqXu Rs#0NG0H__HFVuVR);Qv
+RNO30CGCNsMD8_CHMV_NRlC"s#0NG0H_"HF;O
+NR 3#HPb_E_8DkR#C4N;
+PHR3#Hbsl;R4
+RNP3bH#N48R;P
+NRE3b$H_#0"CRQzmAw
+";N3PRCCG0sDMN_sPCHoDF_lMNC#R"00sNHHG_F
+";N3PRCCG0sDMN_8PEDN_Ml"CR#N0s0_HGH;F"
+RNP3l#H8NCVkRD0'P8Cb,Fs8OCPD,sM8FCPC
+';N3PRHPF_HRCI4N;
+PPR3E_8D#b HR
+4;LNRb8;HF
+RNH3bH#N48R;H
+NRM#$_H0s#00NC;R4
+sFRCkoF0N;
+H#R3HCl8VDNk0hR'z'pp;R
+FOLFlF;k0
+RNH3l#H8NCVkRD0'phzp
+';F8R8HCFso0Fk;H
+NRH3#lV8CN0kDRz'hp;p'
+8HRNH0NMN;
+H#R3HCl8VDNk0hR'z'pp;H
+NRJ3PlV8CN0kDRh't7
+';H8R8HNF80MNH;H
+NRH3#lV8CN0kDRz'hp;p'
+FHRCN;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'BeB'H;
+R0FkO;D
+RNH3l#H8NCVkRD0'phzp
+';N3HRP8JlCkVND'0Rt'h7;H
+NRM#$_OH#D FOR
+4;HkRF0 ODC;MN
+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+FHRC ODC;MN
+HHRM OD;H
+NRH3#lV8CN0kDRz'hp;p'
+RNH3lPJ8NCVkRD0'7th'N;
+H$R#M#_HOODF ;R4
+HHRM ODC;MN
+RNH3l#H8NCVkRD0'BeB'N;
+HPR3JCl8VDNk0eR'B;B'
+NHRsCC#0N;
+H#R3HCl8VDNk0tR'h;7'
+RNH3lPJ8NCVkRD0'7th'N;
+HlR3N_s NM#$OC_s#RC04H;
+RC#s#;C0
+RNH3l#H8NCVkRD0'7th'N;
+HPR3JCl8VDNk0tR'h;7'
+RNH3slN $_#MsO_C0#CR
+4;FVR8VN_80FN_k
+0;
+"VRMNFMl;C"RHyVDjCR
+"VR/0Fb/M#$bVDH$b/VoON_.gjjjDn/HPL/E#8/0P83E;8"RHyVD4CR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_ bN38PE"y;RVCHDRN.
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/8#04c4n38PE"y;RVCHDRNd
+V3RRHP#_ER8D4V;
+RF"/b#0/$DMbH/V$VNbo_jO.jngj/LDH/8PE/#kMHCoM8E3P8R";yDVHC
+RcNRVR3_H#PDE8R
+4;V/R"F/b0#b$MD$HV/oVbN._OjjjgnH/DLE/P8s/NH30EP"E8;VRyHRDC6V
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8R";yDVHC
+RnNRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOLsFN8s_8HsPC_0CM38PE"y;RVCHDRN(
+V3RRHP#_ER8D4V;
+RE"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E;8"RHyVDUCR
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P"E8;VRyHRDCgV
+NRHR3#E_P84DR;R
+V"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNs_NOE3P8R";yDVHCjR4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8R";yDVHC4R4
+RNVR#3H_8PED;R4
+"VR/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_MOF0DsF_ONs38PE"y;RVCHDR
+4.NRVR3_H#PDE8R
+4;V/R"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCNs_sPO3E;8"RHyVD4CRdV
+NRHR3#E_P84DR;h
+eqRv 'sIF o3PNs_8HsPC3ELCN;P'RPyRHRCIHj8R
+qehv' RI Fs3NPo_H8sP3CsMDC0H'#0;RRyPIHCRRH84h
+eqRv 'sIF o3PNC3LE'NP;RRyPIHCRRH8.h
+eqRv 'sIF o3PNF_OMF0sDC3M0#DH0R';yHRPCHIR8
+Rdevhq IR'F3s P_oNO0FMs3FDLNCEPR';yHRPCHIR8
+Rc@
+
+
+ftell;
+@ERMRI FsRNPo_H8sPRCsMDC0H;#0
+RNP3_H##sFkO4CR;P
+NRH3DMFCMR;n(
+RNP3PH#ER8D4N;
+PHR3#E_P84DR;P
+NRs3FHNohl"CRP_oN8PsHC;s"
+RNP#_$Mb#sCCCsPR
+4;N3PRNNDlON_b0OE_F0kMR
+4;N3PRFosHPIHCMCNlRC'LE'NP;P
+NRN3E#l0HHRMo4N;
+PkR3HD_M_N#DOd Rc6cn4F;
+RMDHCF_OkCM0sH_#o;_j
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FDCHM_kOFMs0C_o#H_
+4;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+DFRH_MCOMFk0_Cs#_Ho.N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FHRDMOC_F0kMC#s_Hdo_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+RMDHCF_OkCM0sH_#o;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FDCHM_kOFMs0C_o#H_
+6;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+DFRH_MCOMFk0_Cs#_HonN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FHRDMOC_F0kMC#s_H(o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+RMDHCF_OkCM0sH_#o;_U
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+H8_D$OMFk0_Cs4N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRM"H"H;
+R$8D_kOFMs0C_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";F#RP$_MO#00NC;_.
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$O0_#N_0C6N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RP$_MO#00NC;_d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$O0_#N_0CnN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RP$_MO#00NC;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$O0_#N_0C4N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RP$_MO#00NC;_j
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$O0_#N_0C.N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RE$_MO#00NC;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$O0_#N_0CjN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RE$_MO#00NC;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$O0_#N_0C4N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F#RE$_MO#00NC;_d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$O0_#N_0CnN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFRODMkl_kOFMs0C_o#H_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+OFRFlDkMF_OkCM0sH_#o;_4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FOkFDlOM_F0kMC#s_H.o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+RDOFk_lMOMFk0_Cs#_HodN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFRODMkl_kOFMs0C_o#H_
+c;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+OFRFlDkMF_OkCM0sH_#o;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FOkFDlOM_F0kMC#s_Hno_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+RDOFk_lMOMFk0_Cs#_Ho(N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFRODMkl_kOFMs0C_o#H_
+U;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+OFRFlDkMF_OkCM0sH_#o;_g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_U
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_(
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_n
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_.
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FPM#$OF_OkCM0s;_j
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_U
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_(
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_n
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_c
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_.
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FEM#$OF_OkCM0s;_j
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F8C_#0#_P$_MOOMFk0;Cs
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FP$_#M
+O;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+EFR_M#$ON;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";F_RECLMND#C_H
+o;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+PFR_NCML_DC#;Ho
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+HsCC#0H_bM;_O
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRH;M"
+kFRM8n_DO$_F0kMCjs__
+G;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+8FR_0#C_$E#MOO_F0kMC
+s;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+OHRDb _HOM_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;M
+oRgkM_$E#MOO_F0kMC0sDgN;
+MsR30MD_CM0_NRlC"NPo_H8sP_Csk0MH3gkM_$E#MOO_F0kMC0sDg
+";oOMRDb _HOM_;M
+NRD3OFRO "NPo| OD_MbH"N;
+MOR3D FO_oC8CsR"H"#C;M
+NR#3H_FODO4 R;M
+oRgkM_$P#MOO_F0kMC0sDgN;
+MsR30MD_CM0_NRlC"NPo_H8sP_Csk0MH3gkM_$P#MOO_F0kMC0sDg
+";okMRM8n_DO$_F0kMCjs__
+G;N3MRs_0DM_C0MCNlR "7p_qY) 1aC_MG30\k_Mn8_D$OMFk0_Csj"_G;M
+oR$P#M#O_0CN0_GMC0__.#kJlG
+N;N3MRs_0DM_C0MCNlRo"PNs_8HsPC_HkM0#3P$_MO#00NCC_MG.0__l#Jk"GN;M
+oRCP_MDNLCH_#o__4j__jjj_o_FH_cN;
+MsR30MD_CM0_NRlC"NPo_H8sP_Csk0MH3CP_MDNLCH_#o__4j__jjj_o_FH_c
+";oEMR_NCML_DC#_Ho4__jj__joHj__;Fc
+RNM3Ds0_0MC_lMNCPR"o8N_sCHPsM_kHE03_NCML_DC#_Ho4__jj__joHj__"Fc;M
+oR$E#M#O_0CN0_jd__jj__j_o_
+j;N3MRs_0DM_C0MCNlRo"PNs_8HsPC_HkM0#3E$_MO#00NC__dj__jjo__j"_j;R
+s@d@4:U46:4c:66U::$E#MOO_F0kMCgsr:Rj9fcc4Ud(:Ugg.UpRqaq )_ quXMRO0g.c66j_6_66qqqqRHbsl#RE$_MOOMFk0rCsjS9
+sFCokE0=#O$M_kOFMs0C_fjRmn4(j6:d6j(dRO
+SF=k0EM#$OF_OkCM0sF_Okj0r9mRf4jU.jg:djU.dRO
+SDO =Db _HOM_
+NS80=NNEM#$OF_OkCM0sR_jf4Q4(:njd(Udg
+URS08NNEO=#O$M_kOFMs0C_GMC0__4#kJlGfNRQj.g6dj:g4(4USR
+#sOD!_=t.R_Hf4Qcc:U(d.Ugg
+URSF#DN=8!k_MgEM#$OF_OkCM0sgD0R.fQnndc:UdUjR(U;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;4
+ARj4,y?5jV2:0RA;
+.,R4j5y!j:?V0;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MRgN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"6"NN;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$E#MOO_F0kMC4sr9s
+SCkoF0#=E$_MOOMFk0_Cs4mRf4j(n:gd66R6(
+FSOkE0=#O$M_kOFMs0C_kOF09r4R4fmUjc(:jdg6RjU
+DSO D=O H_bM
+_OS08NNEN=#O$M_kOFMs0C_f4RQ(44ndj:UncjUSR
+8NN0O#=E$_MOOMFk0_CsM0CG_#4_JGlkNQRf.6gjjg:d(U44R#
+SO!Ds=.t__fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MEg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$E#MOO_F0kMCOs_Frk0jf9RQ.4Ujdj:gdj.U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;6U
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgEM#$OF_OkCM0sgD0"s;
+R4@@d6:4U::c4:6U6#:E$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHElR#O$M_kOFMs0Cr
+.9SosCF=k0EM#$OF_OkCM0sR_.f(m4ndj:6d6U(SR
+O0Fk=$E#MOO_F0kMCOs_Frk0.f9Rm(4Ucdj:g(j(USR
+O=D O_D b_HMO8
+SNN0N=$E#MOO_F0kMC.s_R4fQ4j(n:cdUdRdU
+NS80=NOEM#$OF_OkCM0sC_MG40__l#JkRGNfgQ.j:6jd4g(4
+URSD#Ost!=_H._RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$E#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHEM=#O$M_kOFMs0C_kOF09r4R4fQUjc(:jdg6RjU;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MR(N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$E#MOO_F0kMCdsr9s
+SCkoF0#=E$_MOOMFk0_CsdmRf4j(n:(d64Rj(
+FSOkE0=#O$M_kOFMs0C_kOF09rdR4fmgjj4:4dgjRcU
+DSO D=O H_bM
+_OS08NNEN=#O$M_kOFMs0C_fdRQ(44ndj:UjcnUSR
+8NN0O#=E$_MOOMFk0_CsM0CG_#4_JGlkNQRf.6gjjg:d(U44R#
+SO!Ds=.t__fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MEg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$E#MOO_F0kMCOs_Frk0.f9RQ(4Ucdj:g(j(U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;6n
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgEM#$OF_OkCM0sgD0"s;
+R4@@d6:4U::c4:6U6#:E$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHElR#O$M_kOFMs0Cr
+c9SosCF=k0EM#$OF_OkCM0sR_cf(m4ndj:6j(.USR
+O0Fk=$E#MOO_F0kMCOs_Frk0cf9Rm.4gUdj:g44dUSR
+O=D O_D b_HMO8
+SNN0N=$E#MOO_F0kMCcs_R4fQ4j(n:cdUUR(U
+NS80=NOEM#$OF_OkCM0sC_MG40__l#JkRGNfgQ.j:6jd4g(4
+URSD#Ost!=_H._RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$E#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHEM=#O$M_kOFMs0C_kOF09rdR4fQgjj4:4dgjRcU;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MR6N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$E#MOO_F0kMC6sr9s
+SCkoF0#=E$_MOOMFk0_Cs6mRf4j(n:nd66R(U
+FSOkE0=#O$M_kOFMs0C_kOF09r6R4fmgj66:4dg6RUU
+DSO D=O H_bM
+_OS08NNEN=#O$M_kOFMs0C_f6RQ(44ndj:Uc64USR
+8NN0O#=E$_MOOMFk0_CsM0CG_#4_JGlkNQRf.6gjjg:d(U44R#
+SO!Ds=.t__fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MEg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$E#MOO_F0kMCOs_Frk0cf9RQ.4gUdj:g44dU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;6c
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgEM#$OF_OkCM0sgD0"s;
+R4@@d6:4U::c4:6U6#:E$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHElR#O$M_kOFMs0Cr
+n9SosCF=k0EM#$OF_OkCM0sR_nf(m4ndj:6n(.USR
+O0Fk=$E#MOO_F0kMCOs_Frk0nf9RmU4g.dj:g64UUSR
+O=D O_D b_HMO8
+SNN0N=$E#MOO_F0kMCns_R4fQ4j(n:6dUcR4U
+NS80=NOEM#$OF_OkCM0sC_MG40__l#JkRGNfgQ.j:6jd4g(4
+URSD#Ost!=_H._RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$E#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHEM=#O$M_kOFMs0C_kOF09r6R4fQgj66:4dg6RUU;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MRdN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$E#MOO_F0kMC(sr9s
+SCkoF0#=E$_MOOMFk0_Cs(mRf4j(n:(d6jRjj
+FSOkE0=#O$M_kOFMs0C_kOF09r(R.fmjjjg:.dg4R.U
+DSO D=O H_bM
+_OS08NNEN=#O$M_kOFMs0C_f(RQ(44ndj:UU6nUSR
+8NN0O#=E$_MOOMFk0_CsM0CG_#4_JGlkNQRf.6gjjg:d(U44R#
+SO!Ds=.t__fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MEg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$E#MOO_F0kMCOs_Frk0nf9RQU4g.dj:g64UU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;6.
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgEM#$OF_OkCM0sgD0"s;
+R4@@d6:4U::c4:6U6#:E$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHElR#O$M_kOFMs0Cr
+U9SosCF=k0EM#$OF_OkCM0sR_Uf(m4ndj:6cc(USR
+O0Fk=$E#MOO_F0kMCOs_Frk0Uf9Rmd.jndj:gg.dUSR
+O=D O_D b_HMO8
+SNN0N=$E#MOO_F0kMCUs_R4fQ4j(n:6dUgR6U
+NS80=NOEM#$OF_OkCM0sC_MG40__l#JkRGNfgQ.j:6jd4g(4
+URSD#Ost!=_H._RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$E#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHEM=#O$M_kOFMs0C_kOF09r(R.fQjjjg:.dg4R.U;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MR4N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d4:6Uc6:4U::6EM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.d6gUq_66bqRsRHlEM#$OF_OkCM0s9rg
+CSso0Fk=$E#MOO_F0kMCgs_R4fm(:njdj6n4
+URS OD= OD_MbH_SO
+8NN0N#=E$_MOOMFk0_CsgQRf4n4(jg:d(U44R8
+SNO0N=$E#MOO_F0kMCMs_C_G04J_#lNkGR.fQgjj6:(dg4R4U
+OS#D=s!t__.HQRfcU4c(U:dgU.gR#
+SD8FN!M=kg#_E$_MOOMFk0DCs0fgRQd.ncdn:U(UjUSR
+O=HMEM#$OF_OkCM0sF_OkU0r9QRf.njdjg:d.UdgRo;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OH6MRjN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"6N;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_E$_MOOMFk0DCs0;g"
+@sR@:4d.:n(cn:.(::6PM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.6cgjn_nnUn_URUUblsHR$P#MOO_F0kMCjsr9s
+SCkoF0#=P$_MOOMFk0_CsjmRf4j(n:nd6jRjU
+FSOkP0=#O$M_kOFMs0C_kOF09rjR.fm(c6d:jdg.RdU
+DSO D=O H_bM
+_OS08NNPN=#O$M_kOFMs0C_fjRQ(44ndj:Ugd(USR
+8NN0L_=8#_C0EM#$OF_OkCM0sQRf.g4jcU:ddU(gR8
+SNO0N=$P#MOO_F0kMCMs_C_G04J_#lNkGR.fQUg.d:(dg4R4U
+OS#D=s!tn_4_fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MPg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(;UR
+RobsFCok
+0;oObRF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o#bRO;Ds
+Rob#NDF8A;
+4,R444y5?5j*j:?V0!2:fRj2;.
+ARj4,y4!5??5jV2:0:R02;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCPR"#O$M_kOFMs0C"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRN_MbOMFk0_CsV4VR;H
+NRD3N#O0_ERHMc
+g;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnUnU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3M#$OC_s#RC0"PM:o8N_sCHPsM_kHk03MPg_#O$M_kOFMs0CD"0g;R
+s@d@4:(.n:.c:n6(::$P#MOO_F0kMCgsr:Rj9fcc4Ud(:Ugg.UpRqaq )_ quXMRO0g.6c6._q_6qqjjqRHbsl#RP$_MOOMFk0rCs4S9
+sFCokP0=#O$M_kOFMs0C_f4Rmn4(j6:dcc4cRO
+SF=k0PM#$OF_OkCM0sF_Ok40r9mRf.j(Ucg:djU6jRO
+SDO =Db _HOM_
+NS80=NNPM#$OF_OkCM0sR_4f4Q4(:njdjUcn
+URS08NNPO=#O$M_kOFMs0C_GMC0__4#kJlGfNRQ..Uddg:g4(4USR
+#sOD!_=t4Hn_RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$P#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHPM=#O$M_kOFMs0C_kOF09rjR.fQ(c6d:jdg.RdU;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OHcMRUN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_P$_MOOMFk0DCs0;g"
+@sR@:4d.:n(cn:.(::6PM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$P#MOO_F0kMC.sr9s
+SCkoF0#=P$_MOOMFk0_Cs.mRf4j(n:6d6cRjc
+FSOkP0=#O$M_kOFMs0C_kOF09r.R.fmUcj(:jdg(R(U
+DSO D=O H_bM
+_OS08NNPN=#O$M_kOFMs0C_f.RQ(44ndj:UdcdUSR
+8NN0O#=P$_MOOMFk0_CsM0CG_#4_JGlkNQRf.dU.gg:d(U44R#
+SO!Ds=4t_nR_Hf4Qcc:U(d.Ugg
+URSF#DN=8!k_MgPM#$OF_OkCM0sgD0R.fQnndc:UdUjR(U
+HSOM#=P$_MOOMFk0_CsO0FkrR49f(Q.U:jcd6gjj;UR
+RobsFCok
+0;oObRF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNO0N;b
+oRD#Oso;
+bDR#F;N8
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#MOO_F0kMC;s"
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3NbF_OkCM0sV_VR
+4;N3HRN0D#_HOEM(Rc;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRN"6N;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+H#R3$_MOsCC#0MR":NPo_H8sP_Csk0MH3gkM_$P#MOO_F0kMC0sDg
+";s@R@4.d:nc(::(.n:P6:#O$M_kOFMs0Crjg:9cRf4(cU:gdU.RgUq pa)qq_uR XO.M06.gc_66qqj_qqbjRsRHlPM#$OF_OkCM0s9rd
+CSso0Fk=$P#MOO_F0kMCds_R4fm(:njdn64U
+cRSkOF0#=P$_MOOMFk0_CsO0FkrRd9fUm.d:ccdjg4c
+URS OD= OD_MbH_SO
+8NN0N#=P$_MOOMFk0_CsdQRf4n4(jU:dcUnjR8
+SNO0N=$P#MOO_F0kMCMs_C_G04J_#lNkGR.fQUg.d:(dg4R4U
+OS#D=s!tn_4_fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MPg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$P#MOO_F0kMCOs_Frk0.f9RQj.U(dc:g(j(U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$OF_OkCM0s
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;cn
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgPM#$OF_OkCM0sgD0"s;
+R4@@dn:.(::c.:n(6#:P$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHPlR#O$M_kOFMs0Cr
+c9SosCF=k0PM#$OF_OkCM0sR_cf(m4ndj:66.gcSR
+O0Fk=$P#MOO_F0kMCOs_Frk0cf9Rmn.U4dc:g44dUSR
+O=D O_D b_HMO8
+SNN0N=$P#MOO_F0kMCcs_R4fQ4j(n:cdUUR(U
+NS80=NOPM#$OF_OkCM0sC_MG40__l#JkRGNfUQ..:dgd4g(4
+URSD#Ost!=__4nHQRfcU4c(U:dgU.gR#
+SD8FN!M=kg#_P$_MOOMFk0DCs0fgRQd.ncdn:U(UjUSR
+O=HMPM#$OF_OkCM0sF_Okd0r9QRf.cUdcg:d4UjcRo;
+bCRso0Fk;b
+oRkOF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+O;o#bRO;Ds
+Rob#NDF8o;
+bHROMA;
+4,R44.y5?5j*j:?V0!2:fRj2;.
+ARj4,y.!5??5jV2:0:R02;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCPR"#O$M_kOFMs0C"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRN_MbOMFk0_CsV4VR;H
+NRD3N#O0_ERHMc
+6;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNN"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3M#$OC_s#RC0"PM:o8N_sCHPsM_kHk03MPg_#O$M_kOFMs0CD"0g;R
+s@d@4:(.n:.c:n6(::$P#MOO_F0kMCgsr:Rj9fcc4Ud(:Ugg.UpRqaq )_ quXMRO0g.6c6._q_6qqjjqRHbsl#RP$_MOOMFk0rCs6S9
+sFCokP0=#O$M_kOFMs0C_f6Rmn4(j6:d.cU(RO
+SF=k0PM#$OF_OkCM0sF_Ok60r9mRf.UUUcg:d4U6URO
+SDO =Db _HOM_
+NS80=NNPM#$OF_OkCM0sR_6f4Q4(:njd4U6c
+URS08NNPO=#O$M_kOFMs0C_GMC0__4#kJlGfNRQ..Uddg:g4(4USR
+#sOD!_=t4Hn_RcfQ4(cU:gdU.RgU
+DS#F!N8=gkM_$P#MOO_F0kMC0sDgQRf.cndnU:dUUj(RO
+SHPM=#O$M_kOFMs0C_kOF09rcR.fQUcn4:4dgdR4U;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Oo;
+bOR#D
+s;o#bRD8FN;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.5Vj?::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MOOMFk0"Cs;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3MOb_F0kMCVs_V;R4
+RNH3#ND0E_OHcMRcN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Nj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HR#O$M_#sCC"0RMo:PNs_8HsPC_HkM0M3kg#_P$_MOOMFk0DCs0;g"
+@sR@:4d.:n(cn:.(::6PM#$OF_OkCM0s:rgjf9RcU4c(U:dgU.gRaqp _)qqXu R0OM.c6g.q_66qq_jRqjblsHR$P#MOO_F0kMCnsr9s
+SCkoF0#=P$_MOOMFk0_CsnmRf4j(n:jd64R4n
+FSOkP0=#O$M_kOFMs0C_kOF09rnR.fmgc46:4dgUR6U
+DSO D=O H_bM
+_OS08NNPN=#O$M_kOFMs0C_fnRQ(44ndj:U46cUSR
+8NN0O#=P$_MOOMFk0_CsM0CG_#4_JGlkNQRf.dU.gg:d(U44R#
+SO!Ds=4t_nR_Hf4Qcc:U(d.Ugg
+URSF#DN=8!k_MgPM#$OF_OkCM0sgD0R.fQnndc:UdUjR(U
+HSOM#=P$_MOOMFk0_CsO0FkrR69fUQ.U:Ucd6g4U;UR
+RobsFCok
+0;oObRF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNO0N;b
+oRD#Oso;
+bDR#F;N8
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#MOO_F0kMC;s"
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3NbF_OkCM0sV_VR
+4;N3HRN0D#_HOEMdRc;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRN"6N;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+H#R3$_MOsCC#0MR":NPo_H8sP_Csk0MH3gkM_$P#MOO_F0kMC0sDg
+";s@R@4.d:nc(::(.n:P6:#O$M_kOFMs0Crjg:9cRf4(cU:gdU.RgUq pa)qq_uR XO.M06.gc_66qqj_qqbjRsRHlPM#$OF_OkCM0s9r(
+CSso0Fk=$P#MOO_F0kMC(s_R4fm(:njdc6j4
+cRSkOF0#=P$_MOOMFk0_CsO0FkrR(9fgm.c:.cd4g..
+URS OD= OD_MbH_SO
+8NN0N#=P$_MOOMFk0_Cs(QRf4n4(jU:d6UnUR8
+SNO0N=$P#MOO_F0kMCMs_C_G04J_#lNkGR.fQUg.d:(dg4R4U
+OS#D=s!tn_4_fHRQcc4Ud(:Ugg.USR
+#NDF8k!=MPg_#O$M_kOFMs0CDR0gfnQ.d:cndjUU(
+URSMOH=$P#MOO_F0kMCOs_Frk0nf9RQ4.g6dc:g64UU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.j?5?0V:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$OF_OkCM0s
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;c.
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"N6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgPM#$OF_OkCM0sgD0"s;
+R4@@dn:.(::c.:n(6#:P$_MOOMFk0rCsg9:jR4fcc:U(d.UggqURp)a qu_q OXRM60.g_c.6qq6_qqjjsRbHPlR#O$M_kOFMs0Cr
+U9SosCF=k0PM#$OF_OkCM0sR_Uf(m4ndj:6U4ncSR
+O0Fk=$P#MOO_F0kMCOs_Frk0Uf9Rmn.ggdc:gg.dUSR
+O=D O_D b_HMO8
+SNN0N=$P#MOO_F0kMCUs_R4fQ4j(n:6dUgR6U
+NS80=NOPM#$OF_OkCM0sC_MG40__l#JkRGNfUQ..:dgd4g(4
+URSD#Ost!=__4nHQRfcU4c(U:dgU.gR#
+SD8FN!M=kg#_P$_MOOMFk0DCs0fgRQd.ncdn:U(UjUSR
+O=HMPM#$OF_OkCM0sF_Ok(0r9QRf..gccg:d.U4.Ro;
+bCRso0Fk;b
+oRkOF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+O;o#bRO;Ds
+Rob#NDF8o;
+bHROMA;
+4,R44.y5?5j*j:?V0!2:fRj2;.
+ARj4,y.!5??5jV2:0:R02;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCPR"#O$M_kOFMs0C"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRN_MbOMFk0_CsV4VR;H
+NRD3N#O0_ERHMc
+4;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNN"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3M#$OC_s#RC0"PM:o8N_sCHPsM_kHk03MPg_#O$M_kOFMs0CD"0g;R
+s@d@4:(.n:.c:n6(::$P#MOO_F0kMCgsr:Rj9fcc4Ud(:Ugg.UpRqaq )_ quXMRO0g.6d6U_qR6qblsHR$P#MOO_F0kMCgsr9s
+SCkoF0#=P$_MOOMFk0_CsgmRf4j(n:dd6URdn
+DSO D=O H_bM
+_OS08NNPN=#O$M_kOFMs0C_fgRQ(44ndj:g4(4USR
+8NN0O#=P$_MOOMFk0_CsM0CG_#4_JGlkNQRf.dU.gg:d(U44R#
+SO!Ds=4t_nR_Hf4Qcc:U(d.Ugg
+URSF#DN=8!k_MgPM#$OF_OkCM0sgD0R.fQnndc:UdUjR(U
+HSOM#=P$_MOOMFk0_CsO0FkrRU9fgQ.n:gcddg.g;UR
+RobsFCok
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NO
+Rob#sOD;b
+oRF#DN
+8;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$OF_OkCM0s
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3bNM_kOFMs0C_RVV4N;
+HNR3D_#0OMEHR;cj
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"66NN
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR$3#MsO_C0#CR:"MP_oN8PsHCks_M3H0k_MgPM#$OF_OkCM0sgD0"s;
+R4@@d(:g:gc:(::6OkFDlOM_F0kMC#s_Hgor:Rj9f(d.jdj:g4(4UpRqaq )_ quXVRVUUcg_AAAAsRbHOlRFlDkMF_OkCM0sH_#o9rg
+CSso0Fk=DOFk_lMOMFk0_Cs#_HogmRf4j(n:jd(6Rd4
+DSO D=O H_bM
+_OS08NNkN=MO._FlDkMF_OkCM0sC_MGO0_FFlLkg0r9QRf.g(c.g:d(U44R8
+SNL0N=4kMjF_ODMkl_kOFMs0C_o#HDg0FRdfQ.j(j:(dg4R4U
+OS#D=s!OkFDlOM_F0kMCMs_C_G0jJ_#lNkG_44_R4fQg6d6:gdU.RgU;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R4j5y!4j?5?0V:22:VRN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CROkFDlOM_F0kMC#s_H;o"
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMCgGR;H
+NRO3#DVs_V;R4
+RNH3#ND0E_OHdMR(N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blLR"L"LL;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";s@R@4gd:(::cg6(::DOFk_lMOMFk0_Cs#rHog9:jR.fd(:jjd4g(4qURp)a qu_q VXRVjd(_UUjjsRbHOlRFlDkMF_OkCM0sH_#o9rU
+CSso0Fk=DOFk_lMOMFk0_Cs#_HoUmRf4j(n:UdnjR(4
+DSO D=O H_bM
+_OS08NNkN=MO._FlDkMF_OkCM0sC_MGO0_FFlLkU0r9QRf.g(c.g:d(U44R8
+SNL0N=4kMjF_ODMkl_kOFMs0C_o#HDg0FRdfQ.j(j:(dg4R4U
+NS80=NOOkFDlOM_F0kMCMs_C_G0jJ_#lNkG_44_R4fQg6d6:(dg4R4U;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;A44R,!jy55.?4j?5?0V:22:0:R02;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCOR"FlDkMF_OkCM0sH_#o
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;RU
+RNH3#ND0E_OHdMRnN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blUR"j"Uj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9Rdj.(jg:d(U44Raqp _)qqXu RdVV(Uj_jRUjblsHRDOFk_lMOMFk0_Cs#rHo(S9
+sFCokO0=FlDkMF_OkCM0sH_#oR_(f(m4ndj:(g.4nSR
+O=D O_D b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrR(9f(Q..:..d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+8NN0OF=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:g4(4U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+ARj4,y.!5??545Vj?::02002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG(N;
+HNR3D_#0OMEHR;d6
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UUjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";s@R@4gd:(::cg6(::DOFk_lMOMFk0_Cs#rHog9:jR.fd(:jjd4g(4qURp)a qu_q VXRVgUcUA_AAbARsRHlOkFDlOM_F0kMC#s_Hnor9s
+SCkoF0F=ODMkl_kOFMs0C_o#H_fnRmn4(j(:dj4njRO
+SDO =Db _HOM_
+NS80=NNk_M.OkFDlOM_F0kMCMs_C_G0OLFlFrk0nf9RQ..(.d.:g4(4USR
+8NN0LM=k4Oj_FlDkMF_OkCM0sH_#oFD0gQRfdj.(jg:d(U44R#
+SO!Ds=DOFk_lMOMFk0_CsM0CG_#j_JGlkN__44QRf46gd6U:dgU.gRo;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;A44R,!jy554?j:?V0V2:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGnN;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHMd
+c;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRLLLL"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+@sR@:4dgc(:::g(6F:ODMkl_kOFMs0C_o#Hrjg:9dRf.j(j:(dg4R4Uq pa)qq_uR XVcVUgAU_ARAAblsHRDOFk_lMOMFk0_Cs#rHo6S9
+sFCokO0=FlDkMF_OkCM0sH_#oR_6f(m4ndj:ndgd4SR
+O=D O_D b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrR69fnQ.g:6.d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?545Vj?::02V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+6;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;dd
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9R4j(n:cdn(Rjgq pa)qq_uR XVcVUgAU_ARAAblsHRDOFk_lMOMFk0_Cs#rHocS9
+sFCokO0=FlDkMF_OkCM0sH_#oR_cf(m4ndj:njc(gSR
+O=D O_D b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrRc9fnQ.g:6.d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?545Vj?::02V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+c;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;d.
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9R4j(n:ddncRdgq pa)qq_uR XVcVUgAU_ARAAblsHRDOFk_lMOMFk0_Cs#rHodS9
+sFCokO0=FlDkMF_OkCM0sH_#oR_df(m4ndj:nddcgSR
+O=D O_D b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrRd9fnQ.n:U.d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?545Vj?::02V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+d;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;d4
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9R4j(n:6dnURggq pa)qq_uR XVcVUgAU_ARAAblsHRDOFk_lMOMFk0_Cs#rHo.S9
+sFCokO0=FlDkMF_OkCM0sH_#oR_.f(m4ndj:ng6UgSR
+O=D O_D b_HMO8
+SNN0N=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrR.9fnQ.n:U.d4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?545Vj?::02V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+.;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;dj
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4::g(c(:g:O6:FlDkMF_OkCM0sH_#o:rgjf9Rdj.(jg:d(U44Raqp _)qqXu RUVVc_gUAAAARHbslFRODMkl_kOFMs0C_o#Hr
+49SosCF=k0OkFDlOM_F0kMC#s_H4o_R4fm(:njdjnU(
+4RS OD= OD_MbH_SO
+8NN0NM=k.F_ODMkl_kOFMs0C_GMC0F_OlkLF09r4R.fQj.44:(dg4R4U
+NS80=NLkjM4_DOFk_lMOMFk0_Cs#DHo0RFgf.Qd(:jjd4g(4
+URSD#OsO!=FlDkMF_OkCM0sC_MGj0__l#Jk_GN4R_4fgQ4d:66d.Ugg;UR
+RobsFCok
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;4
+ARj4,y4!5??5jV2:0:RV2;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCOR"FlDkMF_OkCM0sH_#o
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R4
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEMgR.;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRL"LL;L"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"s;
+R4@@d(:g:gc:(::6OkFDlOM_F0kMC#s_Hgor:Rj9f(d.jdj:g4(4UpRqaq )_ quXVRVUUcg_((((sRbHOlRFlDkMF_OkCM0sH_#o9rj
+CSso0Fk=DOFk_lMOMFk0_Cs#_HojmRf4j(n:UdnnRdU
+DSO D=O H_bM
+_OS08NNON=FlDkMF_OkCM0sH_#oR_jf4Q4(:njd4g(4
+URS08NNkL=M_4jOkFDlOM_F0kMC#s_H0oDFfgRQ(d.jdj:g4(4USR
+#sOD!F=ODMkl_kOFMs0C_GMC0__j#kJlG4N__f4RQd4g6d6:Ugg.U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j554?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGjN;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM.
+U;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR(((("N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+@sR@:4d4:U(cU:4(::6EM#$O0_#Nr0Cj9:nR(f4ndj:n6.j.pRqaq )_ quXVRVd_UnwjwjRHbsl#RE$_MO#00NC9rn
+CSso0Fk=$E#M#O_0CN0_fnRmn4(jn:d..j6RO
+SDO =Db _HOM_
+NS80=N8k_Mn8_D$OMFk0_CsjR_GfnQdn:Ucd4g(4;UR
+RobsFCok
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN08A;
+4,R4j5y!d:?V0;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MO#00NC
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rj
+RNH3#ND0E_OH.MR(N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"V"jj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4:jdj:dc:j6j::$P#M#O_0CN0rnj:9cRf6(.j:(dg4R4Uq pa)qq_uR XVgVcUB_jqb RsRHlPM#$O0_#Nr0CjS9
+sFCokP0=#O$M_N#00jC_R4fm(:njd((j(
+6RS OD= OD_MbH_SO
+8NN0N#=P$_MO#00NCR_jf4Q4(:njd4g(4
+URS08NNPL=#O$M_N#00dC___HPj__j__ojjd_N_fjRQjd.nd(:g4(4USR
+8NN0OM=knD_8$F_OkCM0s__jGQRfdUnncg:d(U44R8
+SN80N=$P#M#O_0CN0_GMC0__.#kJlGfNRQ.c6jd(:g4(4U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,54yd.?5?!V:5V4?:202:.!5?5j*j:?V052:4:?Vf2j22
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#M#O_0CN0"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+n;N3HRN0D#_HOEMnR.;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRO"jN;C"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+@sR@:4dd:jjcj:dj::6PM#$O0_#Nr0Cj9:nRnfdn:Ucd4g(4qURp)a qu_q VXRVUcg_UjjjsRbHPlR#O$M_N#004Cr9s
+SCkoF0#=P$_MO#00NCR_4f(m4ndj:(.cdcSR
+O=D O_D b_HMO8
+SNN0N=$P#M#O_0CN0_fcRQ(44ndj:g4(4USR
+8NN0LM=k4P._#O$M_kOFMs0C_f(RQc.j6dc:g4(4USR
+8NN0OM=k4Pd_#O$M_kOFMs0C_fcRQ4.n(d6:g4(4USR
+8NN08M=knD_8$F_OkCM0s__jGQRfdUnncg:d(U44Ro;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5?!V:55.?4j?5?0V:22:0:202RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$O0_#N"0C;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG6N;
+HNR3D_#0OMEHR;.6
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"Ujjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";s@R@4dd:jcj::jdj:P6:#O$M_N#00jCr:Rn9fj46Udj:6dg(4pRqaq )_ quXVRVd_(4(ww(RHbsl#RP$_MO#00NC9rn
+FSOlkLF0M=knD_8$F_OkCM0s__jGmRf4U6jj6:dg4(dRs
+SCkoF0#=P$_MO#00NCR_nf(m4ndj:(djngSR
+O=D O_D b_HMO8
+SNN0N=#sCCb0_HOM_
+NS80=NL8_D$OMFk0_CsjQRf4n4(j6:dn4c4R8
+SNO0N=$8D_kOFMs0C_f4RQ(44ndj:6j(n4
+R;oObRFFlLk
+0;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNL0N;b
+oR08NN
+O;A44R,5jy.4?5??5jV2:0::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MO#00NC
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rj
+RNH3#ND0E_OH.MRcN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl(R"V"(V;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4:64.:4c:.66::MDHCF_OkCM0sH_#o:rUjf9Rd.nUng:d(U44Raqp _)qqXu RUVVc_gU7777RHbslHRDMOC_F0kMC#s_HUor9s
+SCkoF0H=DMOC_F0kMC#s_HUo_R4fm(:njd((4g
+4RS OD= OD_MbH_SO
+8NN0NM=k4Dj_H_MCOMFk0_Cs#DHo0RFUf.Qd.:d.d4g(4
+URS08NNkL=MD4_H_MCOMFk0_Cs#_HoOLFlFrk0gf9RQUdn.dn:g4(4USR
+#sOD!H=DMOC_F0kMCMs_C_G0jJ_#lNkG_44_R4fQgc4U:gdU.RgU;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R4j5y!4:?V!?5jV2:02
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0sH_#o
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;RU
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEMdR.;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboR8"88;8"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"s;
+R4@@d.:46::c4:.66H:DMOC_F0kMC#s_HUor:Rj9fUdn.dn:g4(4UpRqaq )_ quXVRVUUcg_7777sRbHDlRH_MCOMFk0_Cs#rHo(S9
+sFCokD0=H_MCOMFk0_Cs#_Ho(mRf4j(n:(d(4RUj
+DSO D=O H_bM
+_OS08NNkN=M_4jDCHM_kOFMs0C_o#HDU0FRdfQ...d:(dg4R4U
+NS80=NLk_M4DCHM_kOFMs0C_o#H_lOFL0FkrRU9fnQdU:.nd4g(4
+URSD#OsD!=H_MCOMFk0_CsM0CG_#j_JGlkN__44QRf4Ug4cU:dgU.gRo;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;A44R,!jy5V4?:j!5?0V:2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRH"DMOC_F0kMC#s_H;o"
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC(GR;H
+NRO3#DVs_V;R4
+RNH3#ND0E_OH.MR.N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl8R"8"88;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";s@R@44d:.c6::64.:D6:H_MCOMFk0_Cs#rHoU9:jRnfd6:6nd4g(4qURp)a qu_q VXRVgUcU7_77b7RsRHlDCHM_kOFMs0C_o#Hr
+n9SosCF=k0DCHM_kOFMs0C_o#H_fnRmn4(j(:d.n4gRO
+SDO =Db _HOM_
+NS80=NNkjM4_MDHCF_OkCM0sH_#oFD0UQRfdd...g:d(U44R8
+SNL0N=4kM_MDHCF_OkCM0sH_#oF_OlkLF09r(RdfQnn66:(dg4R4U
+OS#D=s!DCHM_kOFMs0C_GMC0__j#kJlG4N__f4RQ44gUdc:Ugg.U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?54V5:!j:?V0R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCDR"H_MCOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGnN;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM.
+4;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR8888"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+@sR@:4d4:.6c.:46::6DCHM_kOFMs0C_o#HrjU:9dRfnn66:(dg4R4Uq pa)qq_uR XV(Vdjj_UUbjRsRHlDCHM_kOFMs0C_o#Hr
+69SosCF=k0DCHM_kOFMs0C_o#H_f6Rmn4(j(:d.n4gRO
+SDO =Db _HOM_
+NS80=NNkjM4_MDHCF_OkCM0sH_#oFD0UQRfdd...g:d(U44R8
+SNL0N=4kM_MDHCF_OkCM0sH_#oF_OlkLF09rnRdfQnn66:(dg4R4U
+NS80=NODCHM_kOFMs0C_GMC0__j#kJlG4N__f4RQ44gUdc:g4(4U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+ARj4,y.!5??545Vj?::02002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0sH_#o
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R6
+RNH3#ND0E_OH.MRjN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blUR"j"Uj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4:64.:4c:.66::MDHCF_OkCM0sH_#o:rUjf9RdUn.ng:d(U44Raqp _)qqXu RUVVc_gU7777RHbslHRDMOC_F0kMC#s_Hcor9s
+SCkoF0H=DMOC_F0kMC#s_Hco_R4fm(:njdgn(4
+nRS OD= OD_MbH_SO
+8NN0NM=k4Dj_H_MCOMFk0_Cs#DHo0RFUf.Qd.:d.d4g(4
+URS08NNkL=MD4_H_MCOMFk0_Cs#_HoOLFlFrk06f9RQ.dnUdn:g4(4USR
+#sOD!H=DMOC_F0kMCMs_C_G0jJ_#lNkG_44_R4fQgc4U:gdU.RgU;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R4j5y!4:?V!?5jV2:02
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0sH_#o
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rc
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEMgR4;H
+NRD3N#00_DRCM4N;
+HNR3D_#0sCC[O80CR
+4;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboR8"88;8"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"s;
+R4@@d.:46::c4:.66H:DMOC_F0kMC#s_HUor:Rj9f.dnUdn:g4(4UpRqaq )_ quXVRVUUcg_7777sRbHDlRH_MCOMFk0_Cs#rHodS9
+sFCokD0=H_MCOMFk0_Cs#_HodmRf4j(n:ndnnRcn
+DSO D=O H_bM
+_OS08NNkN=M_4jDCHM_kOFMs0C_o#HDU0FRdfQ...d:(dg4R4U
+NS80=NLk_M4DCHM_kOFMs0C_o#H_lOFL0FkrRc9fnQd.:Und4g(4
+URSD#OsD!=H_MCOMFk0_CsM0CG_#j_JGlkN__44QRf4Ug4cU:dgU.gRo;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;A44R,!jy5V4?:j!5?0V:2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRH"DMOC_F0kMC#s_H;o"
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMCdGR;H
+NRO3#DVs_V;R4
+RNH3#ND0E_OH4MRUN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl8R"8"88;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";s@R@44d:.c6::64.:D6:H_MCOMFk0_Cs#rHoU9:jRnfdj:4nd4g(4qURp)a qu_q VXRVgUcU7_77b7RsRHlDCHM_kOFMs0C_o#Hr
+.9SosCF=k0DCHM_kOFMs0C_o#H_f.Rmn4(jn:dg4dcRO
+SDO =Db _HOM_
+NS80=NNkjM4_MDHCF_OkCM0sH_#oFD0UQRfdd...g:d(U44R8
+SNL0N=4kM_MDHCF_OkCM0sH_#oF_OlkLF09rdRdfQnnj4:(dg4R4U
+OS#D=s!DCHM_kOFMs0C_GMC0__j#kJlG4N__f4RQ44gUdc:Ugg.U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RA44y,j!?54V5:!j:?V0R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCDR"H_MCOMFk0_Cs#"Ho;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG.N;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM4
+(;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR8888"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+@sR@:4d4:.6c.:46::6DCHM_kOFMs0C_o#HrjU:9dRfnnj4:(dg4R4Uq pa)qq_uR XVcVUg7U_7R77blsHRMDHCF_OkCM0sH_#o9r4
+CSso0Fk=MDHCF_OkCM0sH_#oR_4f(m4ndj:ndgd4SR
+O=D O_D b_HMO8
+SNN0N=4kMjH_DMOC_F0kMC#s_H0oDFfURQ.d.dd.:g4(4USR
+8NN0LM=k4H_DMOC_F0kMC#s_HOo_FFlLk.0r9QRfd4njng:d(U44R#
+SO!Ds=MDHCF_OkCM0sC_MGj0__l#Jk_GN4R_4fgQ44:Ucd.Ugg;UR
+RobsFCok
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;4
+ARj4,y4!5?!V:5Vj?:202RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRDCHM_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+4;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;4n
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"8888
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4:64.:4c:.66::MDHCF_OkCM0sH_#o:rUjf9Rdd...g:d(U44Raqp _)qqXu RUVVc_gUAAAARHbslHRDMOC_F0kMC#s_Hjor9s
+SCkoF0H=DMOC_F0kMC#s_Hjo_R4fm(:njd4ngj
+nRS OD= OD_MbH_SO
+8NN0NM=k4H_DMOC_F0kMC#s_HOo_FFlLk40r9QRf.cgcng:d(U44R8
+SNL0N=4kMjH_DMOC_F0kMC#s_H0oDFfURQ.d.dd.:g4(4USR
+#sOD!H=DMOC_F0kMCMs_C_G0jJ_#lNkG_44_R4fQgc4U:gdU.RgU;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R4j5y!4j?5?0V:22:VRN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRDCHM_kOFMs0C_o#H"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+j;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR;46
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"LLLL
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4:(4U:4c:U6(::CP_MDNLCH_#ocRf.n6(:gdUUR6Uq pa)qq_uR XVjVg4 j_ R blsHRCP_MDNLCH_#os
+SCkoF0_=PCLMND#C_HfoRmn4(jU:d(U44RO
+SDO =Db _HOM_
+NS80=NNEM#$O0_#N_0CdQRf4n4(jg:d(U44R8
+SNL0N=$E#M#O_0CN0_f4RQ(44ndj:g4(4USR
+#sOD=nkM_$8D_kOFMs0C_Gj_RdfQncnU:gdU.RgU
+MSCN_=PCLMND#C_H4o__jj__oj_j__HFfcRQ6c.(dn:U6gUU
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobC;MN
+RA44y,j!?54Vj:5?0V:2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR_"PCLMND#C_H;o"
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRO3#DVs_V;R4
+RNH3#ND0E_OH4MRcN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDC4N;
+HDR3ko0blCR"C"CC;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HROODF M_CNCLDR:"MP_oN8PsHCks_M3H0PM_CNCLD_o#H_j4__jj___ojHc_F"s;
+R4@@dj:dj::cd:jj6_:ECLMND#C_HfoRc(.6nU:dgUU6Raqp _)qqXu RgVVj_4j RHbsl_RECLMND#C_HSo
+sFCokE0=_NCML_DC#RHof(m4ndj:ncgd4SR
+O=D O_D b_HMO8
+SNN0N=$P#M#O_0CN0_fdRQ(44ndj:g4(4USR
+8NN0L#=P$_MO#00NCR_4f4Q4(:njd4g(4
+URSD#OsM=knD_8$F_OkCM0s__jGQRfdUnncU:dgU.gRC
+SMEN=_NCML_DC#_Ho4__jj__joHj__RFcf.Qc6:(ndUUg6;UR
+RobsFCok
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRNCM;4
+ARj4,y4!5?5V:j:?V0R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCER"_NCML_DC#"Ho;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM4
+d;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRCCCC"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3FODOC _MDNLCMR":NPo_H8sP_Csk0MH3CE_MDNLCH_#o__4j__jjj_o_FH_c
+";s@R@44d:Uc(::(4U:E6:_M#$O.Rfcc(c:(dg4R4Uq pa)qq_uR XVgVcUw_w(bwRsRHlE$_#MSO
+sFCokE0=_M#$OmRf4j(n:jdUjRdn
+DSO D=O H_bM
+_OS08NNsN=C0#C_MbH_SO
+8NN0LD=8$F_OkCM0sR_jf4Q4(:njd4g(4
+URS08NN8O=DO$_F0kMC4s_R4fQ4j(n:(dg4R4U
+NS80=N8E$_#M4O__jj__oj_4QRf.cc(cg:d(U44Ro;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j!?5dV5:!.4?5??5jV2:0::020R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNCER"_M#$O
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3#ND0E_OH4MR.N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"V"(V;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@d@4:jdj:dc:j6j::#P_$RMOf(.ccdc:g4(4UpRqaq )_ quXVRVc_gUwww(RHbsl_RP#O$M
+CSso0Fk=#P_$RMOf(m4ndj:UdjjnSR
+O=D O_D b_HMO8
+SNN0N=#sCCb0_HOM_
+NS80=NL8_D$OMFk0_CsjQRf4n4(jg:d(U44R8
+SNO0N=$8D_kOFMs0C_f4RQ(44ndj:g4(4USR
+8NN08_=P#O$M_j4__jj__Ro4fcQ.(:ccd4g(4;UR
+RobsFCok
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4j5y!d:?V!?5.554?j:?V002:22:02
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"#P_$"MO;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HNR3D_#0OMEHR;44
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"(VVV
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";s@R@4dd:jcj::jdj:P6:#O$M_N#00jCr:Rn9f.c6jd(:U6gUUpRqaq )_ quXVRVgjj4_ sRbHPlR#O$M_N#006Cr9s
+SCkoF0#=P$_MO#00NCR_6f(m4ndj:n4n(dSR
+O=D O_D b_HMO8
+SNN0N=$P#M#O_0CN0_fnRQ(44ndj:g4(4USR
+8NN0L#=P$_MO#00NCR_jf4Q4(:njd4g(4
+URSD#OsM=knD_8$F_OkCM0s__jGQRfdUnncU:dgU.gRC
+SMPN=#O$M_N#00MC_C_G0.J_#lNkGRcfQ6(.j:gdUUR6U;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bMRCNA;
+4,R4j5y!4:?V5Vj?:202RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$O0_#N"0C;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG4N;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM4
+j;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRCCCC"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3FODOC _MDNLCMR":NPo_H8sP_Csk0MH3$P#M#O_0CN0_GMC0__.#kJlG;N"
+@sR@:4dd:jjcj:dj::6PM#$O0_#Nr0Cj9:nR6fc.:j(dUUg6qURp)a qu_q VXRVjg..j_.jbjRsRHlPM#$O0_#Nr0CcS9
+sFCokP0=#O$M_N#00cC_R4fm(:njdjn.(
+4RS OD= OD_MbH_SO
+8NN0N#=P$_MOOMFk0_CsjQRf4n4(jg:d(U44R8
+SNL0N=$P#MOO_F0kMCgs_R4fQ4j(n:(dg4R4U
+NS80=NOPM#$O0_#N_0C6QRf4n4(jg:d(U44R8
+SN80N=4kMc#_P$_MOOMFk0_CsUQRf.4gdgg:d(U44R#
+SO=Dsk_Mn8_D$OMFk0_CsjR_GfnQdn:Ucd.Ugg
+URSNCM=$P#M#O_0CN0_GMC0__.#kJlGfNRQ.c6jd(:U6gUU
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;o#bRO;Ds
+RobC;MN
+RA44y,j55d?.4?5?!V:5Vj?:202::V2V;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MO#00NC
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R.
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEM;Rg
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;R4
+RNH30DkbRol"j.jj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NRD3OF_O CLMND"CRMo:PNs_8HsPC_HkM0#3P$_MO#00NCC_MG.0__l#Jk"GN;R
+s@d@4:jdj:dc:j6j::$P#M#O_0CN0rnj:9cRf6(.j:gdUUR6Uq pa)qq_uR XVgVU(qU_qRqqblsHR$P#M#O_0CN0r
+d9SosCF=k0PM#$O0_#N_0CdmRf4j(n:(dngRjd
+DSO D=O H_bM
+_OS08NNPN=#O$M_N#004C_R4fQ4j(n:(dg4R4U
+OS#Dks=M8n_DO$_F0kMCjs__fGRQndnUdc:Ugg.USR
+C=MNPM#$O0_#N_0CM0CG_#._JGlkNQRfcj6.(U:dgUU6Ro;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob#sOD;b
+oRNCM;4
+ARj4,yj!5?0V:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#M#O_0CN0"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+d;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR
+U;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRNNNN"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3FODOC _MDNLCMR":NPo_H8sP_Csk0MH3$P#M#O_0CN0_GMC0__.#kJlG;N"
+@sR@:4dd:jjcj:dj::6PM#$O0_#Nr0Cj9:nR6fc.:j(dUUg6qURp)a qu_q VXRVjg..j_UjbjRsRHlPM#$O0_#Nr0C.S9
+sFCokP0=#O$M_N#00.C_R4fm(:njd(nnj
+dRS OD= OD_MbH_SO
+8NN0N#=P$_MOOMFk0_CsjQRf4n4(jg:d(U44R8
+SNL0N=$P#MOO_F0kMCgs_R4fQ4j(n:(dg4R4U
+NS80=NOPM#$O0_#N_0CdQRf4n4(jg:d(U44R8
+SN80N=4kMc#_P$_MOOMFk0_CsUQRf.4gdgg:d(U44R#
+SO=Dsk_Mn8_D$OMFk0_CsjR_GfnQdn:Ucd.Ugg
+URSNCM=$P#M#O_0CN0_GMC0__.#kJlGfNRQ.c6jd(:U6gUU
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;o#bRO;Ds
+RobC;MN
+RA44y,j!?5d55.?4j?5?0V:22:0::020;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"P$_MO#00NC
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rc
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEM;R(
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;R4
+RNH30DkbRol"jUjj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NRD3OF_O CLMND"CRMo:PNs_8HsPC_HkM0#3P$_MO#00NCC_MG.0__l#Jk"GN;R
+s@d@4:(4U:4c:U6(::$E#M#O_0CN0rnj:9cRf.((c:gdUUR6Uq pa)qq_uR XVjVg4 j_ R blsHR$E#M#O_0CN0r
+69SosCF=k0EM#$O0_#N_0C6mRf4j(n:.dngRUd
+DSO D=O H_bM
+_OS08NNEN=#O$M_N#00nC_R4fQ4j(n:(dg4R4U
+NS80=NLEM#$O0_#N_0CjQRf4n4(jg:d(U44R#
+SO=Dsk_Mn8_D$OMFk0_CsjR_GfnQdn:Ucd.Ugg
+URSNCM=$E#M#O_0CN0_jd__jj__j_o_fjRQ(c.cd(:U6gUU
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobC;MN
+RA44y,j!?54Vj:5?0V:2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR#"E$_MO#00NC
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R4
+RNH3D#OsV_VR
+4;N3HRN0D#_HOEM;Rn
+RNH3#ND0D_0C4MR;H
+NRD3N#s0_CO[C0RC84N;
+HlR3FR8C4N;
+HCR3MDNLC;R4
+RNH30DkbRol"CCCC
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NRD3OF_O CLMND"CRMo:PNs_8HsPC_HkM0#3E$_MO#00NC__dj__jjo__j"_j;R
+s@d@4:(4U:4c:U6(::$E#M#O_0CN0rnj:9cRf.((c:gdUUR6Uq pa)qq_uR XV.VgjU._jRjjblsHR$E#M#O_0CN0r
+c9SosCF=k0EM#$O0_#N_0CcmRf4j(n:cdn.R6d
+DSO D=O H_bM
+_OS08NNEN=#O$M_N#006C_R4fQ4j(n:(dg4R4U
+NS80=NLkjM4_$E#MOO_F0kMCds_R.fQjd.U:(dg4R4U
+NS80=NOkjM4_$E#MOO_F0kMC4s_R.fQj6n.:(dg4R4U
+NS80=N8kjM4_$E#MOO_F0kMCcs_R.fQjd.U:(dg4R4U
+OS#Dks=M8n_DO$_F0kMCjs__fGRQndnUdc:Ugg.USR
+C=MNEM#$O0_#N_0Cd__jj__j__ojjQRfcc.((U:dgUU6Ro;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08o;
+bOR#D
+s;oCbRM
+N;A44R,!jy55d?.4?5??5jV2:0::02002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$E#M#O_0CN0"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+.;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR
+6;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRUjjj"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3FODOC _MDNLCMR":NPo_H8sP_Csk0MH3$E#M#O_0CN0_jd__jj__j_o_;j"
+@sR@:4d4:U(cU:4(::6EM#$O0_#Nr0Cj9:nR.fc(:c(dUUg6qURp)a qu_q VXRV(UgUq_qqbqRsRHlEM#$O0_#Nr0CdS9
+sFCokE0=#O$M_N#00dC_R4fm(:njdgn((
+dRS OD= OD_MbH_SO
+8NN0N#=E$_MO#00NCR_4f4Q4(:njd4g(4
+URSD#OsM=knD_8$F_OkCM0s__jGQRfdUnncU:dgU.gRC
+SMEN=#O$M_N#00dC__jj___j_ojj_RcfQ.((c:gdUUR6U;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o#bRO;Ds
+RobC;MN
+RA44y,j!?5jV2:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$O0_#N"0C;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGdN;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHMcN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDC4N;
+HDR3ko0blNR"N"NN;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HROODF M_CNCLDR:"MP_oN8PsHCks_M3H0EM#$O0_#N_0Cd__jj__j__ojj
+";s@R@44d:Uc(::(4U:E6:#O$M_N#00jCr:Rn9f(c.cd(:U6gUUpRqaq )_ quXVRVgjj4_UUUUsRbHElR#O$M_N#00.Cr9s
+SCkoF0#=E$_MO#00NCR_.f(m4ndj:njn(dSR
+O=D O_D b_HMO8
+SNN0N=$E#M#O_0CN0_fdRQ(44ndj:g4(4USR
+8NN0LM=k4E._#O$M_kOFMs0CR.fQn64(:(dg4R4U
+OS#Dks=M8n_DO$_F0kMCjs__fGRQndnUdc:Ugg.USR
+C=MNEM#$O0_#N_0Cd__jj__j__ojjQRfcc.((U:dgUU6Ro;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oCbRM
+N;A44R,!jy554?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$E#M#O_0CN0"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+c;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR
+d;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRUUUU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3FODOC _MDNLCMR":NPo_H8sP_Csk0MH3$E#M#O_0CN0_jd__jj__j_o_;j"
+@sR@:4d4:U(cU:4(::6EM#$O0_#Nr0Cj9:nR.fc(:c(dUUg6qURp)a qu_q VXRVjg..j_UjbjRsRHlEM#$O0_#Nr0C4S9
+sFCokE0=#O$M_N#004C_R4fm(:njd4(c6
+dRS OD= OD_MbH_SO
+8NN0N#=E$_MO#00NCR_cf4Q4(:njd4g(4
+URS08NNkL=M_44EM#$OF_OkCM0sR_.fjQ..:Udd4g(4
+URS08NNkO=M_4jEM#$OF_OkCM0sR_4fjQ.n:.6d4g(4
+URS08NNk8=M_44EM#$OF_OkCM0sR_dfjQ..:Udd4g(4
+URSD#OsM=knD_8$F_OkCM0s__jGQRfdUnncU:dgU.gRC
+SMEN=#O$M_N#00dC__jj___j_ojj_RcfQ.((c:gdUUR6U;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;b
+oRD#Oso;
+bMRCNA;
+4,R4j5y!d.?5??545Vj?::02002:22:0RN;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$O0_#N"0C;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG6N;
+H#R3O_DsV4VR;H
+NRD3N#O0_ERHM.N;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDC4N;
+HDR3ko0blUR"j"jj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HROODF M_CNCLDR:"MP_oN8PsHCks_M3H0EM#$O0_#N_0Cd__jj__j__ojj
+";s@R@44d:Uc(::(4U:E6:#O$M_N#00jCr:Rn9f(c.cd(:U6gUUpRqaq )_ quXVRVgjj4_UUUUsRbHElR#O$M_N#00jCr9s
+SCkoF0#=E$_MO#00NCR_jf(m4ndj:n.dd.SR
+O=D O_D b_HMO8
+SNN0N=$E#M#O_0CN0_f.RQ(44ndj:g4(4USR
+8NN0LM=k4Ed_#O$M_kOFMs0CR.fQn64(:(dg4R4U
+OS#Dks=M8n_DO$_F0kMCjs__fGRQndnUdc:Ugg.USR
+C=MNEM#$O0_#N_0Cd__jj__j__ojjQRfcc.((U:dgUU6Ro;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oCbRM
+N;A44R,!jy554?j:?V002:2
+R;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$E#M#O_0CN0"N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+n;N3HR#sOD_RVV4N;
+HNR3D_#0OMEHR
+4;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+4;N3HRDbk0o"lRUUUU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3FODOC _MDNLCMR":NPo_H8sP_Csk0MH3$E#M#O_0CN0_jd__jj__j_o_;j"
+@sR@:4dgc(:::g(6:+jPM#$O0_#N_0CM0CG_#._JGlkNcRf4c.(:6dUgR.6q pa)qq_uR XN4.c_qqqAsRbHPlR#O$M_N#00MC_C_G0.J_#lNkG
+FSOlkLF0#=P$_MO#00NCC_MG.0__l#JkRGNf4mc.:(cdgU6.
+6RS08NNkN=M8n_DO$_F0kMCjs__fGRQndnUdc:Ud4d6SR
+8NN0L#=P$_MO#00NCC_MG40__l#Jk_GN4QRfd6dg4U:d.6njR8
+SNO0N=$P#M#O_0CN0_GMC0__4#kJlGdN_RdfQd4g6:ddU(Rg6
+NS80=N8k_M4PM#$O0_#N_0CM0CG_#4_JGlkNR_jfnQdn:ggdjU66;6R
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,4!?5djj*5?0V:2.:5?:fj5f4?j2:V2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blNR"N"NL;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+fsRd4UUcU:d66g.Raqp _)qqXu RcN.4j_wwb4RsRHlEM#$O0_#N_0Cd__jj__j__ojjO
+SFFlLkE0=#O$M_N#00dC__jj___j_ojj_RdfmUcU4:6dUgR.6
+NS80=NNEM#$O0_#N_0CM0CG_#4_JGlkNR_4f(Q.d:n6ddU4d
+6RS08NNEL=#O$M_N#00MC_C_G04J_#lNkG_f.RQd.(nd6:Uj.n6SR
+8NN0OM=knD_8$F_OkCM0s__jGQRfdUnncU:dd6(gR8
+SN80N=4kM_$E#M#O_0CN0_GMC0__4#kJlGjN_RdfQ.(jn:6dUjR66;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,yd!5??5.V2:0:?5.V5:!4:?V5Vj?:2022;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"j"V4;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4d.:jncj:.n+:(jM:k4#_E$_MO#00NCC_MG40__l#JkRGNfd.Ujd6:Ug4.dpRqaq )_ quX.RNcj4_qRB blsHR4kM_$E#M#O_0CN0_GMC0__4#kJlGjN_
+FSOlkLF0M=k4#_E$_MO#00NCC_MG40__l#Jk_GNjmRf.jUd6U:d4d.gR8
+SNN0N=$E#M#O_0CN0_f.RQ(44ndj:(jn(dSR
+8NN0L#=E$_MO#00NCR_df4Q4(:njdg(((
+dRS08NNkO=M_4dEM#$OF_OkCM0sQRf.(n46(:dgd4nR8
+SN80N=4kM.#_E$_MOOMFk0RCsfnQ.4:(6dcUj.;dR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,455d?.:?V!5j*j:?V0:22!?5.5V4?::025V4?:2fj2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"N"OC;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4dd:4gc4:dg+:(jM:k4#_P$_MO#00NCC_MG40__l#JkRGNfgd.dd(:Ug4.dpRqaq )_ quX.RNcw4_wR.qblsHR4kM_$P#M#O_0CN0_GMC0__4#kJlGjN_
+FSOlkLF0M=k4#_P$_MO#00NCC_MG40__l#Jk_GNjmRfdd.g(U:d4d.gR8
+SNN0N=$P#M#O_0CN0_f.RQ(44ndj:(jn(dSR
+8NN0LM=k4P._#O$M_kOFMs0C_fnRQc.j6dc:(((gdSR
+8NN0OM=k4P6_#O$M_kOFMs0C_fcRQ4.n(d6:(ng4dSR
+8NN08#=P$_MO#00NCC_MG40__l#Jk_GN.QRfdn.j(U:djdc.Ro;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R445y!d:?V!?5.5V4?:*!j5Vj?:202:j!f2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"V".N;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+fsR.jUd6g:ddnd6Raqp _)qqXu R4N4dj_UUbjRsRHlPM#$O0_#N_0CdP_H_jj__j_o_Nj_d
+_jSlOFL0Fk=$P#M#O_0CN0_Hd_P__jjo__j__jNjd_R.fmU6dj:ddgdR6n
+NS80=NNPM#$O0_#N_0C.QRf4n4(jU:dUn(nR8
+SNL0N=4kM.#_P$_MOOMFk0_CsnQRf.6jccg:djnjdR8
+SNO0N=4kM6#_P$_MOOMFk0_CscQRf.(n46g:d4n..Ro;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+RA44y,j!?5.554?j:?V002:22:0RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UUjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@dd:4g::g4:dgcjj+:hpQ m_Bz_haM0CG\M3k4Dj_H_MCOMFk0_Cs#RHofn.64dc:gjj6jpRqaq )_ quX.RNcw4_wR(wblsHRhpQ m_Bz_haM0CG\M3k4Dj_H_MCOMFk0_Cs#DHo0
+FUSlOFL0Fk=4kMjH_DMOC_F0kMC#s_H0oDFfURmn.64dc:gjj6jSR
+8NN0NH=DMOC_F0kMC#s_Hno_R4fQ4j(n:6dUgR4j
+NS80=NLDCHM_kOFMs0C_o#H_f(RQ(44ndj:UU(4jSR
+8NN0OH=DMOC_F0kMC#s_HUo_R4fQ4j(n:UdUdR(j
+NS80=N8kjM4_MDHCF_OkCM0sH_#oFD06QRf.cc(cU:dgjndRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4j5y!d:?V!?5.554?j:?V002:22:02
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"V(;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@44j:nj4::44n:+4c.o:PNs_8HsPC_HkM0dRf(c66:6dUdRn6q pa)qq_uR XN4.c_4jwwsRbHtlR_S.
+OLFlF=k0t__.HmRfd6(6cU:d66dnR8
+SNN0N=$E#M#O_0CN0_fjRQ(44ndj:U(j(6SR
+8NN0L#=E$_MO#00NCR_nf4Q4(:njdjU.c
+6RS08NNkO=MEg_#O$M_kOFMs0CDR0gfnQ.d:cnd.Udd
+6RS08NNk8=M8n_DO$_F0kMCjs__fGRQndnUdc:Ugcc6
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,5jyd.?5?0V:2.:5??54Vj:5?0V:202:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"V"4V;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4dd:.n4d4:.dn:.:+jPM#$O0_#N_0CM0CG_#4_JGlkNR_4f4djUdg:(cUUdpRqaq )_ quX.RNc74_jRwjblsHR$P#M#O_0CN0_GMC0__4#kJlG4N_
+FSOlkLF0#=P$_MO#00NCC_MG40__l#Jk_GN4mRfdUj4g(:dUdUcR8
+SNN0N=$P#MOO_F0kMCjs_R4fQ4j(n:cd(.R6d
+NS80=NLPM#$OF_OkCM0sR_gf4Q4(:njd6(6.
+dRS08NNPO=#O$M_N#006C_R4fQ4j(n:nd((R4d
+NS80=N8kcM4_$P#MOO_F0kMCUs_R.fQggd4:(d(gR(d;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,yd!5??5.5V4?:j!5?0V:202:2.:5?0V:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl8R"j"Vj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4dd:d44d4:dd4:d:+jPM#$O0_#N_0CM0CG_#4_JGlkNR_.fd.Ujd6:(nnn4pRqaq )_ quX4RN4.d_qR.qblsHR$P#M#O_0CN0_GMC0__4#kJlG.N_
+FSOlkLF0#=P$_MO#00NCC_MG40__l#Jk_GN.mRf.jUd6(:dn4nnR8
+SNN0N=$P#M#O_0CN0_fcRQ(44ndj:((.j4SR
+8NN0LM=k4P._#O$M_kOFMs0C_f(RQc.j6dc:(cdd4SR
+8NN0OM=k4Pd_#O$M_kOFMs0C_fcRQ4.n(d6:(dc64
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+AR44,y?5.5V4?:*!j5Vj?:202:j!f2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRN"..;N"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4dd:d4g:4d:dgc:d+Pj:#O$M_N#00MC_C_G04J_#lNkG_fdRdUj4gU:djdjdRaqp _)qqXu RcN.4j_(wbjRsRHlPM#$O0_#N_0CM0CG_#4_JGlkN
+_dSlOFL0Fk=$P#M#O_0CN0_GMC0__4#kJlGdN_Rdfmjg4U:jdUjRdd
+NS80=NNPM#$OF_OkCM0sR_jf4Q4(:njdc(6c
+dRS08NNPL=#O$M_kOFMs0C_fgRQ(44ndj:(4n(dSR
+8NN0O#=P$_MO#00NCR_df4Q4(:njdg((j
+dRS08NNk8=M_4cPM#$OF_OkCM0sR_UfgQ.d:4gd4(gn;dR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j55d?.4?5??5jV2:0::02V!2:5V.?:202RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"V(jj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@jn:44::j4:n44.c+:NPo_H8sP_Csk0MHR(fd6:6cddU6nq6Rp)a qu_q NXR._c4jww4RHbsl_Rt4Sn
+OLFlF=k0tn_4_fHRm6d(6dc:Un6d6SR
+8NN0N#=P$_MO#00NCR_jf4Q4(:njd(Uj(
+6RS08NNPL=#O$M_N#00nC_R4fQ4j(n:.dUjRc6
+NS80=NOk_MgPM#$OF_OkCM0sgD0R.fQnndc:ddU.Rd6
+NS80=N8k_Mn8_D$OMFk0_CsjR_GfnQdn:UcdcUcg;6R
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j55d?.:?V052:.4?5?5V:j:?V0:220R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRjVV4"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:444:4g:4c4:4:+jBzmpvBh_mazh_GMC0k\3M_4jOkFDlOM_F0kMC#s_HfoR.46ncg:dj.jdRaqp _)qqXu RcN.4w_4jbwRsRHlBzmpvBh_mazh_GMC0k\3M_4jOkFDlOM_F0kMC#s_H0oDFSg
+OLFlF=k0kjM4_DOFk_lMOMFk0_Cs#DHo0RFgf6m.n:4cdjgjd
+.RS08NNON=FlDkMF_OkCM0sH_#oR_(f4Q4(:njdcU6c
+.RS08NNOL=FlDkMF_OkCM0sH_#oR_Uf4Q4(:njd(Un4
+.RS08NNOO=FlDkMF_OkCM0sH_#oR_gf4Q4(:njdgU(j
+.RS08NNk8=M_4jOkFDlOM_F0kMC#s_H0oDnQRf.cc(cU:dg.4nRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5??5.5V4?:?5jV2:022:0:?5.V2:02
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"4j;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4.d:44U:44:.Ud:d+Ej:#O$M_N#00MC_C_G04J_#lNkG_f.R.jdnd(:dUdUcRaqp _)qqXu RcN.4q_.qbqRsRHlEM#$O0_#N_0CM0CG_#4_JGlkN
+_.SlOFL0Fk=$E#M#O_0CN0_GMC0__4#kJlG.N_R.fmddnj:Ud(URcd
+NS80=NNEM#$O0_#N_0CcQRf4n4(j(:dcd.6R8
+SNL0N=4kM4#_E$_MOOMFk0_Cs.QRf.Uj.d(:d6d6.R8
+SNO0N=4kMj#_E$_MOOMFk0_Cs4QRf..jn6(:dnd(4R8
+SN80N=4kM4#_E$_MOOMFk0_CsdQRf.Uj.d(:d(dg(Ro;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R44dy5??5.5V4?:*!j5Vj?:202:j!f2f:!j;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl.R"N"NN;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4d.:4d4.4:4dd:.:+jEM#$O0_#N_0CM0CG_#4_JGlkNR_4fn.djdd:(((6dpRqaq )_ quX.RNc.4_qRqqblsHR$E#M#O_0CN0_GMC0__4#kJlG4N_
+FSOlkLF0#=E$_MO#00NCC_MG40__l#Jk_GN4mRf.jdnd(:d(d6(R8
+SNN0N=$E#M#O_0CN0_f6RQ(44ndj:(U.gdSR
+8NN0LM=k4Ej_#O$M_kOFMs0C_fdRQ..jUdd:(6c.dSR
+8NN0OM=k4Ej_#O$M_kOFMs0C_f4RQn.j.d6:(c6cdSR
+8NN08M=k4Ej_#O$M_kOFMs0C_fcRQ..jUdd:(jn(d
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,54yd.?5??54Vj:!*?5jV2:02f:!j!2:fRj2;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR.NNN"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:4.d::44.:d4dj.+:Y]1hwB_1Mv_C\G034kMd#_E$_MOOMFk0RCsf...cd.:(d6.jpRqaq )_ quX.RNc44_jRjjblsHRY]1hwB_1Mv_C\G034kMd#_E$_MOOMFk0
+CsSlOFL0Fk=4kMd#_E$_MOOMFk0RCsf.m..:c.d.(6d
+jRS08NNEN=#O$M_kOFMs0C_fnRQ(44ndj:(cjnjSR
+8NN0L#=E$_MOOMFk0_Cs(QRf4n4(j(:d4jg4R8
+SNO0N=4kMd#_E$_MOOMFk0_Cs.QRf.4j4.(:ddj4jR8
+SN80N=4kMd#_E$_MOOMFk0_Cs(QRf.Uj.d(:dcjdnRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5??5.5V4?:?5jV2:022:V:RV2;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR4jjj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:.4(:4g:(d.:n:+j]h1YBm_Bz_haM0CG\M3kg#_E$_MOOMFk0RCsf...cd.:(dg44pRqaq )_ quX.RNcw4_(RwwblsHRY]1hBB_mazh_GMC0k\3MEg_#O$M_kOFMs0CD
+0gSlOFL0Fk=gkM_$E#MOO_F0kMC0sDgmRf.c...(:dg44dR8
+SNN0N=$E#MOO_F0kMCUs_R4fQ4j(n:cd(6Rc4
+NS80=NLEM#$OF_OkCM0sR_gf4Q4(:njdU(64
+4RS08NNkO=MEg_#O$M_kOFMs0CD_0gdQRf.4j4.(:d(4jjR8
+SN80N=4kMd#_E$_MOOMFk0_Cs(QRf.Uj.d(:dU4.nRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4j5y!d.?5?!V:554?j:?V002:2V2:2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboR("VV;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4.d:Ug4::4.U:+dnj1:eY_hBBhmzaC_MG30\k_MgPM#$OF_OkCM0s.Rf...c:gd(4Rd4q pa)qq_uR XN4.c_www(sRbHelR1BYh_zBmhMa_C\G03gkM_$P#MOO_F0kMC0sDgO
+SFFlLkk0=MPg_#O$M_kOFMs0CDR0gf.m..:c.d4(gd
+4RS08NNPN=#O$M_kOFMs0C_fcRQ(44ndj:(cc64SR
+8NN0L#=P$_MOOMFk0_Cs6QRf4n4(j(:d64U4R8
+SNO0N=gkM_$P#MOO_F0kMC0sDgR_6fjQ.4:4.dj((j
+4RS08NNk8=MPg_#O$M_kOFMs0CD_0gnQRf.4j4.(:dU4.nRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4j5y!d:?V5V.?:4!5??5jV2:0:2022
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"VV;("
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4.d:.4n:4.:.nc:d+]j:1BYh_vw1_GMC0k\3M_4.EM#$OF_OkCM0s.Rf...c:nd(cRgjq pa)qq_uR XN4.c_jUjjsRbH]lR1BYh_vw1_GMC0k\3M_4.EM#$OF_OkCM0sO
+SFFlLkk0=M_4.EM#$OF_OkCM0smRf.c...(:dnjcgR8
+SNN0N=$E#MOO_F0kMCjs_R4fQ4j(n:4d(gRjj
+NS80=NLEM#$OF_OkCM0sR_4f4Q4(:njd4(d(
+jRS08NNkO=M_4.EM#$OF_OkCM0sR_dfjQ.4:4.dd(cn
+jRS08NNk8=M_4.EM#$OF_OkCM0sR_cfjQ.4:4.dn(6.;jR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j!?5d55.?4j?5?0V:22:0::020;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blUR"j"jj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4d4:dggd:4gj:c+pj:Q_h BhmzaC_MG30\kjM4_MDHCF_OkCM0sH_#o.Rfj.gU:6dUURnUq pa)qq_uR XN4.c_jjw(sRbHplRQ_h BhmzaC_MG30\kjM4_MDHCF_OkCM0sH_#oFD06O
+SFFlLkk0=M_4jDCHM_kOFMs0C_o#HD60FR.fmj.gU:6dUURnU
+NS80=NNDCHM_kOFMs0C_o#H_f4RQ(44ndj:U(4.USR
+8NN0LH=DMOC_F0kMC#s_H.o_R4fQ4j(n:.dU6RcU
+NS80=NODCHM_kOFMs0C_o#H_f6RQ(44ndj:Udd(USR
+8NN08M=k4Dj_H_MCOMFk0_Cs#DHo0.c_R.fQj.44:cdUgRgU;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5d5V.?::025V.?:?545Vj?::020222RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"jjV(
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@dc:dc4:4:cdc:+d.j1:eY_hBw_1vM0CG\M3k4P6_#O$M_kOFMs0CR.f..:c.d.(6dqjRp)a qu_q NXR4_4d4jj4RHbsl1ReY_hBw_1vM0CG\M3k4P6_#O$M_kOFMs0C_Sc
+OLFlF=k0k6M4_$P#MOO_F0kMCcs_R.fm...c:6d(.Rdj
+NS80=NNPM#$OF_OkCM0sR_4f4Q4(:njdn(jc
+jRS08NNPL=#O$M_kOFMs0C_fcRQ(44ndj:(44gjSR
+8NN0OM=k4P6_#O$M_kOFMs0C_fdRQ4.j4d.:(jd4j
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+ARj4,y?5.5V4?:?5jV2:022:VRN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"44jj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@dd:d44:4:4dd:+ddj1:eY_hBw_1vM0CG\M3k4Pd_#O$M_kOFMs0CR.f..:c.d6(jgqURp)a qu_q NXR4_4dUjjURHbsl1ReY_hBw_1vM0CG\M3k4Pd_#O$M_kOFMs0C_Sc
+OLFlF=k0kdM4_$P#MOO_F0kMCcs_R.fm...c:jd(6RgU
+NS80=NNPM#$OF_OkCM0sR_jf4Q4(:njdjnnj
+URS08NNPL=#O$M_kOFMs0C_f6RQ(44ndj:n((.USR
+8NN0OM=k4Pd_#O$M_kOFMs0C_fdRQ4.j4d.:nnUcU
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+ARj4,y.!5??545Vj?::02002:2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRj"UU;j"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@44d:4g4::444:+c4jm:Bphzv_zBmhMa_C\G034kMjF_ODMkl_kOFMs0C_o#HRjf.g:U.dcU6jqjRp)a qu_q NXR._c4www(RHbslmRBphzv_zBmhMa_C\G034kMjF_ODMkl_kOFMs0C_o#HD
+0nSlOFL0Fk=4kMjF_ODMkl_kOFMs0C_o#HDR0nfjm.g:U.dcU6j
+jRS08NNON=FlDkMF_OkCM0sH_#oR_cf4Q4(:njdUUj4
+jRS08NNOL=FlDkMF_OkCM0sH_#oR_nf4Q4(:njdjU.U
+jRS08NNOO=FlDkMF_OkCM0sH_#oR_6f4Q4(:njd.Ud(
+jRS08NNk8=M_4jOkFDlOM_F0kMC#s_H0oDnR_cfjQ.4:4.d6Ucd;jR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j!?5dV5:!.4?5??5jV2:0::020R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVVV("N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:g4n:4(:ndg:.:+jEM#$OF_OkCM0sC_MG40__l#JkRGNfg.4ndc:gdjj.pRqaq )_ quX.RNcj4_jRUjblsHR$E#MOO_F0kMCMs_C_G04J_#lNkG
+FSOlkLF0#=E$_MOOMFk0_CsM0CG_#4_JGlkNmRf.n4gcg:dj.jdR8
+SNN0N=#sCCb0_HOM_
+NS80=NL8_D$OMFk0_CsjQRf4n4(jU:dn.(4R8
+SNO0N=$8D_kOFMs0C_f4RQ(44ndj:Uj(g.SR
+8NN08_=8#_C0EM#$OF_OkCM0sQRf.g4jcU:dg.4nRo;
+bFROlkLF0o;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j5Vd?:.!5??545Vj?::02002:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"j"Uj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4dd:dg4d4:ddg:c:+jeh1YB1_wvC_MG30\kcM4_$P#MOO_F0kMCfsR.c6jc(:ddUngRaqp _)qqXu RgNc_UUUUsRbHelR1BYh_vw1_GMC0k\3M_4cPM#$OF_OkCM0s
+_USlOFL0Fk=4kMc#_P$_MOOMFk0_CsUmRf.c6jc(:ddUngR8
+SNN0N=4kM.#_P$_MOOMFk0_CsnQRf.6jccn:dgU4jR8
+SNL0N=4kM.#_P$_MOOMFk0_Cs(QRf.6jcc(:djUd(Ro;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0LA;
+4,R4j5y!4j?5?0V:22:0RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UUUU
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@dd:4g::g4:dgcjj+:MDHCF_OkCM0sC_MGj0__l#Jk_GN44Rf6jjU:6dU4Rgcq pa)qq_uR XN4.c_UjjjsRbHDlRH_MCOMFk0_CsM0CG_#j_JGlkN__44O
+SFFlLkD0=H_MCOMFk0_CsM0CG_#j_JGlkN__44mRf4U6jjU:d6c4gR8
+SNN0N=#sCCb0_HOM_
+NS80=NL8_D$OMFk0_CsjQRf4n4(jU:d4cU(R8
+SNO0N=$8D_kOFMs0C_f4RQ(44ndj:UndjcSR
+8NN08#=P$_MO#00NCR_4f4Q4(:njddUc.;cR
+RobOLFlF;k0
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5?!V:55.?4j?5?0V:22:0:202RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"Ujjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+Rjf.g:U.ddgd6qnRp)a qu_q NXR._c4BUB7RHbsl_RP#O$M_j4__jj__
+o4SlOFL0Fk=#P_$_MO4__jj__jof4Rmg.jUd.:g6ddnSR
+8NN0N#=P$_MO#00NCR_.f4Q4(:njd(UUn
+nRS08NNPL=_M#$OQRf4n4(jg:djnjdR8
+SNO0N=$P#M#O_0CN0_fcRQ(44ndj:g.4.nSR
+8NN08M=k4#_P$_MO#00NC__.jQRf.4j4.g:d.ncURo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R445y!d4?5?0V:2.:5??54Vj:!*?5jV2:024:5?:fj0222RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"8OOU
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+RUfdU:4cdjUngqnRp)a qu_q NXR4_4dw44wRHbsl_RECLMND#C_H4o__jj__oj_j__HFSc
+OLFlF=k0EM_CNCLD_o#H_j4__jj___ojHc_FRdfmUcU4:ndUjRgn
+NS80=NNPM#$O0_#N_0CcQRf4n4(jU:d4n6jR8
+SNL0N=$P#M#O_0CN0_f6RQ(44ndj:U(.(nSR
+8NN0OM=knD_8$F_OkCM0s__jGQRfdUnncU:ddngnRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+RA44y,j!?5.V5:!4:?V5Vj?:2022
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboR4"VV;4"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4.d:((U::U.(:+d.j#:P$_MOOMFk0_CsM0CG_#4_JGlkN.Rf4d46:jdgjRd.q pa)qq_uR XN4.c_UjjjsRbHPlR#O$M_kOFMs0C_GMC0__4#kJlGSN
+OLFlF=k0PM#$OF_OkCM0sC_MG40__l#JkRGNf4m.4:6ddjgjd
+.RS08NNsN=C0#C_MbH_SO
+8NN0LD=8$F_OkCM0sR_jf4Q4(:njd(Un4
+.RS08NN8O=DO$_F0kMC4s_R4fQ4j(n:(dUgRj.
+NS80=N88C_#0#_P$_MOOMFk0RCsfjQ..:Udd4Ugn;.R
+RobOLFlF;k0
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5?!V:55.?4j?5?0V:22:0:202RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"Ujjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+RUfdU:4cdjUngqnRp)a qu_q NXR4_4dw44wRHbsl_RPCLMND#C_H4o__jj__oj_j__HFSc
+OLFlF=k0PM_CNCLD_o#H_j4__jj___ojHc_FRdfmUcU4:ndUjRgn
+NS80=NNEM#$O0_#N_0CcQRf4n4(jU:d4n6jR8
+SNL0N=$E#M#O_0CN0_f6RQ(44ndj:U(.(nSR
+8NN0OM=knD_8$F_OkCM0s__jGQRfdUnncU:ddngnRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+RA44y,j!?5.V5:!4:?V5Vj?:2022
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboR4"VV;4"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s.Rfj.gU:ddgdR6nq pa)qq_uR XN4.c_7BBUsRbHElR_M#$O__4j__jj4_o
+FSOlkLF0_=E#O$M_j4__jj__Ro4fjm.g:U.ddgd6
+nRS08NNEN=#O$M_N#00.C_R4fQ4j(n:UdU(Rnn
+NS80=NLE$_#MfORQ(44ndj:gdjjnSR
+8NN0O#=E$_MO#00NCR_cf4Q4(:njd.g4.
+nRS08NNk8=ME4_#O$M_N#00dC__fjRQ4.j4d.:gU.cn
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,!4y55d?4:?V052:.4?5?!V:jj*5?0V:252:4j?f:2022
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRO"O8;U"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@44d:4g4::444:+c4jF:ODMkl_kOFMs0C_GMC0__j#kJlG4N_R6f4j:UjdjU6.qdRp)a qu_q NXR._c4jjjURHbslFRODMkl_kOFMs0C_GMC0__j#kJlG4N__S4
+OLFlF=k0OkFDlOM_F0kMCMs_C_G0jJ_#lNkG_44_R4fm6jjU:6dUjR.d
+NS80=NNsCC#0H_bM
+_OS08NN8L=DO$_F0kMCjs_R4fQ4j(n:4dU(Rjd
+NS80=NO8_D$OMFk0_Cs4QRf4n4(jU:d.dUgR8
+SN80N=$E#M#O_0CN0_f4RQ(44ndj:U6c4d
+R;oObRFFlLk
+0;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5dV5:!.4?5??5jV2:0::020R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRjjjU"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:n..::44.:.ndjc+:Y]1hwB_1Mv_C\G034kM.#_E$_MOOMFk0RCsfd4n6dj:(64UUpRqaq )_ quX.RNcj4_jR4jblsHRY]1hwB_1Mv_C\G034kM.#_E$_MOOMFk0_CscO
+SFFlLkk0=M_4.EM#$OF_OkCM0sR_cfnm4d:6jdU(46
+URS08NNEN=#O$M_kOFMs0C_fnRQ(44ndj:nn(.USR
+8NN0L#=E$_MOOMFk0_Cs(QRf4n4(jn:dUU6dR8
+SNO0N=$E#MOO_F0kMCgs_R4fQ4j(n:gdn(R.U
+NS80=N8EM#$OF_OkCM0sR_df4Q4(:njdg(jU;UR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j5Vd?:?5.5V4?:?5jV2:022:V2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRj"j4;j"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4.d:.4n:4.:.nc:d+]j:1BYh_vw1_GMC0k\3M_4.EM#$OF_OkCM0s4Rfnjd6:jd(6RgUq pa)qq_uR XN4.c_jjjUsRbH]lR1BYh_vw1_GMC0k\3M_4.EM#$OF_OkCM0s
+_dSlOFL0Fk=4kM.#_E$_MOOMFk0_CsdmRf46ndj(:djU6gR8
+SNN0N=$E#MOO_F0kMC.s_R4fQ4j(n:ndnjRjU
+NS80=NLEM#$OF_OkCM0sR_Uf4Q4(:njd.n((
+URS08NNEO=#O$M_kOFMs0C_fcRQ(44ndj:nnUcUSR
+8NN08#=E$_MOOMFk0_Cs6QRf4n4(jn:dgU(.Ro;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5?5V:.:?V!?545Vj?::020222RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"jjjU
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@d4:.U4:4:U.4:+ddj1:]Y_hBw_1vM0CG\M3k4E4_#O$M_kOFMs0CRnf4d:6jdj(ccqjRp)a qu_q NXR._c4jUjjRHbsl1R]Y_hBw_1vM0CG\M3k4E4_#O$M_kOFMs0C_Sd
+OLFlF=k0k4M4_$E#MOO_F0kMCds_R4fmnjd6:cd(jRcj
+NS80=NNEM#$OF_OkCM0sR_jf4Q4(:njdcng6
+jRS08NNEL=#O$M_kOFMs0C_f4RQ(44ndj:(.j(jSR
+8NN0O#=E$_MOOMFk0_CsdQRf4n4(j(:d4jg4R8
+SN80N=$E#MOO_F0kMCcs_R4fQ4j(n:dd(4R(j;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5dV.:5?!V:554?j:?V002:2R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRjUjj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:U.4::44.:4Udjd+:Y]1hwB_1Mv_C\G034kM4#_E$_MOOMFk0RCsfd4n6dj:(g46jpRqaq )_ quX4RN4jd_URjUblsHRY]1hwB_1Mv_C\G034kM4#_E$_MOOMFk0_Cs.O
+SFFlLkk0=M_44EM#$OF_OkCM0sR_.fnm4d:6jd6(4g
+jRS08NNEN=#O$M_kOFMs0C_f.RQ(44ndj:nj(jjSR
+8NN0L#=E$_MOOMFk0_Cs(QRf4n4(jn:dUj.(R8
+SNO0N=$E#MOO_F0kMCns_R4fQ4j(n:gdncRnj;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;A44R,5jy.:?V!?545Vj?::020R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRjUUj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:.4(:4g:(d.:n:+j]h1YBm_Bz_haM0CG\M3kg#_E$_MOOMFk0RCsfd4n6dj:(dd.gpRqaq )_ quX.RNc(4_wRwwblsHRY]1hBB_mazh_GMC0k\3MEg_#O$M_kOFMs0CD_0gdO
+SFFlLkk0=MEg_#O$M_kOFMs0CD_0gdmRf46ndj(:ddg.dR8
+SNN0N=$E#MOO_F0kMCns_R4fQ4j(n:UdnnRcg
+NS80=NLEM#$OF_OkCM0sR_(f4Q4(:njdgng4
+gRS08NNEO=#O$M_kOFMs0C_fcRQ(44ndj:(j44gSR
+8NN08#=E$_MOOMFk0_Cs6QRf4n4(j(:d.gdnRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5??5.554?j:?V002:22:0:R02;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR(VVV"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:4.d::44.:d4dj.+:Y]1hwB_1Mv_C\G034kMd#_E$_MOOMFk0RCsfd4n6dj:ndgdUpRqaq )_ quX.RNcj4_jRUjblsHRY]1hwB_1Mv_C\G034kMd#_E$_MOOMFk0_Cs.O
+SFFlLkk0=M_4dEM#$OF_OkCM0sR_.fnm4d:6jddngd
+URS08NNEN=#O$M_kOFMs0C_fURQ(44ndj:ncc(USR
+8NN0L#=E$_MOOMFk0_CsgQRf4n4(jn:dnUj4R8
+SNO0N=$E#MOO_F0kMCcs_R4fQ4j(n:(dn.RjU
+NS80=N8EM#$OF_OkCM0sR_6f4Q4(:njdcnUn;UR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j5Vd?:.!5??545Vj?::02002:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"j"Uj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4d.:U4gU:.4n:d+ej:1BYh_zBmhMa_C\G03gkM_$P#MOO_F0kMCfsR46ndj(:dcgcgRaqp _)qqXu RcN.4w_(wbwRsRHleh1YBm_Bz_haM0CG\M3kg#_P$_MOOMFk0DCs0ng_
+FSOlkLF0M=kg#_P$_MOOMFk0DCs0ng_R4fmnjd6:cd(cRgg
+NS80=NNPM#$OF_OkCM0sR_.f4Q4(:njdgngj
+gRS08NNPL=#O$M_kOFMs0C_fdRQ(44ndj:((44gSR
+8NN0O#=P$_MOOMFk0_CsjQRf4n4(j(:d.gdnR8
+SN80N=$P#MOO_F0kMC4s_R4fQ4j(n:dd(nR.g;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5d55.?4j?5?0V:22:0::020;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl(R"V"VV;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4d.:U4gU:.4n:d+ej:1BYh_zBmhMa_C\G03gkM_$P#MOO_F0kMCfsR46ndj(:ddg.dRaqp _)qqXu RcN.4w_(wbwRsRHleh1YBm_Bz_haM0CG\M3kg#_P$_MOOMFk0DCs06g_
+FSOlkLF0M=kg#_P$_MOOMFk0DCs06g_R4fmnjd6:dd(.Rdg
+NS80=NNPM#$OF_OkCM0sR_Uf4Q4(:njdnnUc
+gRS08NNPL=#O$M_kOFMs0C_fgRQ(44ndj:n4gggSR
+8NN0O#=P$_MOOMFk0_CsnQRf4n4(j(:d4g4jR8
+SN80N=$P#MOO_F0kMC(s_R4fQ4j(n:.d(dRng;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5d55.?4j?5?0V:22:0::020;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl(R"V"VV;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4d.:4d4.4:4dd:.:+j]h1YB1_wvC_MG30\kjM4_$E#MOO_F0kMCfsR46ndj(:d.j((Raqp _)qqXu RcN.4j_UjbjRsRHl]h1YB1_wvC_MG30\kjM4_$E#MOO_F0kMCcs_
+FSOlkLF0M=k4Ej_#O$M_kOFMs0C_fcRmd4n6dj:((.(jSR
+8NN0N#=E$_MOOMFk0_CscQRf4n4(jn:dUj4UR8
+SNL0N=$E#MOO_F0kMCns_R4fQ4j(n:gdncR6j
+NS80=NOEM#$OF_OkCM0sR_4f4Q4(:njdn(jc
+jRS08NNE8=#O$M_kOFMs0C_fdRQ(44ndj:(j4gj
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,!jy55d?.4?5??5jV2:0::02002:2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRj"Uj;j"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4.d:44d:44:.d.:d+]j:1BYh_vw1_GMC0k\3M_4jEM#$OF_OkCM0s4Rfnjd6:jd(dR.jq pa)qq_uR XNd44_jj44sRbH]lR1BYh_vw1_GMC0k\3M_4jEM#$OF_OkCM0s
+_dSlOFL0Fk=4kMj#_E$_MOOMFk0_CsdmRf46ndj(:djjd.R8
+SNN0N=$E#MOO_F0kMCjs_R4fQ4j(n:6dn(Rdj
+NS80=NLEM#$OF_OkCM0sR_(f4Q4(:njdjn(j
+jRS08NNEO=#O$M_kOFMs0C_f.RQ(44ndj:ngU4j
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+ARj4,y?5.V4:5?5V:j:?V0222RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"jj44
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@dc:dc4:4:cdc:+d.j1:eY_hBw_1vM0CG\M3k4P6_#O$M_kOFMs0CRnf4d:6jddngdqURp)a qu_q NXR._c4jjj.RHbsl1ReY_hBw_1vM0CG\M3k4P6_#O$M_kOFMs0C_Sd
+OLFlF=k0k6M4_$P#MOO_F0kMCds_R4fmnjd6:gdndRdU
+NS80=NNPM#$OF_OkCM0sR_gf4Q4(:njd(ncc
+URS08NNPL=#O$M_kOFMs0C_f.RQ(44ndj:n4njUSR
+8NN0O#=P$_MOOMFk0_CsdQRf4n4(jn:d(U.jR8
+SN80N=$P#MOO_F0kMCjs_R4fQ4j(n:UdncRnU;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5dV.:5??54V5:!j:?V0:22VR22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRjjj."N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:4dd::44d:d4djd+:Ye1hwB_1Mv_C\G034kMd#_P$_MOOMFk0RCsfd4n6dj:njc(npRqaq )_ quX.RNcj4_jRj4blsHRYe1hwB_1Mv_C\G034kMd#_P$_MOOMFk0_CsdO
+SFFlLkk0=M_4dPM#$OF_OkCM0sR_dfnm4d:6jd(ncj
+nRS08NNPN=#O$M_kOFMs0C_fnRQ(44ndj:n4j4nSR
+8NN0L#=P$_MOOMFk0_Cs(QRf4n4(jn:d4ndUR8
+SNO0N=$P#MOO_F0kMCUs_R4fQ4j(n:.dn6R(n
+NS80=N8PM#$OF_OkCM0sR_gf4Q4(:njdUndd;nR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j5Vd?:?5.V4:5?5V:j:?V02222
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRj"jj;4"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@44d:4g4::444:+c4jm:Bphzv_zBmhMa_C\G034kMjF_ODMkl_kOFMs0C_o#HRnf4d:6jd(UjnqURp)a qu_q NXR._c4(wwwRHbslmRBphzv_zBmhMa_C\G034kMjF_ODMkl_kOFMs0C_o#HD_0ncO
+SFFlLkk0=M_4jOkFDlOM_F0kMC#s_H0oDnR_cfnm4d:6jd(Ujn
+URS08NNON=FlDkMF_OkCM0sH_#oR_.f4Q4(:njd4(n(
+URS08NNOL=FlDkMF_OkCM0sH_#oR_df4Q4(:njdc((c
+URS08NNOO=FlDkMF_OkCM0sH_#oR_jf4Q4(:njdn(Ud
+URS08NNO8=FlDkMF_OkCM0sH_#oR_4f4Q4(:njdU(gg;UR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j55d?.4?5??5jV2:0::02002:2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"(V;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@44d:dgg::g4d:+cjjQ:phB _mazh_GMC0k\3M_4jDCHM_kOFMs0C_o#HRnf4d:6jd.U4dqnRp)a qu_q NXR4_4d(ww(RHbslQRphB _mazh_GMC0k\3M_4jDCHM_kOFMs0C_o#HD_0c.O
+SFFlLkk0=M_4jDCHM_kOFMs0C_o#HD_0c.mRf46ndjU:d4n.dR8
+SNN0N=MDHCF_OkCM0sH_#oR_df4Q4(:njdn(nc
+nRS08NNDL=H_MCOMFk0_Cs#_HocQRf4n4(j(:d(ng4R8
+SNO0N=MDHCF_OkCM0sH_#oR_jf4Q4(:njd4(gj;nR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0OA;
+4,R4j.y5??545Vj?::02002:2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"((;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4.d:44d:44:.d.:d+]j:1BYh_vw1_GMC0k\3M_4jEM#$OF_OkCM0s4Rfnjd6:4d(4RnUq pa)qq_uR XNd44_jj44sRbH]lR1BYh_vw1_GMC0k\3M_4jEM#$OF_OkCM0s
+_4SlOFL0Fk=4kMj#_E$_MOOMFk0_Cs4mRf46ndj(:d4U4nR8
+SNN0N=$E#MOO_F0kMC6s_R4fQ4j(n:ndn6R(U
+NS80=NLEM#$OF_OkCM0sR_Uf4Q4(:njdUn(c
+URS08NNEO=#O$M_kOFMs0C_fgRQ(44ndj:ndgjU
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;4
+ARj4,y?5.V4:5?5V:j:?V0222RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"jj44
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@d.:dn4:4:nd.:+d.j1:eY_hBw_1vM0CG\M3k4P._#O$M_kOFMs0CRnf4d:6jdjn6jqcRp)a qu_q NXR._c4j4jjRHbsl1ReY_hBw_1vM0CG\M3k4P._#O$M_kOFMs0C_Sn
+OLFlF=k0k.M4_$P#MOO_F0kMCns_R4fmnjd6:6dnjRjc
+NS80=NNPM#$OF_OkCM0sR_(f4Q4(:njdcnj4
+cRS08NNPL=#O$M_kOFMs0C_fURQ(44ndj:nU4ncSR
+8NN0O#=P$_MOOMFk0_Cs6QRf4n4(jn:d.cU(R8
+SN80N=$P#MOO_F0kMCns_R4fQ4j(n:cdn4Rdc;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5dV.:5?5V:4:?V5Vj?:2022;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"j"j4;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4dd:.n4d4:.dn:.:+jeh1YB1_wvC_MG30\k.M4_$P#MOO_F0kMCfsR46ndjn:dnc.(Raqp _)qqXu RcN.4j_jjb4RsRHleh1YB1_wvC_MG30\k.M4_$P#MOO_F0kMC(s_
+FSOlkLF0M=k4P._#O$M_kOFMs0C_f(Rmd4n6dj:n(n.cSR
+8NN0N#=P$_MOOMFk0_CsdQRf4n4(jn:d4cnUR8
+SNL0N=$P#MOO_F0kMCcs_R4fQ4j(n:.dngR6c
+NS80=NOPM#$OF_OkCM0sR_4f4Q4(:njd4ncc
+cRS08NNP8=#O$M_kOFMs0C_f.RQ(44ndj:nj6cc
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,5jyd:?V5V.?:?54Vj:5?0V:2222RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"jjj4
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@dd:.44:4:4.d:+d.j1:]Y_hBw_1vM0CG\M3k4Ed_#O$M_kOFMs0CRnf4d:6jdc(j.q(Rp)a qu_q NXR._c4UjjjRHbsl1R]Y_hBw_1vM0CG\M3k4Ed_#O$M_kOFMs0C_S(
+OLFlF=k0kdM4_$E#MOO_F0kMC(s_R4fmnjd6:jd(cR.(
+NS80=NNEM#$OF_OkCM0sR_.f4Q4(:njdUn6d
+(RS08NNEL=#O$M_kOFMs0C_fdRQ(44ndj:nj(4(SR
+8NN0O#=E$_MOOMFk0_CsjQRf4n4(jn:dU(.gR8
+SN80N=$E#MOO_F0kMC4s_R4fQ4j(n:gdn6R6(;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,yd!5??5.554?j:?V002:22:0:R02;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRUjjj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:n.j:.c:j(n:+kj:ME4_#O$M_N#00dC_Rnf4d:6jd(UU.qcRp)a qu_q NXRc g_ R blsHR4kM_$E#M#O_0CN0_jd_
+FSOlkLF0M=k4#_E$_MO#00NC__djmRf46ndjU:dUc(.R8
+SNN0N=$E#M#O_0CN0_fdRQ(44ndj:Udc4cSR
+8NN0L#=E$_MO#00NCR_4f4Q4(:njdcU6j;cR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+RA44y,j!?54Vj:5?0V:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blCR"C"CC;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4dd:4gc4:dg+:(jM:k4#_P$_MO#00NCR_.fd4n6dj:U.U(cpRqaq )_ quXcRNg _ b RsRHlk_M4PM#$O0_#N_0C.
+_jSlOFL0Fk=4kM_$P#M#O_0CN0_j._R4fmnjd6:UdU(R.c
+NS80=NNPM#$O0_#N_0CdQRf4n4(jU:dcc4dR8
+SNL0N=$P#M#O_0CN0_f4RQ(44ndj:Uj6cc
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;A44R,!jy5V4?:?5jV2:02
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRC"CC;C"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4.d:ccU::U.c:j(+:#8_CE0_#O$M_kOFMs0CRnf4d:6jdn(ncq.Rp)a qu_q NXRc g_ R blsHR#8_CE0_#O$M_kOFMs0C
+FSOlkLF0_=8#_C0EM#$OF_OkCM0smRf46ndj(:dn.ncR8
+SNN0N=$E#M#O_0CN0_fnRQ(44ndj:(6.j.SR
+8NN0L#=E$_MO#00NCR_jf4Q4(:njdd(d.;.R
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+RA44y,j!?54Vj:5?0V:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blCR"C"CC;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4dd:n4cn:d4+:(j_:8#_C0PM#$OF_OkCM0s4Rfnjd6:6dU.R.gq pa)qq_uR XN_cg RHbsl_R8#_C0PM#$OF_OkCM0sO
+SFFlLk80=_0#C_$P#MOO_F0kMCfsRmd4n6dj:U.6.gSR
+8NN0N#=P$_MO#00NCR_nf4Q4(:njdnUjd
+gRS08NNPL=#O$M_N#00jC_R4fQ4j(n:4dUgRjg;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;4
+ARj4,y4!5?5V:j:?V0R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRCCCC"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:44c::d44:c46j.+:4kM_MDHCF_OkCM0sH_#o:rg4f9Rdndjcg:ddnd6Raqp _)qqXu RjN4(nd_BRnBblsHR4kM_MDHCF_OkCM0sH_#o9rg
+FSOlkLF0M=k4H_DMOC_F0kMC#s_HOo_FFlLkg0r9mRfdndjcg:ddnd6R8
+SNN0N=MDHCF_OkCM0sH_#oR_(f4Q4(:njd(UUn
+nRS08NNDL=H_MCOMFk0_Cs#_HoUQRf4n4(jg:djnjdRO
+SHkM=MD4_H_MCOMFk0_Cs#_HoO0FkrR(9fUQ.d:ccdnUUd;nR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+RobO;HM
+RA44y,455.?4*?j5Vj?::02!2fj:4!5?0V:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"nO;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+@sR@:4d4:c4d44:c64:.:+jk_M4DCHM_kOFMs0C_o#Hr4g:9dRfdcjn:ddgdR6nq pa)qq_uR XNc4j4q_66bqRsRHlk_M4DCHM_kOFMs0C_o#Hr
+U9SlOFL0Fk=4kM_MDHCF_OkCM0sH_#oF_OlkLF09rURdfmdcjn:ddgdR6n
+NS80=NNDCHM_kOFMs0C_o#H_f(RQ(44ndj:UnU(nSR
+O=HMk_M4DCHM_kOFMs0C_o#H_kOF09rnR.fQUcdc:UdUnRdn;b
+oRlOFL0Fk;b
+oR08NN
+N;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"66NN
+";N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo's;
+R4@@dc:444:d:44c:+6.jM:k4H_DMOC_F0kMC#s_Hgor:R49fd.Ucdc:UdUnnpRqaq )_ quX4RNj_((nBBn_UUjjsRbHklRMD4_H_MCOMFk0_Cs#rHo(S9
+OLFlF=k0k_M4DCHM_kOFMs0C_o#H_lOFL0FkrR(9f.md(:gcddgd6
+nRSkOF0M=k4H_DMOC_F0kMC#s_HOo_Frk0(f9Rmd.Ucdc:UdUnnSR
+8NN0NH=DMOC_F0kMC#s_H6o_R4fQ4j(n:.dU4Rgn
+NS80=NLDCHM_kOFMs0C_o#H_fnRQ(44ndj:Ug.4nSR
+O=HMk_M4DCHM_kOFMs0C_o#H_kOF09r6R.fQUcj(:UdUdRnn;b
+oRlOFL0Fk;b
+oRkOF0o;
+bNR80;NN
+Rob8NN0Lo;
+bHROMA;
+4,R44.y5??54jj*5?0V:2f:!j!2:5V4?:202RA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"Uj;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+@sR@:4d4:c4d44:c64:.:+jk_M4DCHM_kOFMs0C_o#Hr4g:9.RfUcdc:UdUnRdnq pa)qq_uR XN(4j(q_66Uq_jRUjblsHR4kM_MDHCF_OkCM0sH_#o9rn
+FSOlkLF0M=k4H_DMOC_F0kMC#s_HOo_FFlLkn0r9mRfdg.(cg:ddnd6RO
+SF=k0k_M4DCHM_kOFMs0C_o#H_kOF09rnR.fmUcdc:UdUnRdn
+NS80=NNDCHM_kOFMs0C_o#H_f6RQ(44ndj:Ug.4nSR
+8NN0LH=DMOC_F0kMC#s_Hno_R4fQ4j(n:.dU4Rgn
+HSOMM=k4H_DMOC_F0kMC#s_HOo_Frk0cf9RQj.U(dc:UnUdn
+R;oObRFFlLk
+0;oObRF;k0
+Rob8NN0No;
+bNR80;NL
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNU"N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;R
+s@d@4:44c::d44:c46j.+:4kM_MDHCF_OkCM0sH_#o:rg4f9R.(UjcU:dUndnRaqp _)qqXu RjN4(n(_B_nBUjjURHbslMRk4H_DMOC_F0kMC#s_H6or9O
+SFFlLkk0=MD4_H_MCOMFk0_Cs#_HoOLFlFrk06f9Rm6d..dc:g6ddnSR
+O0Fk=4kM_MDHCF_OkCM0sH_#oF_Ok60r9mRf.(UjcU:dUndnR8
+SNN0N=MDHCF_OkCM0sH_#oR_df4Q4(:njdgU4.
+nRS08NNDL=H_MCOMFk0_Cs#_HocQRf4n4(jU:d4ng.RO
+SHkM=MD4_H_MCOMFk0_Cs#_HoO0FkrRd9f(Q.U:jcdjUUg;nR
+RobOLFlF;k0
+RobO0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oRMOH;4
+AR44,y?5.5j4?*?5jV2:0:j!f25:!4:?V0R22;.
+ARj4,y.!5??545Vj?::02002:2
+R;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRO"nU;j"
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';s@R@44d:cd4:4c:44.:6+kj:MD4_H_MCOMFk0_Cs#rHog9:4RUf.j:(cddUUnqnRp)a qu_q NXR4(j(_66qqj_UUbjRsRHlk_M4DCHM_kOFMs0C_o#Hr
+c9SlOFL0Fk=4kM_MDHCF_OkCM0sH_#oF_OlkLF09rcRdfm.c6.:ddgdR6n
+FSOkk0=MD4_H_MCOMFk0_Cs#_HoO0FkrRc9fUm.j:(cddUUn
+nRS08NNDN=H_MCOMFk0_Cs#_HodQRf4n4(jU:d4ng.R8
+SNL0N=MDHCF_OkCM0sH_#oR_cf4Q4(:njdgU4.
+nRSMOH=4kM_MDHCF_OkCM0sH_#oF_Ok.0r9QRf.j(UcU:dUnjgRo;
+bFROlkLF0o;
+bFROk
+0;o8bRNN0N;b
+oR08NN
+L;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Uj;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+@sR@:4d4:c4d44:c64:.:+jk_M4DCHM_kOFMs0C_o#Hr4g:9.Rf(cUj:UdUjRgnq pa)qq_uR XN(4j(B_nnUB_jRUjblsHR4kM_MDHCF_OkCM0sH_#o9rd
+FSOlkLF0M=k4H_DMOC_F0kMC#s_HOo_FFlLkd0r9mRfd6..cg:ddnd6RO
+SF=k0k_M4DCHM_kOFMs0C_o#H_kOF09rdR.fm(cUj:UdUjRgn
+NS80=NNDCHM_kOFMs0C_o#H_f4RQ(44ndj:U64nnSR
+8NN0LH=DMOC_F0kMC#s_H.o_R4fQ4j(n:4dUnR6n
+HSOMM=k4H_DMOC_F0kMC#s_HOo_Frk04f9RQ6.(ddc:U.(Un
+R;oObRFFlLk
+0;oObRF;k0
+Rob8NN0No;
+bNR80;NL
+RobO;HM
+RA44y,455.?4*?j5Vj?::02!2fj:4!5?0V:2;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UnOj
+";N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo's;
+R4@@dc:444:d:44c:+6.jM:k4H_DMOC_F0kMC#s_Hgor:R49fU.(jdc:UgUjnpRqaq )_ quX4RNj_((6qq6_UUjjsRbHklRMD4_H_MCOMFk0_Cs#rHo.S9
+OLFlF=k0k_M4DCHM_kOFMs0C_o#H_lOFL0FkrR.9f.md.:6cddgd6
+nRSkOF0M=k4H_DMOC_F0kMC#s_HOo_Frk0.f9RmU.(jdc:UgUjnSR
+8NN0NH=DMOC_F0kMC#s_H4o_R4fQ4j(n:4dUnR6n
+NS80=NLDCHM_kOFMs0C_o#H_f.RQ(44ndj:U64nnSR
+O=HMk_M4DCHM_kOFMs0C_o#H_ON_Frk04f9RQ6.(ddc:U.(Un
+R;oObRFFlLk
+0;oObRF;k0
+Rob8NN0No;
+bNR80;NL
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNU"N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;R
+s@d@4:44c::d44:c46j.+:4kM_MDHCF_OkCM0sH_#o:rg4f9R.d(6cU:d(nU.Raqp _)qqXu R.N6_jjjjU_UUbURsRHlk_M4DCHM_kOFMs0C_o#H_4Nr9O
+SF=k0k_M4DCHM_kOFMs0C_o#H_ON_Frk04f9Rm6.(ddc:U.(UnSR
+8NN0N_=8#_C0EM#$OF_OkCM0sQRf.g4jcU:d4ndUR8
+SNL0N=MDHCF_OkCM0sH_#oR_jf4Q4(:njddU4U;nR
+RobO0Fk;b
+oR08NN
+N;o8bRNL0N;4
+ARj4,y;VR
+RA.4y,j!?545Vj?::020;2R
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bljR"j"UU;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4d4:c4d44:c64:.:+jk_M4DCHM_kOFMs0C_o#Hr4g:9.Rf(c6d:(dUUR.nq pa)qq_uR XN_6dnnnn_UUUUsRbHklRMD4_H_MCOMFk0_Cs#rHo4S9
+OLFlF=k0k_M4DCHM_kOFMs0C_o#H_lOFL0FkrR49f6m.n:Ucddgd6
+nRSkOF0M=k4H_DMOC_F0kMC#s_HOo_Frk04f9Rm6.(ddc:U.(UnSR
+8NN0N_=8#_C0EM#$OF_OkCM0sQRf.g4jcU:d4ndUR8
+SNL0N=MDHCF_OkCM0sH_#oR_jf4Q4(:njddU4U;nR
+RobOLFlF;k0
+RobO0Fk;b
+oR08NN
+N;o8bRNL0N;4
+AR44,y?54jj*5?0V:2f:!j;2R
+RA.4y,j!?545Vj?::020;2R
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"n"UU;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4d4:4.d44:46.:c:+jk_M.OkFDlOM_F0kMCMs_CrG0g9:jRdf.(:djddgd6qnRp)a qu_q NXR4dj(_nnBBsRbHklRMO._FlDkMF_OkCM0sC_MGg0r9O
+SFFlLkk0=MO._FlDkMF_OkCM0sC_MGO0_FFlLkg0r9mRf.dd(jg:ddnd6R8
+SNN0N=DOFk_lMOMFk0_Cs#_HoUQRf4n4(jU:dUn(nR8
+SNL0N=DOFk_lMOMFk0_Cs#_HogQRf4n4(jg:djnjdRO
+SHkM=MO._FlDkMF_OkCM0sC_MGO0_Frk0(f9RQj4g4dj:UdUnn
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;oObRH
+M;A44R,54y.4?5?5j*j:?V0!2:f:j2!?54V2:02
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRO"nn;O"
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';s@R@44d:4d.:44:4.c:6+kj:MO._FlDkMF_OkCM0sC_MGg0r:Rj9f(.dddj:g6ddnpRqaq )_ quX4RNj_c46qq6RHbslMRk.F_ODMkl_kOFMs0C_GMC09rU
+FSOlkLF0M=k.F_ODMkl_kOFMs0C_GMC0F_OlkLF09rUR.fmdj(d:ddgdR6n
+NS80=NNOkFDlOM_F0kMC#s_HUo_R4fQ4j(n:UdU(Rnn
+HSOMM=k.F_ODMkl_kOFMs0C_GMC0F_Okn0r9QRf44gjjU:dUnndRo;
+bFROlkLF0o;
+bNR80;NN
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRN"66;N"
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';s@R@44d:4d.:44:4.c:6+kj:MO._FlDkMF_OkCM0sC_MGg0r:Rj9fj4g4dj:UdUnnpRqaq )_ quX4RNj_((nBBn_UUjjsRbHklRMO._FlDkMF_OkCM0sC_MG(0r9O
+SFFlLkk0=MO._FlDkMF_OkCM0sC_MGO0_FFlLk(0r9mRf.ndcjg:ddnd6RO
+SF=k0k_M.OkFDlOM_F0kMCMs_C_G0O0FkrR(9fgm4j:4jdnUUd
+nRS08NNON=FlDkMF_OkCM0sH_#oR_nf4Q4(:njd4U.g
+nRS08NNOL=FlDkMF_OkCM0sH_#oR_(f4Q4(:njd4U.g
+nRSMOH=.kM_DOFk_lMOMFk0_CsM0CG_kOF09r6R4fQUj(c:UdUdRnn;b
+oRlOFL0Fk;b
+oRkOF0o;
+bNR80;NN
+Rob8NN0Lo;
+bHROMA;
+4,R44.y5??54jj*5?0V:2f:!j!2:5V4?:202RA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"Uj;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+@sR@:4d4:4.d44:46.:c:+jk_M.OkFDlOM_F0kMCMs_CrG0g9:jRgf4j:4jdnUUdqnRp)a qu_q NXR4(j(_66qqj_UUbjRsRHlk_M.OkFDlOM_F0kMCMs_CrG0nS9
+OLFlF=k0k_M.OkFDlOM_F0kMCMs_C_G0OLFlFrk0nf9Rmc.dndj:g6ddnSR
+O0Fk=.kM_DOFk_lMOMFk0_CsM0CG_kOF09rnR4fmgjj4:UdUnRdn
+NS80=NNOkFDlOM_F0kMC#s_Hno_R4fQ4j(n:.dU4Rgn
+NS80=NLOkFDlOM_F0kMC#s_H(o_R4fQ4j(n:.dU4Rgn
+HSOMM=k.F_ODMkl_kOFMs0C_GMC0F_Okc0r9QRf4cU(jU:dUndnRo;
+bFROlkLF0o;
+bFROk
+0;o8bRNN0N;b
+oR08NN
+L;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Uj;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+@sR@:4d4:4.d44:46.:c:+jk_M.OkFDlOM_F0kMCMs_CrG0g9:jRUf4(:cjddUUnqnRp)a qu_q NXR4(j(_nnBBj_UUbjRsRHlk_M.OkFDlOM_F0kMCMs_CrG06S9
+OLFlF=k0k_M.OkFDlOM_F0kMCMs_C_G0OLFlFrk06f9Rm4.dgdj:g6ddnSR
+O0Fk=.kM_DOFk_lMOMFk0_CsM0CG_kOF09r6R4fmUj(c:UdUdRnn
+NS80=NNOkFDlOM_F0kMC#s_Hco_R4fQ4j(n:4dUgR.n
+NS80=NLOkFDlOM_F0kMC#s_H6o_R4fQ4j(n:4dUgR.n
+HSOMM=k.F_ODMkl_kOFMs0C_GMC0F_Okd0r9QRf4(UcjU:dUnjgRo;
+bFROlkLF0o;
+bFROk
+0;o8bRNN0N;b
+oR08NN
+L;oObRH
+M;A44R,54y.4?5?5j*j:?V0!2:f:j2!?54V2:02
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnjOU"N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;R
+s@d@4:.44::d44:4.6jc+:.kM_DOFk_lMOMFk0_CsM0CGrjg:94RfUj(c:UdUdRnnq pa)qq_uR XN(4j(q_66Uq_jRUjblsHR.kM_DOFk_lMOMFk0_CsM0CGr
+c9SlOFL0Fk=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrRc9fdm.4:gjddgd6
+nRSkOF0M=k.F_ODMkl_kOFMs0C_GMC0F_Okc0r9mRf4cU(jU:dUndnR8
+SNN0N=DOFk_lMOMFk0_Cs#_HocQRf4n4(jU:d4ng.R8
+SNL0N=DOFk_lMOMFk0_Cs#_Ho6QRf4n4(jU:d4ng.RO
+SHkM=MO._FlDkMF_OkCM0sC_MGO0_Frk0.f9RQc4U(dj:UgUjn
+R;oObRFFlLk
+0;oObRF;k0
+Rob8NN0No;
+bNR80;NL
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNU"N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;R
+s@d@4:.44::d44:4.6jc+:.kM_DOFk_lMOMFk0_CsM0CGrjg:94RfUjc(:UdUjRgnq pa)qq_uR XN(4j(B_nnUB_jRUjblsHR.kM_DOFk_lMOMFk0_CsM0CGr
+d9SlOFL0Fk=.kM_DOFk_lMOMFk0_CsM0CG_lOFL0FkrRd9f.m.g:.jddgd6
+nRSkOF0M=k.F_ODMkl_kOFMs0C_GMC0F_Okd0r9mRf4(UcjU:dUnjgR8
+SNN0N=DOFk_lMOMFk0_Cs#_Ho.QRf4n4(jU:d4nn6R8
+SNL0N=DOFk_lMOMFk0_Cs#_HodQRf4n4(jU:d4nn6RO
+SHkM=MO._FlDkMF_OkCM0sC_MGO0_Frk04f9RQ.4Ujdj:U.(Un
+R;oObRFFlLk
+0;oObRF;k0
+Rob8NN0No;
+bNR80;NL
+RobO;HM
+RA44y,455.?4*?j5Vj?::02!2fj:4!5?0V:2;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UnOj
+";N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo's;
+R4@@d4:4.4:d:.44:+6cjM:k.F_ODMkl_kOFMs0C_GMC0:rgjf9R4(UcjU:dUnjgRaqp _)qqXu RjN4(6(_q_6qUjjURHbslMRk.F_ODMkl_kOFMs0C_GMC09r.
+FSOlkLF0M=k.F_ODMkl_kOFMs0C_GMC0F_OlkLF09r.R.fm.jg.:ddgdR6n
+FSOkk0=MO._FlDkMF_OkCM0sC_MGO0_Frk0.f9Rmc4U(dj:UgUjnSR
+8NN0NF=ODMkl_kOFMs0C_o#H_f.RQ(44ndj:U64nnSR
+8NN0LF=ODMkl_kOFMs0C_o#H_fdRQ(44ndj:U64nnSR
+O=HMk_M.OkFDlOM_F0kMCMs_C_G0O0FkrRj9fUQ4.:jjdUU(.;nR
+RobOLFlF;k0
+RobO0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U6Nj
+";N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo's;
+R4@@d4:4.4:d:.44:+6cjM:k.F_ODMkl_kOFMs0C_GMC0:rgjf9R4jU.jU:d(nU.Raqp _)qqXu RdN6_nnnnU_UUbURsRHlk_M.OkFDlOM_F0kMCMs_CrG04S9
+OLFlF=k0k_M.OkFDlOM_F0kMCMs_C_G0OLFlFrk04f9Rmd4n6dj:g6ddnSR
+O0Fk=.kM_DOFk_lMOMFk0_CsM0CG_kOF09r4R4fmUj.j:(dUUR.n
+NS80=NNOkFDlOM_F0kMC#s_Hjo_R4fQ4j(n:4dUdRUn
+NS80=NLOkFDlOM_F0kMC#s_H4o_R4fQ4j(n:4dUdRUn;b
+oRlOFL0Fk;b
+oRkOF0o;
+bNR80;NN
+Rob8NN0LA;
+4,R444y5?5j*j:?V0!2:fRj2;.
+ARj4,y4!5??5jV2:0:R02;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnUnU"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@d@4:.44::d44:4.6jc+:.kM_DOFk_lMOMFk0_CsM0CGrjg:94RfUj.j:(dUUR.nq pa)qq_uR XN_6.6666_UUUUsRbHklRMO._FlDkMF_OkCM0sC_MGj0r9O
+SF=k0k_M.OkFDlOM_F0kMCMs_C_G0O0FkrRj9fUm4.:jjdUU(.
+nRS08NNON=FlDkMF_OkCM0sH_#oR_jf4Q4(:njddU4U
+nRS08NNOL=FlDkMF_OkCM0sH_#oR_4f4Q4(:njddU4U;nR
+RobO0Fk;b
+oR08NN
+N;o8bRNL0N;4
+ARj4,y?5jV2:0RA;
+.,R4j5y!4j?5?0V:22:0RN;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U66U
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'b;
+R4@@:44::.4:+0.:sRkCfjj:Rk0sCsR0keCRB
+B;NsHRCFoHMPR'o;N'
+fbRjR:jV#NDChRt7hRt7@;
+
+
+
+
+ftell;
+@ERMRI FsRNPo_MOF0DsFR0MCD0H#;P
+NR#3H_k#FsROC4N;
+PDR3HMMCFgRdUN;
+PHR3#8PED;R4
+RNP3_H#PDE8R
+4;N3PRFosHhCNlRo"PNF_OMF0sD
+";N#PR$bM_sCC#sRPC4N;
+PNR3DOlN_0bNEF_OkRM04N;
+PFR3sPHoHMCINRlC'ELCN;P'
+RNP3#EN0HHlM4oR;P
+NRH3k__MD#ODN cRdcn6(;R
+HDCHM_kOFMs0C_o#H_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HHRDMOC_F0kMC#s_H.o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;R
+HDCHM_kOFMs0C_o#H_
+4;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HHRDMOC_F0kMC#s_Hdo_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;R
+HDCHM_kOFMs0C_o#H_
+n;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HHRDMOC_F0kMC#s_H6o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;R
+HDCHM_kOFMs0C_o#H_
+c;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HHRDMOC_F0kMC#s_H(o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs""HM;R
+HDCHM_kOFMs0C_o#H_
+U;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+4;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+.;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+U;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+d;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+6;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+c;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+g;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+(;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HFRODMkl_kOFMs0C_o#H_
+n;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";FFR0oCoD_kOFMs0C_o#H_
+j;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+0FRFDooCF_OkCM0sH_#o;_4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H.o_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+Ro0Fo_DCOMFk0_Cs#_HodN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_
+c;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+0FRFDooCF_OkCM0sH_#o;_6
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_Hno_;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"F;
+Ro0Fo_DCOMFk0_Cs#_Ho(N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_
+U;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+0FRFDooCF_OkCM0sH_#o;_g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_jN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;44
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_.N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;4d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_cN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;46
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_nN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;4(
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H4o_UN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;4g
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H.o_jN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;.4
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H.o_.N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";FFR0oCoD_kOFMs0C_o#H_;.d
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoDOC_F0kMC#s_H.o_cN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";H_RECLMND#C_H
+o;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";F;Ro
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+FLN;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HbR3FNs0Ds8HRk"F0
+";H_RPCLMND#C_H
+o;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";F;Rs
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRF"k0;R
+F0oFoD#C_H
+o;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sFR"k;0"
+kHRM8n_DO$_F0kMCjs__
+G;N3HR#FDbs8HoH"sRHkMF0
+";N3HRb0FsNHD8sHR"M
+";HDRO H_bM;_O
+RNH3b#DFosH8RHs"FHMk;0"
+RNH3sbF08NDH"sRH;M"
+RoMO_D b_HMON;
+MOR3D FORo"PND|O H_bM
+";N3MROODF 8_Co"CRsCH#"N;
+MHR3#D_OFRO 4s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jR(f4ndj:n(cUcpRqaq )_ quXVRVc.cU_jwwjsRbH0lRFDooCF_OkCM0sH_#ocr.9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R.cf(m4ndj:n(cUcSR
+O=D O_D b_HMO8
+SN80N=7th
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};A44R,!jy5Vd?:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GcR.;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jR(f4ndj:njdncpRqaq )_ quXVRVc.cU_jwwjsRbH0lRFDooCF_OkCM0sH_#odr.9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R.df(m4ndj:njdncSR
+O=D O_D b_HMO8
+SN80N=7th
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};A44R,!jy5Vd?:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GdR.;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jR(f4ndj:n.(dcpRqaq )_ quXVRVc.cU_jwwjsRbH0lRFDooCF_OkCM0sH_#o.r.9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R..f(m4ndj:n.(dcSR
+O=D O_D b_HMO8
+SN80N=7th
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};A44R,!jy5Vd?:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G.R.;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jR(f4ndj:nnnjcpRqaq )_ quXVRVc.cU_jwwjsRbH0lRFDooCF_OkCM0sH_#o4r.9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R.4f(m4ndj:nnnjcSR
+O=D O_D b_HMO8
+SN80N=7th
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};A44R,!jy5Vd?:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G4R.;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRV64dU6n_qR6qblsHRo0Fo_DCOMFk0_Cs#rHo.
+j9SosCF=k00oFoDOC_F0kMC#s_H.o_jmRf4j(n:jd((Rnn
+DSO D=O H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oj_.R4fQ4j(n:(dg4R4U
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Ok40rUf9RQn.jddj:gg.dU
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5?5j*j:?V0!2:fRj2;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GjR.;H
+NRO3#DVs_V;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"6N;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1) Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_4UnBBnRHbslFR0oCoD_kOFMs0C_o#Hr94g
+CSso0Fk=o0Fo_DCOMFk0_Cs#_Ho4fgRmn4(jn:dgncgRO
+SDO =Db _HOM_
+NS80=NN0oFoDOC_F0kMC#s_H4o_UQRf4n4(jg:d(U44R8
+SNL0N=o0Fo_DCOMFk0_Cs#_Ho4fgRQ(44ndj:g4(4USR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=o0Fo_DCOMFk0_Cs#_HoO0Fkr94(R.fQjjdn:.dgdRgU;b
+oRosCF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5??54jj*5?0V:2f:!j!2:5V4?:202RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC4GRgN;
+H#R3O_DsV4VR;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnOOn"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_kOFMs0C_o#Hr:.cjf9Rc.c(.U:dgU.gRaqp _)qqXu R4VVd.n._66qqj_UUbjRsRHl0oFoDOC_F0kMC#s_H4orUS9
+sFCok00=FDooCF_OkCM0sH_#oU_4R4fm(:njd4nnd
+cRSkOF0F=0oCoD_kOFMs0C_o#H_kOF0Ur49mRf.djnjg:d.UdgRO
+SDO =Db _HOM_
+NS80=NN0oFoDOC_F0kMC#s_H4o_UQRf4n4(jU:d6Ug6R8
+SNL0N=o0Fo_DCOMFk0_Cs#_Ho4fgRQ(44ndj:U66gUSR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=o0Fo_DCOMFk0_Cs#_HoO0Fkr94nR.fQjjdn:.dg4R.U;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR;4U
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRN"6U;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRVn4d.n._B_nBUjjURHbslFR0oCoD_kOFMs0C_o#Hr94(
+CSso0Fk=o0Fo_DCOMFk0_Cs#_Ho4f(Rmn4(jn:dccUnRO
+SF=k00oFoDOC_F0kMC#s_HOo_Frk04R(9fjm.d:njddg.g
+URS OD= OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_R4nf4Q4(:njdgU66
+URS08NN0L=FDooCF_OkCM0sH_#o(_4R4fQ4j(n:6dUgR6U
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Ok40r6f9RQj.jgdj:g..4U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.5j4?*?5jV2:0:j!f25:!4:?V0R22;.
+ARj4,y.!5??545Vj?::02002:2
+R;N3HRs_0DFosHMCNlRF"0oCoD_kOFMs0C_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG4
+(;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UnOj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4.dn.q_66Uq_jRUjblsHRo0Fo_DCOMFk0_Cs#rHo4
+n9SosCF=k00oFoDOC_F0kMC#s_H4o_nmRf4j(n:(dndR.c
+FSOk00=FDooCF_OkCM0sH_#oF_Ok40rnf9Rmd.jndj:g..4USR
+O=D O_D b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_Ho4fnRQ(44ndj:UU6nUSR
+8NN0LF=0oCoD_kOFMs0C_o#H_R4(f4Q4(:njdnU6U
+URSDNOsM=knD_8$F_OkCM0s__jG#
+SO!Ds=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:gdU.RgU
+HSOMF=0oCoD_kOFMs0C_o#H_kOF0cr49QRf.gjjjg:d4UU6Ro;
+bCRso0Fk;b
+oRkOF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GnR4;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1) Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..nBBn_UUjjsRbH0lRFDooCF_OkCM0sH_#o6r49s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R46f(m4ndj:ng.n.SR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0Fkr946R.fmjjjg:.dg4R.U
+DSO D=O H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oc_4R4fQ4j(n:6dUnRUU
+NS80=NL0oFoDOC_F0kMC#s_H4o_6QRf4n4(jU:d6UnURN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk04Rd9fgQ4U:.jdUg46;UR
+RobsFCok
+0;oObRF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5??54jj*5?0V:2f:!j!2:5V4?:202RA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR;46
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRO"nU;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRVn4d.6._q_6qUjjURHbslFR0oCoD_kOFMs0C_o#Hr94c
+CSso0Fk=o0Fo_DCOMFk0_Cs#_Ho4fcRmn4(jn:d4.6jRO
+SF=k00oFoDOC_F0kMC#s_HOo_Frk04Rc9fjm.j:gjdUg46
+URS OD= OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_R4cf4Q4(:njdcU64
+URS08NN0L=FDooCF_OkCM0sH_#o6_4R4fQ4j(n:6dUcR4U
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Ok40r.f9RQU4g.dj:gU46U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC4GRcN;
+H#R3O_DsV4VR;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_kOFMs0C_o#Hr:.cjf9Rc.c(.U:dgU.gRaqp _)qqXu R4VVd.n._nnBBj_UUbjRsRHl0oFoDOC_F0kMC#s_H4ordS9
+sFCok00=FDooCF_OkCM0sH_#od_4R4fm(:njd.njd
+.RSkOF0F=0oCoD_kOFMs0C_o#H_kOF0dr49mRf4.gUjg:d4UU6RO
+SDO =Db _HOM_
+NS80=NN0oFoDOC_F0kMC#s_H4o_.QRf4n4(jU:d6Uc4R8
+SNL0N=o0Fo_DCOMFk0_Cs#_Ho4fdRQ(44ndj:U46cUSR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=o0Fo_DCOMFk0_Cs#_HoO0Fkr944R4fQgj66:4dg6RUU;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.4?5?5j*j:?V0!2:f:j2!?54V2:02
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8GdR4;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1) Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..6qq6_UUjjsRbH0lRFDooCF_OkCM0sH_#o.r49s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R4.f(m4ndj:6nUjjSR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0Fkr94.R4fmgjU.:4dg6RUU
+DSO D=O H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#o._4R4fQ4j(n:6dU4RcU
+NS80=NL0oFoDOC_F0kMC#s_H4o_dQRf4n4(jU:d6U4cRN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk04Rj9fgQ46:6jddg44;UR
+RobsFCok
+0;oObRF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5?5j*j:?V0!2:fRj2;.
+ARj4,y.!5??545Vj?::02002:2
+R;N3HRs_0DFosHMCNlRF"0oCoD_kOFMs0C_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCG4
+.;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4.dn.B_nnUB_jRUjblsHRo0Fo_DCOMFk0_Cs#rHo4
+49SosCF=k00oFoDOC_F0kMC#s_H4o_4mRf4j(n:nd6UR(j
+FSOk00=FDooCF_OkCM0sH_#oF_Ok40r4f9Rm64g6dj:gU46USR
+O=D O_D b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_Ho4fjRQ(44ndj:Uc64USR
+8NN0LF=0oCoD_kOFMs0C_o#H_R44f4Q4(:njd4U6c
+URSDNOsM=knD_8$F_OkCM0s__jG#
+SO!Ds=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:gdU.RgU
+HSOMF=0oCoD_kOFMs0C_o#H_kOF09rgR4fQgj.U:4dgdR4U;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.4?5?5j*j:?V0!2:f:j2!?54V2:02
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G4R4;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1) Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..6qq6_UUjjsRbH0lRFDooCF_OkCM0sH_#ojr49s
+SCkoF0F=0oCoD_kOFMs0C_o#H_R4jf(m4ndj:6j6njSR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0Fkr94jR4fmgj66:4dgdR4U
+DSO D=O H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oj_4R4fQ4j(n:cdUUR(U
+NS80=NL0oFoDOC_F0kMC#s_H4o_4QRf4n4(jU:dcUU(RN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk0Uf9RQ.4gUdj:gc4jU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC4GRjN;
+H#R3O_DsV4VR;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6jNU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_kOFMs0C_o#Hr:.cjf9Rc.c(.U:dgU.gRaqp _)qqXu R4VVd.n._nnBBj_UUbjRsRHl0oFoDOC_F0kMC#s_Hgor9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_fgRmn4(j6:d.U.dRO
+SF=k00oFoDOC_F0kMC#s_HOo_Frk0gf9Rm.4gUdj:g44dUSR
+O=D O_D b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_HoUQRf4n4(jU:dcUU(R8
+SNL0N=o0Fo_DCOMFk0_Cs#_HogQRf4n4(jU:dcUU(RN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk0(f9RQj4g4dj:gc4jU
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.5j4?*?5jV2:0:j!f25:!4:?V0R22;.
+ARj4,y.!5??545Vj?::02002:2
+R;N3HRs_0DFosHMCNlRF"0oCoD_kOFMs0C_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGgN;
+H#R3O_DsV4VR;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRnjOU"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk0.N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_kOFMs0C_o#Hr:.cjf9Rc.c(.U:dgU.gRaqp _)qqXu R4VVd.n._66qqj_UUbjRsRHl0oFoDOC_F0kMC#s_HUor9s
+SCkoF0F=0oCoD_kOFMs0C_o#H_fURmn4(j6:djUgnRO
+SF=k00oFoDOC_F0kMC#s_HOo_Frk0Uf9Rm.4gUdj:gc4jUSR
+O=D O_D b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_HoUQRf4n4(jU:dcUnjR8
+SNL0N=o0Fo_DCOMFk0_Cs#_HogQRf4n4(jU:dcUnjRN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.USR
+O=HM0oFoDOC_F0kMC#s_HOo_Frk0nf9RQj4g4dj:g(j(U
+R;osbRCkoF0o;
+bFROk
+0;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob#sOD;b
+oRMOH;4
+AR44,y?5.jj*5?0V:2f:!j;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMCUGR;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0bl6R"N"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1) Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..nBBn_UUjjsRbH0lRFDooCF_OkCM0sH_#o9r(
+CSso0Fk=o0Fo_DCOMFk0_Cs#_Ho(mRf4j(n:dd6cR.U
+FSOk00=FDooCF_OkCM0sH_#oF_Ok(0r9mRf44gjjg:d4UjcRO
+SDO =Db _HOM_
+NS80=NN0oFoDOC_F0kMC#s_Hno_R4fQ4j(n:cdUnRjU
+NS80=NL0oFoDOC_F0kMC#s_H(o_R4fQ4j(n:cdUnRjU
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Ok60r9QRf4cU(jg:djU((Ro;
+bCRso0Fk;b
+oRkOF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobO;HM
+RA44y,455.?4*?j5Vj?::02!2fj:4!5?0V:2;2R
+RA.4y,j!?5.554?j:?V002:22:0RN;
+HsR30FD_sMHoNRlC"o0Fo_DCOMFk0_Cs#"Ho;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC(GR;H
+NRO3#DVs_V;R4
+RNH38lFC;R.
+RNH3NCMLRDCjN;
+HDR3ko0blnR"O"Uj;H
+NR$3#M_OElCF8R
+4;N3HR#_klDOk0_bHMk.0R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1) Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4g.:g::cg6g::o0Fo_DCOMFk0_Cs#rHo.jc:9cRfc.(.:gdU.RgUq pa)qq_uR XVdV4n_..6qq6_UUjjsRbH0lRFDooCF_OkCM0sH_#o9rn
+CSso0Fk=o0Fo_DCOMFk0_Cs#_HonmRf4j(n:ndcdRdn
+FSOk00=FDooCF_OkCM0sH_#oF_Okn0r9mRf44gjjg:djU((RO
+SDO =Db _HOM_
+NS80=NN0oFoDOC_F0kMC#s_Hno_R4fQ4j(n:cdUdRdU
+NS80=NL0oFoDOC_F0kMC#s_H(o_R4fQ4j(n:cdUdRdU
+OSNDks=M8n_DO$_F0kMCjs__SG
+#sOD!F=0oCoD_o#H_jj__oj_4QRfc.c(.U:dgU.gRO
+SH0M=FDooCF_OkCM0sH_#oF_Okc0r9QRf4cU(jg:djU6jRo;
+bCRso0Fk;b
+oRkOF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;o#bRO;Ds
+RobO;HM
+RA44y,45j.?*?5jV2:0:j!f2
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rn
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRN"6U;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRVn4d.n._B_nBUjjURHbslFR0oCoD_kOFMs0C_o#Hr
+69SosCF=k00oFoDOC_F0kMC#s_H6o_R4fm(:njdnc(j
+nRSkOF0F=0oCoD_kOFMs0C_o#H_kOF09r6R4fmUj(c:jdg(R(U
+DSO D=O H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oR_cf4Q4(:njddUcd
+URS08NN0L=FDooCF_OkCM0sH_#oR_6f4Q4(:njddUcd
+URSDNOsM=knD_8$F_OkCM0s__jG#
+SO!Ds=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:gdU.RgU
+HSOMF=0oCoD_kOFMs0C_o#H_kOF09rdR4fQUjc(:jdg6RjU;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.4?5?5j*j:?V0!2:f:j2!?54V2:02
+R;A4.R,!jy55.?4j?5?0V:22:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R6
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRO"nU;j"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R.
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRVn4d.6._q_6qUjjURHbslFR0oCoD_kOFMs0C_o#Hr
+c9SosCF=k00oFoDOC_F0kMC#s_Hco_R4fm(:njdj(cn
+URSkOF0F=0oCoD_kOFMs0C_o#H_kOF09rcR4fmUj(c:jdg6RjU
+DSO D=O H_bM
+_OS08NN0N=FDooCF_OkCM0sH_#oR_cf4Q4(:njdjUcn
+URS08NN0L=FDooCF_OkCM0sH_#oR_6f4Q4(:njdjUcn
+URSDNOsM=knD_8$F_OkCM0s__jG#
+SO!Ds=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:gdU.RgU
+HSOMF=0oCoD_kOFMs0C_o#H_kOF09r.R4fQUjc(:jdg.RdU;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+c;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4.dn.B_nnUB_jRUjblsHRo0Fo_DCOMFk0_Cs#rHodS9
+sFCok00=FDooCF_OkCM0sH_#oR_df(m4ndj:(gd(USR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0FkrRd9fUm4c:(jd6gjj
+URS OD= OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_f.RQ(44ndj:UncjUSR
+8NN0LF=0oCoD_kOFMs0C_o#H_fdRQ(44ndj:UncjUSR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=o0Fo_DCOMFk0_Cs#_HoO0FkrR49fUQ4.:jjd.gjd;UR
+RobsFCok
+0;oObRF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#Oso;
+bHROMA;
+4,R44.y5??54jj*5?0V:2f:!j!2:5V4?:202RA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+d;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"UnOj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4.dn.q_66Uq_jRUjblsHRo0Fo_DCOMFk0_Cs#rHo.S9
+sFCok00=FDooCF_OkCM0sH_#oR_.f(m4ndj:(gd(USR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0FkrR.9fUm4c:(jd.gjd
+URS OD= OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_f.RQ(44ndj:Ugd(USR
+8NN0LF=0oCoD_kOFMs0C_o#H_fdRQ(44ndj:Ugd(USR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg
+URSMOH=.kM_o0Fo_DCOMFk0_CsM0CG_kOF09rjR4fQUj.j:gdUgRnU;b
+oRosCF;k0
+RobO0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}o;
+bNR80;NN
+Rob8NN0Lo;
+bOR#D
+s;oObRH
+M;A44R,54y.*?j5Vj?::02!2fjRA;
+.,R4j5y!.4?5??5jV2:0::020;2R
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4N;
+H#R3$NM_HD_OFRO {H
+NRNPo| OD_MbHRN{
+HHRs#4CR;;
+}
+
+};N3HRksMVNHO_MG8CR
+.;N3HR#sOD_RVV4N;
+HlR3FR8C.N;
+HCR3MDNLC;Rj
+RNH30DkbRol"U6Nj
+";N3HR#O$MEF_l84CR;H
+NRk3#lk_D0HO_M0bkR
+.;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;H
+NR#3N$_MOsCC#0MR":p7 q)Y_ a1 _GMC03\\k_Mn8_D$OMFk0_Csj"_G;R
+s@.@4::ggcg:g:06:FDooCF_OkCM0sH_#ocr.:Rj9f(cc.d.:Ugg.UpRqaq )_ quXVRV4g.6Un_nnUn_URUUblsHRo0Fo_DCOMFk0_Cs#rHo4S9
+sFCok00=FDooCF_OkCM0sH_#oR_4f(m4ndj:(.d6USR
+O0Fk=o0Fo_DCOMFk0_Cs#_HoO0FkrR49fUm4.:jjd.gjd
+URS OD= OD_MbH_SO
+8NN0NF=0oCoD_kOFMs0C_o#H_fjRQ(44ndj:Ugd(USR
+8NN0LF=0oCoD_kOFMs0C_o#H_f4RQ(44ndj:Ugd(USR
+NsOD=nkM_$8D_kOFMs0C_Gj_
+OS#D=s!0oFoD#C_Hjo__jj__Ro4fcQc(:..d.Ugg;UR
+RobsFCok
+0;oObRF;k0
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;b
+oR08NN
+N;o8bRNL0N;b
+oRD#OsA;
+4,R444y5?5j*j:?V0!2:fRj2;.
+ARj4,y4!5??5jV2:0:R02;H
+NR03sDs_FHNoMl"CR0oFoDOC_F0kMC#s_H;o"
+RNH#_$Mb#sCCCsPR
+4;N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;R4
+RNH3D#OsV_VR
+4;N3HRlCF8R
+.;N3HRCLMNDjCR;H
+NRk3D0lboRn"nU;U"
+RNH3M#$OlE_FR8C4N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.g:g:gc:g::60oFoDOC_F0kMC#s_H.orc9:jRcfc(:..d.UggqURp)a qu_q VXRV64.n6._6R66blsHRo0Fo_DCOMFk0_Cs#rHojS9
+sFCok00=FDooCF_OkCM0sH_#oR_jf(m4ndj:(.d6USR
+O=D O_D b_HMO8
+SNN0N=o0Fo_DCOMFk0_Cs#_HojQRf4n4(jg:d(U44RN
+SO=Dsk_Mn8_D$OMFk0_Csj
+_GSD#Os0!=FDooCH_#o__jj__jof4RQ(cc.d.:Ugg.U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oRD#OsA;
+4,R4jjy5?0V:2
+R;N3HRs_0DFosHMCNlRF"0oCoD_kOFMs0C_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HkR3MNVsOM_H8RCGjN;
+H#R3O_DsV4VR;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6666"N;
+H#R3$EMO_8lFC;R4
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';N3HROODF PR"oON|Db _H;M"
+RNH3$N#MsO_C0#CR:"M7q pY _)1_ aM0CG\k\3M8n_DO$_F0kMCjs__;G"
+@sR@:4.gcg:::gg6F:0oCoD_o#HRcfc(:..d4g(4qURp)a qu_q VXRVjcc.g_ggbgRsRHl0oFoD#C_HSo
+sFCok00=FDooCH_#omRf4j(n:(dU4R4U
+DSO D=O H_bM
+_OS08NN0N=FDooCH_#oQRf4n4(jg:d(U44R8
+SNL0N=o0Fo_DC#_Hoj__jj4_oRcfQc.(.:(dg4R4U
+OSNDks=M8n_DO$_F0kMCjs__
+G;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};o8bRNN0N;b
+oR08NN
+L;A44R,!4y5j4?*?5jV2:0:j!f2
+R;N3HRs_0DFosHMCNlRF"0oCoD_o#H"N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"gggg
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1) Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4n.:j::cn6j::fsRdd6cgg:d(U44Raqp _)qqXu RcVV6_gcUjjjRHbsl
+RsSosCF=k0sO
+SDO =Db _HOM_
+NS80=NN0oFoD#C_HfoRQ(44ndj:g4(4USR
+8NN0L_=PCLMND#C_HfoRQ(44ndj:g4(4USR
+8NN0O_=LM0CG_#j_JGlkN__(cQRfdjjU(g:d(U44R8
+SN80N=ML_C_G0jJ_#lNkG_6(_RdfQ6gcd:(dg4R4U
+OSNDks=M8n_DO$_F0kMCjs__
+G;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j!?5d55.?4j?5?0V:22:0::020;2R
+RNH3Ds0_HFsolMNCsR""N;
+H$R#Ms_bCs#CP4CR;H
+NR$3#MH_N_FODO{ R
+RNHP|oNO_D bRHM{H
+NR#sHC;R4
+
+};}N;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"jUjj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo'N;
+HOR3D FORo"PND|O H_bM
+";N3HRNM#$OC_s#RC0"7M: Ypq_1) Ma_C\G0\M3knD_8$F_OkCM0s__jG
+";s@R@4n.:j::cn6j::fLRdd6cgg:d(U44Raqp _)qqXu RcVV6_gccjjjRHbsl
+RLSosCF=k0LO
+SDO =Db _HOM_
+NS80=NN0oFoD#C_HfoRQ(44ndj:g4(4USR
+8NN0L_=PCLMND#C_HfoRQ(44ndj:g4(4USR
+8NN0O_=LM0CG_#j_JGlkN__(cQRfdjjU(g:d(U44R8
+SN80N=ML_C_G0jJ_#lNkG_6(_RdfQ6gcd:(dg4R4U
+OSNDks=M8n_DO$_F0kMCjs__
+G;oObRD
+ ;N3bR#_$MNOH_D FORN{
+boRPND|O H_bM
+R{NsbRHR#C4};
+;;
+}
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j55d?.4?5??5jV2:0::V2VV2:2
+R;N3HRs_0DFosHMCNlR""L;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRcjjj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+R4@@.j:n:nc:j::6ojRf:qjRp)a qu_q VXRVUcc.w_wjbjRsRHlos
+SCkoF0
+=oS OD= OD_MbH_SO
+8NN08h=t7N
+SO=Dsk_Mn8_D$OMFk0_Csj;_G
+RobO;D
+RNb3M#$__NHOODF
+R{NPbRoON|Db _H{MR
+RNbsCH#R
+4;}};
+;4
+ARj4,yd!5?0V:2
+R;N3HRs_0DFosHMCNlR""o;H
+NRM#$_Cbs#PCsC;R4
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVjVj"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"N;
+HNR3#O$M_#sCC"0RM :7p_qY) 1aC_MG\0\3nkM_$8D_kOFMs0C_Gj_"s;
+Rgfd6:4jdjUcUqnRp)a qu_q NXR._c4jd(jRHbslFR0oCoD_o#H_jj__oj_4O
+SFFlLk00=FDooCH_#o__jj__jof4Rm6dg4dj:UUcjnSR
+8NN0NF=0oCoD_kOFMs0C_o#H_R4gf4Q4(:njdc(gg
+nRS08NN0L=FDooCF_OkCM0sH_#oj_.R4fQ4j(n:jdU(Rnn
+NS80=NO0oFoD#C_Hjo__jj___o4.QRf.4j4.U:d4ng6R8
+SN80N=4kM_o0Fo_DCOMFk0_Cs#DHo0UF4RdfQUjnc:ddU.R4n;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5d5V.?:?545Vj?::020:225V.?:?54V2:02;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"("jd;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4.4:44(4:44U:d+Ac:piQh M)_C\G034kM_o0Fo_DCOMFk0_Cs#RHofUdc(dU:(6gccpRqaq )_ quX.RNc(4_wR((blsHRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#oFD04SU
+OLFlF=k0k_M40oFoDOC_F0kMC#s_H0oDFR4UfcmdU:(Udc(g6
+cRS08NN0N=FDooCF_OkCM0sH_#o(_4R4fQ4j(n:cd(URnc
+NS80=NL0oFoDOC_F0kMC#s_H4o_UQRf4n4(j(:dnc4dR8
+SNO0N=o0Fo_DCOMFk0_Cs#_Ho4fnRQ(44ndj:(.(dcSR
+8NN08M=k4F_0oCoD_kOFMs0C_o#HD40F6QRfdjcjU(:dUc6URo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R44dy5??5.j4*5??5jV2:0::020f2:j;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bl(R"V"((;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4.(46:jn:(:+njc_:LM0CG_#j_JGlkNdRf4n6j:ddg4RU6q pa)qq_uR XN4.c_j(wjsRbHLlR_GMC0__j#kJlG(N__S6
+OLFlF=k0LC_MGj0__l#Jk_GN(R_6f4md6:jnd4gdU
+6RS08NNON=FlDkMF_OkCM0sH_#oR_nf4Q4(:njd6UUg
+6RS08NNOL=FlDkMF_OkCM0sH_#oR_(f4Q4(:njdUUgn
+6RS08NNkO=MP6__NCMLDDC0RF6fcQ.(:ccdjg46
+6RS08NNL8=_GMC0__j#kJlG(N__fdRQndjddn:g4.d6
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,5jyd.?5??545Vj?::02002:22:VRN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"j(Vj
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@.6:(::4j(nn:j:+cLC_MGj0__l#JkRGNfU.n(dc:gUd46pRqaq )_ quX.RNc 4_wR.dblsHRML_C_G0jJ_#lNkG_c(_
+FSOlkLF0_=LM0CG_#j_JGlkN__(cmRf.(nUcg:dd64UR8
+SNN0N=MDHCF_OkCM0sH_#oR_Uf4Q4(:njd6UUg
+6RS08NNDL=H_MCOMFk0_Cs#_Ho(QRf4n4(jU:dg6UnR8
+SNO0N=4kMd__PCLMND0CDFfnRQ(.ccdc:g64j6SR
+8NN08_=LM0CG_#j_JGlkN__(cR_NfcQ.(:ccddg.4;6R
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,4!?5d55.?4:?Vjj*5?0V:2V2:25:!.4?5?!V:f:j25V4?:2022
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"C.;d"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4(.:6j:4::(nncj+:ML_C_G0jJ_#lNkGRjf.g:U.d6UU6qdRp)a qu_q NXR._c4jww4RHbsl_RLM0CG_#j_JGlkN__(c
+_NSlOFL0Fk=ML_C_G0jJ_#lNkG_c(__fNRmg.jUd.:U6U6dSR
+8NN0NH=DMOC_F0kMC#s_Hco_R4fQ4j(n:ddUgRnd
+NS80=NLDCHM_kOFMs0C_o#H_f6RQ(44ndj:Ud6.dSR
+8NN0OH=DMOC_F0kMC#s_Hno_R4fQ4j(n:ndUcR.d
+NS80=N8k(M4_CP_MDNLCFD0dQRf.4j4.U:d(dnURo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4jdy5??5.V2:0:?5.5V4?:?5jV2:022:02
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"j4;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4(.:6j:4::(nncj+:ML_C_G0jJ_#lNkGRnf.U:(cd6UU6qdRp)a qu_q NXR._c4 jjwRHbsl_RLM0CG_#j_JGlkN__(dO
+SFFlLkL0=_GMC0__j#kJlG(N__fdRmU.n(dc:U6U6dSR
+8NN0NF=ODMkl_kOFMs0C_o#H_f(RQ(44ndj:UndgdSR
+8NN0LF=ODMkl_kOFMs0C_o#H_fgRQ(44ndj:Ud6.dSR
+8NN0O_=LM0CG_#j_JGlkN__(.QRf.4j4.U:dndc.R8
+SN80N=gkM_CP_MDNLCFD0nQRf.jnjcU:d(dnURo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4j5y!d.?5??54Vj:5?0V:202:2.:5?0V:2;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blCR"j"Vj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4.4:44(4:44U:d+Ac:piQh M)_C\G034kM_o0Fo_DCOMFk0_Cs#RHof.djcdn:(.cU.pRqaq )_ quX.RNcw4_wR(wblsHRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#oFD04S6
+OLFlF=k0k_M40oFoDOC_F0kMC#s_H0oDFR46fjmd.:cndU(c.
+.RS08NN0N=FDooCF_OkCM0sH_#od_4R4fQ4j(n:jd(.Rd.
+NS80=NL0oFoDOC_F0kMC#s_H4o_cQRf4n4(j(:d4.6jR8
+SNO0N=o0Fo_DCOMFk0_Cs#_Ho4f6RQ(44ndj:(g.n.SR
+8NN08M=k4F_0oCoD_kOFMs0C_o#HD40F.QRf.(gdn(:dd.g6Ro;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0Lo;
+bNR80;NO
+Rob8NN08A;
+4,R4j5y!d:?V!?5.554?j:?V002:22:02
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboRV"V(;V"
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@4(.:6U:d::(6ncj+:q7)WT_1z q)_GMC0k\3MP6__NCMLRDCfg.jUd.:Ug(.dpRqaq )_ quX.RNcw4_ R blsHRq7)WT_1z q)_GMC0k\3MP6__NCMLDDC0
+F6SlOFL0Fk=6kM_CP_MDNLCFD06mRf.Ujg.U:d(d.gR8
+SNN0N=DOFk_lMOMFk0_Cs#_HocQRf4n4(jU:d.d(jR8
+SNL0N=DOFk_lMOMFk0_Cs#_Ho6QRf4n4(jU:dddg(R8
+SNO0N=DOFk_lMOMFk0_Cs#_HodQRf4n4(jU:d6d4nR8
+SN80N=6kM_CP_MDNLC.D0R.fQj.44:ndUcR.d;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+AR44,yd!5??5.V*:j5V4?:?5jV2:02f2:j;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"C"CC;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4.4:44(4:44U:d+Ac:piQh M)_C\G034kM_o0Fo_DCOMFk0_Cs#RHofn.64dc:(gj4jpRqaq )_ quX.RNcj4_4RjjblsHRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#oFD04S.
+OLFlF=k0k_M40oFoDOC_F0kMC#s_H0oDFR4.f6m.n:4cd4(jg
+jRS08NN0N=FDooCF_OkCM0sH_#oj_4R4fQ4j(n:6dnnRjj
+NS80=NL0oFoDOC_F0kMC#s_H4o_4QRf4n4(jn:dnjU(R8
+SNO0N=o0Fo_DCOMFk0_Cs#_Ho4f.RQ(44ndj:nnUjjSR
+8NN08M=k4F_0oCoD_kOFMs0C_o#HDg0FR.fQcc(c:gdndR.j;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,y?5d5V.?:?54Vj:5?0V:2:22V;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"4"jj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4.(4n:jn:(:+d.c):7q1W_T)zq C_MG30\kdM4_CP_MDNLC.Rfj.gU:(dU.Rgdq pa)qq_uR XN4.c_((w(sRbH7lR)_qW1qTz)M _C\G034kMd__PCLMND0CDFSn
+OLFlF=k0kdM4_CP_MDNLCFD0nmRf.Ujg.U:d(d.gR8
+SNN0N=MDHCF_OkCM0sH_#oR_6f4Q4(:njd(U.j
+dRS08NNDL=H_MCOMFk0_Cs#_HonQRf4n4(jU:dddg(R8
+SNO0N=MDHCF_OkCM0sH_#oR_df4Q4(:njd4U6n
+dRS08NNk8=M_4dPM_CNCLDDc0F_fjRQ4.j4d.:U.ncd
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,54yd.?5?5j*4j?5?0V:22:0::02fRj2;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR((V("N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@.@4::(64(j:6.:d+7c:)_qW1qTz)M _C\G03gkM_CP_MDNLC.Rf...c:ddUgR.4q pa)qq_uR XNd44_ww((sRbH7lR)_qW1qTz)M _C\G03gkM_CP_MDNLCFD0nO
+SFFlLkk0=MPg__NCMLDDC0RFnf.m..:c.dgUd.
+4RS08NNON=FlDkMF_OkCM0sH_#oR_6f4Q4(:njdd(gd
+4RS08NNOL=FlDkMF_OkCM0sH_#oR_nf4Q4(:njdnUjj
+4RS08NNkO=MPg__NCMLDDC0RFcfjQ.4:4.d(U4g;4R
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0OA;
+4,R4j5y!.:?V!?545Vj?::020R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRV((V"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@.@4:444:4(:4d4:U:+cAhpQi_ )M0CG\M3k4F_0oCoD_kOFMs0C_o#HRjf.g:U.d6n66qURp)a qu_q NXR._c4((w(RHbslpRAQ hi)C_MG30\k_M40oFoDOC_F0kMC#s_H0oDFSg
+OLFlF=k0k_M40oFoDOC_F0kMC#s_H0oDFfgRmg.jUd.:n666USR
+8NN0NF=0oCoD_kOFMs0C_o#H_fURQ(44ndj:nnjgUSR
+8NN0LF=0oCoD_kOFMs0C_o#H_fgRQ(44ndj:nd..USR
+8NN0OF=0oCoD_kOFMs0C_o#H_f(RQ(44ndj:n.dcUSR
+8NN08M=k4F_0oCoD_kOFMs0C_o#HDR0nfjQ.4:4.dnncU;UR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,455d?.*?j554?j:?V002:22:0:2fjRN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"((V(
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@.n:(::dU(nn:j:+c7W)q_z1Tq_) M0CG\M3k4P(__NCMLRDCfd4n6dj:U.dg4pRqaq )_ quX.RNcw4_ RjjblsHRq7)WT_1z q)_GMC0k\3M_4(PM_CNCLDDd0F
+FSOlkLF0M=k4P(__NCMLDDC0RFdfnm4d:6jdgUd.
+4RS08NNDN=H_MCOMFk0_Cs#_Ho4QRf4n4(j(:dg4ddR8
+SNL0N=MDHCF_OkCM0sH_#oR_.f4Q4(:njdnUjj
+4RS08NNDO=H_MCOMFk0_Cs#_HojQRf4n4(jU:d44(gR8
+SN80N=MDHCF_OkCM0sH_#oR_df4Q4(:njdjUd6;4R
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+Rob8NN0Oo;
+bNR80;N8
+RA44y,j!?5d5V.?:?54Vj:5?0V:2:220;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blVR"C"jj;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+fsR46ndj(:dUc4gRaqp _)qqXu RcN.4w_wwb RsRHl0oFoD#C_Hjo__jj___o4.O
+SFFlLk00=FDooCH_#o__jj__jo.4_R4fmnjd6:Ud(4Rgc
+NS80=NN0oFoDOC_F0kMC#s_H.o_dQRf4n4(j(:ddcnjR8
+SNL0N=o0Fo_DCOMFk0_Cs#_Ho.fcRQ(44ndj:((cUcSR
+8NN0OF=0oCoD_kOFMs0C_o#H_R.4f4Q4(:njdj(nn
+cRS08NN08=FDooCF_OkCM0sH_#o._.R4fQ4j(n:(d(dR.c;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;o8bRN80N;4
+ARj4,yd!5?5V:.:?V5V4?:?5jV2:02R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVCVV"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@.@4::(64(j:nj:n+Lc:_GMC0__j#kJlGfNR46ndjU:d.4nnRaqp _)qqXu RcN.4j_jjbcRsRHlLC_MGj0__l#Jk_GN(
+_.SlOFL0Fk=ML_C_G0jJ_#lNkG_.(_R4fmnjd6:.dUnRn4
+NS80=NNOkFDlOM_F0kMC#s_HUo_R4fQ4j(n:Ud(jR(4
+NS80=NLEM_CNCLD_o#HR4fQ4j(n:gd(dRc4
+NS80=NOOkFDlOM_F0kMC#s_Hgo_R4fQ4j(n:jdU6Rd4
+NS80=N8DCHM_kOFMs0C_o#H_fURQ(44ndj:Ug4(4
+R;oObRFFlLk
+0;o8bRNN0N;b
+oR08NN
+L;o8bRNO0N;b
+oR08NN
+8;A44R,5jyd:?V5V.?:?545Vj?::02V222RN;
+HlR3FR8C4N;
+HCR3MDNLC;Rj
+RNH30DkbRol"jjjc
+";N3HR#_klDOk0_bHMk40R;H
+NRosCHRFM'NPo's;
+R4@@.6:(::4j(d6:.:+c7W)q_z1Tq_) M0CG\M3kg__PCLMNDfCR46ndj(:dUgj.Raqp _)qqXu R4N4d4_jjb4RsRHl7W)q_z1Tq_) M0CG\M3kg__PCLMND0CDFSc
+OLFlF=k0k_MgPM_CNCLDDc0FR4fmnjd6:Ud(jR.g
+NS80=NNOkFDlOM_F0kMC#s_Hdo_R4fQ4j(n:dd(cRdg
+NS80=NLOkFDlOM_F0kMC#s_Hco_R4fQ4j(n:cd((Rjg
+NS80=NOOkFDlOM_F0kMC#s_H.o_R4fQ4j(n:6d(URgg;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;A44R,5jy.:?V5V4?:?5jV2:02;2R
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0bljR"4"j4;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+@sR@:4.(d6:U6:(:+njc):7q1W_T)zq C_MG30\k_M6PM_CNCLDRnf4d:6jdnU.nq4Rp)a qu_q NXR4_4dw wRHbsl)R7q1W_T)zq C_MG30\k_M6PM_CNCLDD
+0.SlOFL0Fk=6kM_CP_MDNLC.D0R4fmnjd6:.dUnRn4
+NS80=NNOkFDlOM_F0kMC#s_H4o_R4fQ4j(n:Ud(jR(4
+NS80=NLOkFDlOM_F0kMC#s_H.o_R4fQ4j(n:gd(dRc4
+NS80=NOOkFDlOM_F0kMC#s_Hjo_R4fQ4j(n:jdU6Rd4;b
+oRlOFL0Fk;b
+oR08NN
+N;o8bRNL0N;b
+oR08NN
+O;A44R,!jy5V.?:?54Vj:5?0V:2R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRVCCV"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@.@4::(n4(j:n.:d+7c:)_qW1qTz)M _C\G034kMd__PCLMNDfCR46ndjU:d.4nnRaqp _)qqXu RgNc_4444sRbH7lR)_qW1qTz)M _C\G034kMd__PCLMND0CDFjc_
+FSOlkLF0M=k4Pd__NCMLDDC0_FcjmRf46ndjU:d.4nnR8
+SNN0N=MDHCF_OkCM0sH_#oR_cf4Q4(:njdj(U(
+4RS08NNDL=H_MCOMFk0_Cs#_Ho.QRf4n4(j(:dg4dcRo;
+bFROlkLF0o;
+bNR80;NN
+Rob8NN0LA;
+4,R4j4y5?5V:j:?V0R22;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR4444"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+s@.@4:444:4(:4d4:U:+cAhpQi_ )M0CG\M3k4F_0oCoD_kOFMs0C_o#HRnf4d:6jdgnj.qnRp)a qu_q NXRc(g_(R((blsHRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#onD0
+FSOlkLF0M=k4F_0oCoD_kOFMs0C_o#HDR0nfnm4d:6jdgnj.
+nRS08NN0N=FDooCF_OkCM0sH_#oR_nf4Q4(:njdd6nd
+nRS08NN0L=FDooCF_OkCM0sH_#oR_6f4Q4(:njdn6(j;nR
+RobOLFlF;k0
+Rob8NN0No;
+bNR80;NL
+RA44y,j554?j:?V002:2
+R;N3HRlCF8R
+4;N3HRCLMNDjCR;H
+NRk3D0lboR("((;("
+RNH3l#k_0DkOM_HbRk04N;
+HCRsoMHFRo'PN
+';s@R@44.:4.6:g4:46.:6+kc:M0._FDooCF_OkCM0sC_MG.0rj9:jRUf4.:jjdgUgnqURp)a qu_q NXR66._6_66UUUURHbslMRk.F_0oCoD_kOFMs0C_GMC09rj
+FSOkk0=M0._FDooCF_OkCM0sC_MGO0_Frk0jf9Rm.4Ujdj:UnggUSR
+8NN0NF=0oCoD_kOFMs0C_o#H_fjRQ(44ndj:U.d6USR
+8NN0LF=0oCoD_kOFMs0C_o#H_f4RQ(44ndj:U.d6U
+R;oObRF;k0
+Rob8NN0No;
+bNR80;NL
+RA44y,j5Vj?:R02;.
+ARj4,y4!5??5jV2:0:R02;H
+NRF3l8.CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lR6U6U"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;R
+b@:@44::44+:..N:VDR#Cfjj:RDVN#VCRNCD#R7th;H
+NRosCHRFM'NPo'b;
+R:fjjsR0keCRBeBRB
+B;@
+
+
+ftell;
+@E@MR@dn:U::(dgU:RFRIsP RoLNRCPEN;P
+NR#3H_k#FsROC4N;
+PDR3HMMCFgRcnN;
+PHR3#8PED;R4
+RNP3_H#PDE8R
+4;N3PR#_$MVblNRF"Is\ R"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNN_b E3P8\\"MsIF "R\/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_0CM38PE\M"\I FsR/\"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oNN3sOP\E8"I\MFRs \E"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sLO/F8Ns_H8sP_CsC3M0P\E8"I\MFRs \E"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sLO/F8Ns_H8sP_CsN3sOP\E8"I\MFRs \E"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/oON_FsM0FCD_MP03E"8\\FMIs\ R"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNF_OMF0sDs_NOE3P8\\"MsIF "R\/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsC3M0P\E8"I\MFRs \E"/F#lC/sLkL/NM8CH8D8k/H_8C4Ln/#/b.7HC#oDMVF#I/sPO/o8N_sCHPss_NOE3P8\\"M
+";N#PR$bM_sCC#sRPC4N;
+P$R#MN_bs00HHRFM"oVbNu= 461.w(Bn."-n;P
+NRD3VF#I_0CN0RN{
+PVR3D_FIbbsF#b_NbCDH8;R4
+RNP3FVDIF_DF_b#L sFCjMR;P
+NRD3VFkI_MkHJHCVH8;R4
+RNP3FVDI0_#Fsb_CHk#Mlo_FC8oM;R4
+RNP3FVDIC_8ObFlR
+4;N3PRVIDF_blNbRC84N;
+PVR3D_FIEsHCNEsO$C_s#s0FC48R;P
+NRD3VFNI_Vs0C_oDFH#O_$EM0C##HR
+4;}N;
+PlR3NFb_bF0HM"#RyamuQ1mh:|\"-Fbs8b0$C$|#MHbDVb$_s-F|CsMO$|b0-Fbs|N-bs 0|u.416nwB(n.-|N-lGMVN|j6j|H-bb-C|VoHGN80COODF d#||H-VGMoCC0sNCD8OF#O |-d|#_$MNCD0slN_FD8C||FM-b0F_PDCClD_FD8kCo|PNl|-N-b|PcJl4V|-s|CJ.463(-6|#|NbfQQ7)o/PNN3#b8|-COPHCLDH|b/F0$/#MHbDVV$/b_oNOj.jg/jnD/HLNCD0sNN/Ds0CN|3P-P8CHDOCH/L|F/b0#b$MD$HV/oVbN._OjjjgnH/DLD/N0NCs/NJks#0k_gQQj0/#sHN0G|3P-P8CHDOCH/L|F/b0#b$MD$HV/oVbN._OjjjgnH/DLD/N0NCs/NJks#0k_gQQjD/N0NCs_3lVP8|-COPHCLDH|b/F0$/#MHbDVV$/b_oNOj.jg/jnD/HLNCD0sJN/k0NskQ#_Q/gjNCD0sDN_bPl3|C-8PCHOD|HL/0Fb/M#$bVDH$b/VoON_.gjjjDn/HNL/Ds0CNk/JNks0#Q_QgNj/Ds0CNs_bH0lHH#PC3-P|#|NbfQQ7)o/PNN3#b\\"MzyB)":\/0Fb/M#$bVDH$b/VoON_.gjjjDn/HGMk/Nl_Ds0CN:\"4d.cjjdn(Mg\"N;
+POR3FHlbDbC_F0HM_lMNCPR'o;N'
+RNP3VsCFHD8MPo_H_CIH48R;P
+NR83OLN_#P{CR
+RNP4jjjRo"PNC|8VCHM_FODO- RHCM0sDMNRn{RR{}RROb:Db _H}MRRN-Ml{CRRNPo| OD_MbHR-}Rs_CVsCH#Rj{R3jjjjRjj}sR-CVV_NRDD{gR43jUngR6j}kR-MsOC0MNH0{$RRjj3jjjjjRR}-sbCHRF8{gRd34(.gRjj}OR-D FOoksFbRR{QCMVs8sC_ ODoksFbR_j}sR-HR#C{3Rjjjjjj}jRRN-VD{DRR34gUgnj6}jR"N;
+P$R#MC_sVCCsM_OCOODF
+R{NPPRoON|Db _H{MR
+RNP3M#$_VsCOODF $_0bnCR;;
+}
+
+};}N;
+PMR3NNsC8FCOl4bR;P
+NRC38ObFl_HbslN#_sRCN4N;
+PNR3DOlN_0bNEF_OkRM04N;
+PbR3N_0EORM04N;
+PFR3Lb#F0M8FC;R4
+RNP3l0HCN#0l4bR.46ndgU(4N;
+POR3bE_OC#O k6lRgg(dn6(.;P
+NRM33DD_NDHkMJRkC4N;
+P3R370FMuMsH0Fusb0Cs$#vC#CNo#;Rj
+RNP3N30_0MC_D8CNF$_M;Rj
+RNP3N3aQFoMssCaC$CabCCh0D7CNj$R;P
+NRa33N#q#kplCF1N8EDHC8oHMR
+j;N3PR3_MDsDCbN0OCCbOEI4sR;P
+NRa33NDBNOsuF0H7sPRC#jN;
+P3R3aNNBDFOusC07DRN$jN;
+P3R3a#NzCbQlsCFPR
+j;N3PR3zaN#FC)kR0CjN;
+P3R3VOFsCk_N0FFOMs#0R
+j;N3PR3_MDI0sHCk_N0FFOMs#0_O#8R
+4;N3PR3sVFI8Ns_MNMF00NCk_N0FFOMs#0R
+4;N3PR3_MDNFk0O#FM0jsR;P
+NRV33FCsO_0NkFMOF#_0ssNCDGF_HR
+j;N3PR3_b#8HC#o#M_0CN0R
+j;N3PRk0H_HMlHoO_#NRDC4jjjjN;
+PER3NH#0loHMR
+4;N3PRkMH_DD_#NRO d6cc(
+n;H@R@n4:c:c(:4d:4: OD_MbHR OD_MbH;H
+NR03sDs_FHNoMl"CRO_D b"HM;H
+NR83OL
+R{N4HRjRjj{H
+NR[FLCRO0{H
+NR4jR;;
+}
+
+};}N;
+HOR38OL_b
+R{NjHRRd"6d_jn4_U(njcgjc_n6_4..c(dgg_6d_4n4..ncU_..4n_j(U._64.n4c_4ncc_((4c._ng"4.;;
+}
+RNH3#EN_NMLON _040R;H
+NRF3bsD0N8RHs""HM;b
+oR OD_MbH;b
+NR83OL
+R{N4bRjRjj{b
+NR[FLCRO0{b
+NR4jR;;
+}
+
+};}N;
+bHR3#N_o0_C8OODF ;R4
+RNb3_H#OODF ;R4
+RNb3FODO" RP|oNO_D b"HM;R
+H@:@nc(.:::c.4s6:C0#C_MbHR#sCCb0_H
+M;N3HRs_0DFosHMCNlRC"s#_C0b"HM;H
+NRF3bsD0N8RHs""HM;R
+F@:@nc(c:::cc4s.:jH_bMjRs_MbH;H
+NR03sDs_FHNoMl"CRsbj_H;M"
+RNH3sbF08NDH"sRF"k0;R
+F@:@nc4c:6c:c::.jsb4_HsMR4H_bMN;
+HsR30FD_sMHoNRlC"_s4b"HM;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::cc.cd:cU:.:_s.bRHMsb._H
+M;N3HRs_0DFosHMCNlR."s_MbH"N;
+HbR3FNs0Ds8HRk"F0
+";F@R@n6:c:c(:6.:4:_ojbRHMobj_H
+M;N3HRs_0DFosHMCNlRj"o_MbH"N;
+HbR3FNs0Ds8HRk"F0
+";F@R@n6:c::46c.6:j4:o_MbHR_o4b;HM
+RNH3Ds0_HFsolMNCoR"4H_bM
+";N3HRb0FsNHD8sFR"k;0"
+@FR@cn:6d:.::c6.oU:.H_bM.Ro_MbH;H
+NR03sDs_FHNoMl"CRob._H;M"
+RNH3sbF08NDH"sRF"k0;R
+F@:@nc(n:::cn4L.:jH_bMjRL_MbH;H
+NR03sDs_FHNoMl"CRLbj_H;M"
+RNH3sbF08NDH"sRF"k0;R
+F@:@nc4n:6n:c::.jLb4_HLMR4H_bMN;
+HsR30FD_sMHoNRlC"_L4b"HM;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::c(((:c::46EM#$OH_bM#RE$_MOb;HM
+RNH3Ds0_HFsolMNCER"#O$M_MbH"N;
+HbR3FNs0Ds8HRk"F0
+";F@R@nU:c:c(:U6:4:$P#MbO_HPMR#O$M_MbH;H
+NR03sDs_FHNoMl"CRPM#$OH_bM
+";N3HRb0FsNHD8sFR"k;0"
+@FR@6n:j::(64j:gC:#P_CM#_CobrHM4jd:9CR#P_CM#_CobrHM4jd:9CR#P_CM#_CobrHM4jd:9N;
+HsR30FD_sMHoNRlC"P#CC#M_Cbo_H;M"
+RNH3sbF08NDH"sRF"k0;R
+F@:@n6(.:::6.48d:_$E#M8OR_$E#M
+O;N3HRs_0DFosHMCNlR_"8EM#$O
+";N3HRb0FsNHD8sFR"k;0"
+@FR@6n:.n:4::6..8.:_$P#M8OR_$P#M
+O;N3HRs_0DFosHMCNlR_"8PM#$O
+";N3HRb0FsNHD8sFR"k;0"
+@FR@6n:d::(6.d:._:8OkFDlOM_F0kMCgsr:Rj98F_ODMkl_kOFMs0Crjg:9_R8OkFDlOM_F0kMCgsr:;j9
+RNH3Ds0_HFsolMNC8R"_DOFk_lMOMFk0"Cs;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::6c(c:6::.j8H_DMOC_F0kMCUsr:Rj98H_DMOC_F0kMCUsr:Rj98H_DMOC_F0kMCUsr:;j9
+RNH3Ds0_HFsolMNC8R"_MDHCF_OkCM0s
+";N3HRb0FsNHD8sFR"k;0"
+@FR@6n:6::(6.6:n_:8#_C0OkFDlOM_F0kMC8sR_0#C_DOFk_lMOMFk0;Cs
+RNH3Ds0_HFsolMNC8R"_0#C_DOFk_lMOMFk0"Cs;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::66.6g:6n:c:#8_CD0_H_MCOMFk0RCs8C_#0H_DMOC_F0kMC
+s;N3HRs_0DFosHMCNlR_"8#_C0DCHM_kOFMs0C"N;
+HbR3FNs0Ds8HRk"F0
+";F@R@nn:6:6(:n4:.:E8_#O$M_kOFMs0Crjg:9_R8EM#$OF_OkCM0s:rgj89R_$E#MOO_F0kMCgsr:;j9
+RNH3Ds0_HFsolMNC8R"_$E#MOO_F0kMC;s"
+RNH3sbF08NDH"sRF"k0;R
+F@:@n6((:::6(.84:_$P#MOO_F0kMCgsr:Rj98#_P$_MOOMFk0rCsg9:jRP8_#O$M_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"P8_#O$M_kOFMs0C"N;
+HbR3FNs0Ds8HRk"F0
+";F@R@nU:6:6(:U6:.:#8_CE0_#O$M_kOFMs0CR#8_CE0_#O$M_kOFMs0C;H
+NR03sDs_FHNoMl"CR8C_#0#_E$_MOOMFk0"Cs;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::6U.6U:Un:c:#8_CP0_#O$M_kOFMs0CR#8_CP0_#O$M_kOFMs0C;H
+NR03sDs_FHNoMl"CR8C_#0#_P$_MOOMFk0"Cs;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::6g(g:6::4n8__ECLMND8CR_CE_MDNLCN;
+HsR30FD_sMHoNRlC"E8__NCML"DC;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::nj(j:n::4n8__PCLMND8CR_CP_MDNLCN;
+HsR30FD_sMHoNRlC"P8__NCML"DC;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::n4(4:n:8g:_8sR_
+s;N3HRs_0DFosHMCNlR_"8s
+";N3HRb0FsNHD8sFR"k;0"
+@FR@nn:4.:4::n448c:_8oR_
+o;N3HRs_0DFosHMCNlR_"8o
+";N3HRb0FsNHD8sFR"k;0"
+@FR@nn:4(:4::n448g:_8LR_
+L;N3HRs_0DFosHMCNlR_"8L
+";N3HRb0FsNHD8sFR"k;0"
+@FR@nn:.::(n4.:g_:8EM#$O0_#Nr0Cj9:nRE8_#O$M_N#00jCr:Rn98#_E$_MO#00NC:rjn
+9;N3HRs_0DFosHMCNlR_"8EM#$O0_#N"0C;H
+NRF3bsD0N8RHs"0Fk"F;
+Rn@@::nd(d:n::4g8#_P$_MO#00NC:rjn89R_$P#M#O_0CN0rnj:9_R8PM#$O0_#Nr0Cj9:n;H
+NR03sDs_FHNoMl"CR8#_P$_MO#00NC
+";N3HRb0FsNHD8sFR"k;0"
+@FR@nn:c::(n4c:(_:8#00NCD_O _R8#00NCD_O N;
+HsR30FD_sMHoNRlC"#8_0CN0_ OD"N;
+HbR3FNs0Ds8HRk"F0
+";F@R@n6:n:n(:6c:4:08_FDooC_R80oFoD
+C;N3HRs_0DFosHMCNlR_"80oFoD;C"
+RNH3sbF08NDH"sRF"k0;R
+F@:@nn(n:::nn.8.:_o0Fo_DCOMFk0rCs.jc:9_R80oFoDOC_F0kMC.src9:jR08_FDooCF_OkCM0scr.:;j9
+RNH3Ds0_HFsolMNC8R"_o0Fo_DCOMFk0"Cs;H
+NRF3bsD0N8RHs"0Fk"o;
+LDRO H_bMN;
+LOR38{LR
+RNL4jjjRN{
+LLRF[0CORN{
+LRRj4};
+;;
+}
+
+};N#LR$OM_D FO_VHMCCss8;R4
+RNL3FODO" RP|oNO_D b"HM;L
+NRD3OF_O CC8oRH"s#;C"
+RoMtd_d;M
+NRosCHRFM'NPo'N;
+MHR3#D_OFRO 4N;
+MHR3#N_o0_C8OODF ;R4
+RoMO_D b_HMON;
+MOR3D FORo"PND|O H_bM
+";N3MROODF 8_Co"CRsCH#"N;
+MHR3#D_OFRO 4N;
+MHR3#N_o0_C8OODF ;R4
+RoMO_D b;HM
+RNM3_H#OODF ;R4
+RNM3_H#oCN08D_OFRO 4b;
+R4@@:44::.4:+0.:sRkCfjj:Rk0sCsR0keCRB
+B;NsHRCFoHMPR'o;N'
+@bR@44::44::..+:DVN#fCRjR:jV#NDCNRVDR#Ct;h7
+RNHsHCoF'MRP'oN;R
+s@j@4:d44:4c:46d::$8D_kOFMs0Crj4:94Rf(:njdnc(jq4Rp)a qu_q VXRVjd(_qqUUsRbH8lRDO$_F0kMC4sr9s
+SCkoF0D=8$F_OkCM0s9r4R4fm(:njdnc(j
+4RS OD= OD_MbH_SO
+8NN0NC=s#_C0b_HMO8
+SNL0N=$8D_kOFMs0CrRj9f4Q4(:njd4g(4
+URS08NN8O=DO$_F0kMC4sr9QRf4n4(jg:d(U44Ro;
+bCRso0Fk;b
+oR OD;b
+NR$3#MH_N_FODO{ R
+RNbP|oNO_D bRHM{b
+NR#sHC;R4
+
+};}N;
+bHR3#N_o0_C8OODF ;R4
+RNb3_H#OODF ;R4
+Rob8NN0Lo;
+bNR80;NO
+RA44y,4!?5.jj*5?0V:24:5?:fj0R22;H
+NRM#$_Cbs#PCsC;R4
+RNH3Ds0_HFsolMNC8R"DO$_F0kMC;s"
+RNH3M#$__NHOODF
+R{NPHRoON|Db _H{MR
+RNHsCH#R
+4;}};
+;H
+NRM3kVOsN_8HMC4GR;H
+NRD3N#O0_ERHMd
+g;N3HRN0D#_C0DM;R4
+RNH3#ND0C_s[0COC48R;H
+NRF3l84CR;H
+NRM3CNCLDR
+j;N3HRDbk0o"lRNUUN"N;
+H#R3kDl_k_0OHkMb0;R4
+RNHsHCoF'MRP'oN;H
+NRD3OFRO "NPo| OD_MbH"s;
+R4@@j4:4d::c4:4d6D:8$F_OkCM0s:r4jf9R4j(n:ndccR44q pa)qq_uR XV(Vdj._qqb.RsRHl8_D$OMFk0rCsjS9
+sFCok80=DO$_F0kMCjsr9mRf4j(n:ndccR44
+DSO D=O H_bM
+_OS08NNsN=C0#C_MbH_SO
+8NN0LD=8$F_OkCM0s9rjR4fQ4j(n:(dg4R4U
+NS80=NO8_D$OMFk0rCs4f9RQ(44ndj:g4(4U
+R;osbRCkoF0o;
+bDRO N;
+b#R3$NM_HD_OFRO {b
+NRNPo| OD_MbHRN{
+bHRs#4CR;;
+}
+
+};N3bRHo#_N80C_FODO4 R;b
+NR#3H_FODO4 R;b
+oR08NN
+L;o8bRNO0N;4
+AR44,y.!5?5j*j:?V0!2:5V4?:j!f2;2R
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRD"8$F_OkCM0s
+";N3HR#_$MNOH_D FORN{
+HoRPND|O H_bM
+R{NsHRHR#C4};
+;;
+}
+RNH3VkMs_NOHCM8G;Rj
+RNH3#ND0E_OHdMRUN;
+HNR3D_#00MDCR
+4;N3HRN0D#_[sCCCO08;R4
+RNH38lFC;R4
+RNH3NCMLRDCjN;
+HDR3ko0blNR"."N.;H
+NRk3#lk_D0HO_M0bkR
+4;NsHRCFoHMPR'o;N'
+RNH3FODO" RP|oNO_D b"HM;R
+s@:@nc(.:::c.4s6:C0#C_MbHR:fjj Rv))BzYQ_pA0R#sHN0GF_H_amujsRbHslRC0#C_MbH_
+HMS8bNHsF=C0#C_MbH
+FSOlkLF0C=s#_C0b_HMOF
+SCh=t7N;
+HbR3FNs0Ds8HRM"H"N;
+HsR30FD_sMHoNRlC"#sCCb0_H;M"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"bHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nc(4:::c44Od:Db _HfMRjR:jvB )z_)YpRQA#N0s0_HGHmF_uRajblsHR OD_MbH_
+HMS8bNHOF=Db _HSM
+OLFlF=k0O_D b_HMOF
+SCh=t7N;
+HbR3FNs0Ds8HRM"H"N;
+HER3NM#_L NO_0N0R
+4;N3HRO_8LO{bR
+RNHj6R"dndj_(4U_gncjnj_c.64_d.(c6g_gnd4_n4...c_U_.n4.jU(._46_nc4c4cn4_((nc_..g4"};
+;H
+NR03sDs_FHNoMl"CRO_D b"HM;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8RM"Hb"k0;H
+NR$3#MD_OF_O bRN84N;
+HCRsoMHFRo'PN
+';N3HROODF N_o0oHMR
+4;s@R@nn:n:n(:n.:.:08_FDooCF_OkCM0scr.:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR08_FDooCF_OkCM0sk_F0cr.9b
+SNF8H=08_FDooCF_OkCM0scr.98
+SNH0NMo=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#ocr.9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"80oFoDOC_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::nn(n:n::..8F_0oCoD_kOFMs0Cr:.cjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_0oCoD_kOFMs0C_0Fkr9.d
+NSb8=HF8F_0oCoD_kOFMs0Cr9.d
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr9.d;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"08_FDooCF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nn(n:::nn.8.:_o0Fo_DCOMFk0rCs.jc:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_o0Fo_DCOMFk0_CsFrk0.
+.9S8bNH8F=_o0Fo_DCOMFk0rCs.
+.9S08NN=HMP_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo.;.9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_k.0r4S9
+bHN8F_=80oFoDOC_F0kMC.sr4S9
+8NN0HPM=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_H.or4
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_o0Fo_DCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nn:n:n(:n.:.:08_FDooCF_OkCM0scr.:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR08_FDooCF_OkCM0sk_F0jr.9b
+SNF8H=08_FDooCF_OkCM0sjr.98
+SNH0NMo=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#ojr.9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"80oFoDOC_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::nn(n:n::..8F_0oCoD_kOFMs0Cr:.cjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_0oCoD_kOFMs0C_0Fkr94g
+NSb8=HF8F_0oCoD_kOFMs0Cr94g
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr94g;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"08_FDooCF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nn(n:::nn.8.:_o0Fo_DCOMFk0rCs.jc:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_o0Fo_DCOMFk0_CsFrk04
+U9S8bNH8F=_o0Fo_DCOMFk0rCs4
+U9S08NN=HMP_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo4;U9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_k40r(S9
+bHN8F_=80oFoDOC_F0kMC4sr(S9
+8NN0HPM=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_H4or(
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_o0Fo_DCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nn:n:n(:n.:.:08_FDooCF_OkCM0scr.:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR08_FDooCF_OkCM0sk_F0nr49b
+SNF8H=08_FDooCF_OkCM0snr498
+SNH0NMo=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#onr49N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"80oFoDOC_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::nn(n:n::..8F_0oCoD_kOFMs0Cr:.cjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_0oCoD_kOFMs0C_0Fkr946
+NSb8=HF8F_0oCoD_kOFMs0Cr946
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr946;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"08_FDooCF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nn(n:::nn.8.:_o0Fo_DCOMFk0rCs.jc:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_o0Fo_DCOMFk0_CsFrk04
+c9S8bNH8F=_o0Fo_DCOMFk0rCs4
+c9S08NN=HMP_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo4;c9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_k40rdS9
+bHN8F_=80oFoDOC_F0kMC4srdS9
+8NN0HPM=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_H4ord
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_o0Fo_DCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nn:n:n(:n.:.:08_FDooCF_OkCM0scr.:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR08_FDooCF_OkCM0sk_F0.r49b
+SNF8H=08_FDooCF_OkCM0s.r498
+SNH0NMo=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#o.r49N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"80oFoDOC_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::nn(n:n::..8F_0oCoD_kOFMs0Cr:.cjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_0oCoD_kOFMs0C_0Fkr944
+NSb8=HF8F_0oCoD_kOFMs0Cr944
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr944;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"08_FDooCF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nn(n:::nn.8.:_o0Fo_DCOMFk0rCs.jc:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_o0Fo_DCOMFk0_CsFrk04
+j9S8bNH8F=_o0Fo_DCOMFk0rCs4
+j9S08NN=HMP_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo4;j9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_kg0r9b
+SNF8H=08_FDooCF_OkCM0s9rg
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;g9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_kU0r9b
+SNF8H=08_FDooCF_OkCM0s9rU
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;U9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_k(0r9b
+SNF8H=08_FDooCF_OkCM0s9r(
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;(9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_kn0r9b
+SNF8H=08_FDooCF_OkCM0s9rn
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;n9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_k60r9b
+SNF8H=08_FDooCF_OkCM0s9r6
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;69
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_kc0r9b
+SNF8H=08_FDooCF_OkCM0s9rc
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;c9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_kd0r9b
+SNF8H=08_FDooCF_OkCM0s9rd
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;d9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_k.0r9b
+SNF8H=08_FDooCF_OkCM0s9r.
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;.9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_k40r9b
+SNF8H=08_FDooCF_OkCM0s9r4
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;49
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:n::(n.n:._:80oFoDOC_F0kMC.src9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R80oFoDOC_F0kMCFs_kj0r9b
+SNF8H=08_FDooCF_OkCM0s9rj
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr;j9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8F_0oCoD_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:6::(n46:c_:80oFoDfCRjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_0oCoD_0Fk
+NSb8=HF8F_0oCoD
+NS80MNH=NPo_MOF0DsF_HkM0F30oCoD_o#H;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"08_FDooC
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nn(c:::nc48(:_N#00OC_Df RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl80_#N_0CO_D F
+k0S8bNH8F=_N#00OC_DS
+8NN0HtM=_;dd
+Rob8NN0H
+M;N3bRHo#_N80C_FODO4 R;b
+NR#3H_FODO4 R;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"#8_0CN0_ OD"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:d::(n4d:g_:8PM#$O0_#Nr0Cj9:nR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8PM#$O0_#N_0CFrk0jS9
+bHN8F_=8PM#$O0_#Nr0CjS9
+8NN0HPM=o8N_sCHPsM_kHP03#O$M_N#00jCr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8PM#$O0_#N"0C;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nd:n:n(:dg:4:P8_#O$M_N#00jCr:Rn9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRP8_#O$M_N#00FC_k40r9b
+SNF8H=P8_#O$M_N#004Cr98
+SNH0NMo=PNs_8HsPC_HkM0#3P$_MO#00NC9r4;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P8_#O$M_N#00;C"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::nd(d:n::4g8#_P$_MO#00NC:rjnf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8#_P$_MO#00NCk_F09r.
+NSb8=HF8#_P$_MO#00NC9r.
+NS80MNH=NPo_H8sP_Csk0MH3$P#M#O_0CN0r;.9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8#_P$_MO#00NC
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nn(d:::nd48g:_$P#M#O_0CN0rnj:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$P#M#O_0CN0_0Fkr
+d9S8bNH8F=_$P#M#O_0CN0r
+d9S08NN=HMP_oN8PsHCks_M3H0PM#$O0_#Nr0Cd
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_$P#M#O_0CN0"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:d::(n4d:g_:8PM#$O0_#Nr0Cj9:nR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8PM#$O0_#N_0CFrk0cS9
+bHN8F_=8PM#$O0_#Nr0CcS9
+8NN0HPM=o8N_sCHPsM_kHP03#O$M_N#00cCr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8PM#$O0_#N"0C;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nd:n:n(:dg:4:P8_#O$M_N#00jCr:Rn9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRP8_#O$M_N#00FC_k60r9b
+SNF8H=P8_#O$M_N#006Cr98
+SNH0NMo=PNs_8HsPC_HkM0#3P$_MO#00NC9r6;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P8_#O$M_N#00;C"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::nd(d:n::4g8#_P$_MO#00NC:rjnf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8#_P$_MO#00NCk_F09rn
+NSb8=HF8#_P$_MO#00NC9rn
+NS80MNH=NPo_H8sP_Csk0MH3$P#M#O_0CN0r;n9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8#_P$_MO#00NC
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nn(.:::n.48g:_$E#M#O_0CN0rnj:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$E#M#O_0CN0_0Fkr
+j9S8bNH8F=_$E#M#O_0CN0r
+j9S08NN=HMP_oN8PsHCks_M3H0EM#$O0_#Nr0Cj
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_$E#M#O_0CN0"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:.::(n4.:g_:8EM#$O0_#Nr0Cj9:nR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8EM#$O0_#N_0CFrk04S9
+bHN8F_=8EM#$O0_#Nr0C4S9
+8NN0HPM=o8N_sCHPsM_kHE03#O$M_N#004Cr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8EM#$O0_#N"0C;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n.:n:n(:.g:4:E8_#O$M_N#00jCr:Rn9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRE8_#O$M_N#00FC_k.0r9b
+SNF8H=E8_#O$M_N#00.Cr98
+SNH0NMo=PNs_8HsPC_HkM0#3E$_MO#00NC9r.;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"E8_#O$M_N#00;C"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::n.(.:n::4g8#_E$_MO#00NC:rjnf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8#_E$_MO#00NCk_F09rd
+NSb8=HF8#_E$_MO#00NC9rd
+NS80MNH=NPo_H8sP_Csk0MH3$E#M#O_0CN0r;d9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8#_E$_MO#00NC
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nn(.:::n.48g:_$E#M#O_0CN0rnj:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$E#M#O_0CN0_0Fkr
+c9S8bNH8F=_$E#M#O_0CN0r
+c9S08NN=HMP_oN8PsHCks_M3H0EM#$O0_#Nr0Cc
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_$E#M#O_0CN0"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:.::(n4.:g_:8EM#$O0_#Nr0Cj9:nR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8EM#$O0_#N_0CFrk06S9
+bHN8F_=8EM#$O0_#Nr0C6S9
+8NN0HPM=o8N_sCHPsM_kHE03#O$M_N#006Cr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8EM#$O0_#N"0C;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n.:n:n(:.g:4:E8_#O$M_N#00jCr:Rn9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRE8_#O$M_N#00FC_kn0r9b
+SNF8H=E8_#O$M_N#00nCr98
+SNH0NMo=PNs_8HsPC_HkM0#3E$_MO#00NC9rn;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"E8_#O$M_N#00;C"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::n44n(:4g:4:L8_R:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8Lk_F0b
+SNF8H=L8_
+NS80MNH=NPo_MOF0DsF_HkM0;3L
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8"_L;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n4:n::4.n44:c_:8ojRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_Fo_kS0
+bHN8F_=8o8
+SNH0NMo=PNF_OMF0sDM_kHo03;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"o8_"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@nn:4::(ng4::s8_R:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8sk_F0b
+SNF8H=s8_
+NS80MNH=NPo_MOF0DsF_HkM0;3s
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8"_s;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nj:n:n(:jn:4:P8__NCMLRDCfjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRP8__NCML_DCF
+k0S8bNH8F=_CP_MDNLC8
+SNH0NMo=PNs_8HsPC_HkM0_3PCLMND#C_H
+o;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_CP_MDNLC
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(g:::6g48n:_CE_MDNLCjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_CE_MDNLCk_F0b
+SNF8H=E8__NCML
+DCS08NN=HMP_oN8PsHCks_M3H0EM_CNCLD_o#H;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"E8__NCML"DC;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nU:6::.U6cU:n_:8#_C0PM#$OF_OkCM0sjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_0#C_$P#MOO_F0kMCFs_kS0
+bHN8F_=8#_C0PM#$OF_OkCM0s8
+SNH0NMo=PNs_8HsPC_HkM0_38#_C0PM#$OF_OkCM0sN;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8#_C0PM#$OF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(U:::6U.86:_0#C_$E#MOO_F0kMCfsRjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8C_#0#_E$_MOOMFk0_CsF
+k0S8bNH8F=_0#C_$E#MOO_F0kMCSs
+8NN0HPM=o8N_sCHPsM_kH803_0#C_$E#MOO_F0kMC
+s;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_0#C_$E#MOO_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::6(((:6::.48#_P$_MOOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8PM#$OF_OkCM0sk_F09rg
+NSb8=HF8#_P$_MOOMFk0rCsgS9
+8NN0HPM=o8N_sCHPsM_kHP03#O$M_kOFMs0Cr;g9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8#_P$_MOOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n(:6:6(:(4:.:P8_#O$M_kOFMs0Crjg:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$P#MOO_F0kMCFs_kU0r9b
+SNF8H=P8_#O$M_kOFMs0Cr
+U9S08NN=HMP_oN8PsHCks_M3H0PM#$OF_OkCM0s9rU;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P8_#O$M_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:(::(6.(:4_:8PM#$OF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8#_P$_MOOMFk0_CsFrk0(S9
+bHN8F_=8PM#$OF_OkCM0s9r(
+NS80MNH=NPo_H8sP_Csk0MH3$P#MOO_F0kMC(sr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8PM#$OF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6((:::6(.84:_$P#MOO_F0kMCgsr:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRP8_#O$M_kOFMs0C_0Fkr
+n9S8bNH8F=_$P#MOO_F0kMCnsr98
+SNH0NMo=PNs_8HsPC_HkM0#3P$_MOOMFk0rCsn
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_$P#MOO_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::6(((:6::.48#_P$_MOOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8PM#$OF_OkCM0sk_F09r6
+NSb8=HF8#_P$_MOOMFk0rCs6S9
+8NN0HPM=o8N_sCHPsM_kHP03#O$M_kOFMs0Cr;69
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8#_P$_MOOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n(:6:6(:(4:.:P8_#O$M_kOFMs0Crjg:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$P#MOO_F0kMCFs_kc0r9b
+SNF8H=P8_#O$M_kOFMs0Cr
+c9S08NN=HMP_oN8PsHCks_M3H0PM#$OF_OkCM0s9rc;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P8_#O$M_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:(::(6.(:4_:8PM#$OF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8#_P$_MOOMFk0_CsFrk0dS9
+bHN8F_=8PM#$OF_OkCM0s9rd
+NS80MNH=NPo_H8sP_Csk0MH3$P#MOO_F0kMCdsr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8PM#$OF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6((:::6(.84:_$P#MOO_F0kMCgsr:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRP8_#O$M_kOFMs0C_0Fkr
+.9S8bNH8F=_$P#MOO_F0kMC.sr98
+SNH0NMo=PNs_8HsPC_HkM0#3P$_MOOMFk0rCs.
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_$P#MOO_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::6(((:6::.48#_P$_MOOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8PM#$OF_OkCM0sk_F09r4
+NSb8=HF8#_P$_MOOMFk0rCs4S9
+8NN0HPM=o8N_sCHPsM_kHP03#O$M_kOFMs0Cr;49
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8#_P$_MOOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n(:6:6(:(4:.:P8_#O$M_kOFMs0Crjg:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$P#MOO_F0kMCFs_kj0r9b
+SNF8H=P8_#O$M_kOFMs0Cr
+j9S08NN=HMP_oN8PsHCks_M3H0PM#$OF_OkCM0s9rj;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P8_#O$M_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:n::(6.n:4_:8EM#$OF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8#_E$_MOOMFk0_CsFrk0gS9
+bHN8F_=8EM#$OF_OkCM0s9rg
+NS80MNH=NPo_H8sP_Csk0MH3$E#MOO_F0kMCgsr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8EM#$OF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(n:::6n.84:_$E#MOO_F0kMCgsr:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRE8_#O$M_kOFMs0C_0Fkr
+U9S8bNH8F=_$E#MOO_F0kMCUsr98
+SNH0NMo=PNs_8HsPC_HkM0#3E$_MOOMFk0rCsU
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_$E#MOO_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::6n(n:6::.48#_E$_MOOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8EM#$OF_OkCM0sk_F09r(
+NSb8=HF8#_E$_MOOMFk0rCs(S9
+8NN0HPM=o8N_sCHPsM_kHE03#O$M_kOFMs0Cr;(9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8#_E$_MOOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nn:6:6(:n4:.:E8_#O$M_kOFMs0Crjg:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$E#MOO_F0kMCFs_kn0r9b
+SNF8H=E8_#O$M_kOFMs0Cr
+n9S08NN=HMP_oN8PsHCks_M3H0EM#$OF_OkCM0s9rn;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"E8_#O$M_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:n::(6.n:4_:8EM#$OF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8#_E$_MOOMFk0_CsFrk06S9
+bHN8F_=8EM#$OF_OkCM0s9r6
+NS80MNH=NPo_H8sP_Csk0MH3$E#MOO_F0kMC6sr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8EM#$OF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(n:::6n.84:_$E#MOO_F0kMCgsr:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRE8_#O$M_kOFMs0C_0Fkr
+c9S8bNH8F=_$E#MOO_F0kMCcsr98
+SNH0NMo=PNs_8HsPC_HkM0#3E$_MOOMFk0rCsc
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_$E#MOO_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::6n(n:6::.48#_E$_MOOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8EM#$OF_OkCM0sk_F09rd
+NSb8=HF8#_E$_MOOMFk0rCsdS9
+8NN0HPM=o8N_sCHPsM_kHE03#O$M_kOFMs0Cr;d9
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR8#_E$_MOOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nn:6:6(:n4:.:E8_#O$M_kOFMs0Crjg:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$E#MOO_F0kMCFs_k.0r9b
+SNF8H=E8_#O$M_kOFMs0Cr
+.9S08NN=HMP_oN8PsHCks_M3H0EM#$OF_OkCM0s9r.;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"E8_#O$M_kOFMs0C"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:n::(6.n:4_:8EM#$OF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8#_E$_MOOMFk0_CsFrk04S9
+bHN8F_=8EM#$OF_OkCM0s9r4
+NS80MNH=NPo_H8sP_Csk0MH3$E#MOO_F0kMC4sr9N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR_"8EM#$OF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(n:::6n.84:_$E#MOO_F0kMCgsr:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRE8_#O$M_kOFMs0C_0Fkr
+j9S8bNH8F=_$E#MOO_F0kMCjsr98
+SNH0NMo=PNs_8HsPC_HkM0#3E$_MOOMFk0rCsj
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_$E#MOO_F0kMC;s"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::66.6g:6n:c:#8_CD0_H_MCOMFk0RCsfjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR#8_CD0_H_MCOMFk0_CsF
+k0S8bNH8F=_0#C_MDHCF_OkCM0s8
+SNH0NMo=PNs_8HsPC_HkM0#3P$_MO#00NC9r4;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"#8_CD0_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n6:6:6(:6n:.:#8_CO0_FlDkMF_OkCM0sjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_0#C_DOFk_lMOMFk0_CsF
+k0S8bNH8F=_0#C_DOFk_lMOMFk0
+CsS08NN=HMP_oN8PsHCks_M3H0EM#$O0_#Nr0C4
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_0#C_DOFk_lMOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+U9S8bNH8F=_MDHCF_OkCM0s9rU
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9rU;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+(9S8bNH8F=_MDHCF_OkCM0s9r(
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9r(;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+n9S8bNH8F=_MDHCF_OkCM0s9rn
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9rn;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+69S8bNH8F=_MDHCF_OkCM0s9r6
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9r6;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+c9S8bNH8F=_MDHCF_OkCM0s9rc
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9rc;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+d9S8bNH8F=_MDHCF_OkCM0s9rd
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9rd;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+.9S8bNH8F=_MDHCF_OkCM0s9r.
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9r.;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+49S8bNH8F=_MDHCF_OkCM0s9r4
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9r4;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:6:6(:cj:.:D8_H_MCOMFk0rCsU9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8DCHM_kOFMs0C_0Fkr
+j9S8bNH8F=_MDHCF_OkCM0s9rj
+NS80MNH=NPo_H8sP_Csk0MH3MDHCF_OkCM0sH_#o9rj;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nd:6:6(:d.:.:O8_FlDkMF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_ODMkl_kOFMs0C_0Fkr
+g9S8bNH8F=_DOFk_lMOMFk0rCsgS9
+8NN0HPM=o8N_sCHPsM_kHO03FlDkMF_OkCM0sH_#o9rg;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"O8_FlDkMF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(d:::6d.8.:_DOFk_lMOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8OkFDlOM_F0kMCFs_kU0r9b
+SNF8H=O8_FlDkMF_OkCM0s9rU
+NS80MNH=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHoU
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_DOFk_lMOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nd:6:6(:d.:.:O8_FlDkMF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_ODMkl_kOFMs0C_0Fkr
+(9S8bNH8F=_DOFk_lMOMFk0rCs(S9
+8NN0HPM=o8N_sCHPsM_kHO03FlDkMF_OkCM0sH_#o9r(;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"O8_FlDkMF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(d:::6d.8.:_DOFk_lMOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8OkFDlOM_F0kMCFs_kn0r9b
+SNF8H=O8_FlDkMF_OkCM0s9rn
+NS80MNH=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHon
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_DOFk_lMOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nd:6:6(:d.:.:O8_FlDkMF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_ODMkl_kOFMs0C_0Fkr
+69S8bNH8F=_DOFk_lMOMFk0rCs6S9
+8NN0HPM=o8N_sCHPsM_kHO03FlDkMF_OkCM0sH_#o9r6;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"O8_FlDkMF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(d:::6d.8.:_DOFk_lMOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8OkFDlOM_F0kMCFs_kc0r9b
+SNF8H=O8_FlDkMF_OkCM0s9rc
+NS80MNH=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHoc
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_DOFk_lMOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nd:6:6(:d.:.:O8_FlDkMF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_ODMkl_kOFMs0C_0Fkr
+d9S8bNH8F=_DOFk_lMOMFk0rCsdS9
+8NN0HPM=o8N_sCHPsM_kHO03FlDkMF_OkCM0sH_#o9rd;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"O8_FlDkMF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(d:::6d.8.:_DOFk_lMOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8OkFDlOM_F0kMCFs_k.0r9b
+SNF8H=O8_FlDkMF_OkCM0s9r.
+NS80MNH=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHo.
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_DOFk_lMOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nd:6:6(:d.:.:O8_FlDkMF_OkCM0s:rgjf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl8F_ODMkl_kOFMs0C_0Fkr
+49S8bNH8F=_DOFk_lMOMFk0rCs4S9
+8NN0HPM=o8N_sCHPsM_kHO03FlDkMF_OkCM0sH_#o9r4;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"O8_FlDkMF_OkCM0s
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(d:::6d.8.:_DOFk_lMOMFk0rCsg9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl_R8OkFDlOM_F0kMCFs_kj0r9b
+SNF8H=O8_FlDkMF_OkCM0s9rj
+NS80MNH=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHoj
+9;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC8R"_DOFk_lMOMFk0"Cs;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n.:6::4n6..:._:8PM#$OjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$P#MFO_kS0
+bHN8F_=8PM#$O8
+SNH0NMo=PNs_8HsPC_HkM0_3P#O$M;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P8_#O$M"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:.::(64.:d_:8EM#$OjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH8lR_$E#MFO_kS0
+bHN8F_=8EM#$O8
+SNH0NMo=PNs_8HsPC_HkM0_3E#O$M;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"E8_#O$M"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:j::(64j:gC:#P_CM#_CobrHM4jd:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH#lRCMPC_o#C_MbH_H0sr94d
+NSb8=HF#CCPMC_#oH_bMdr498
+SNH0NMB=eBN;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";N3HR0RsH"s30H
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC#R"CMPC_o#C_MbH"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nj:6:6(:jg:4:P#CC#M_Cbo_H4Mrd9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbslCR#P_CM#_Cob_HMFrk04
+.9S8bNH#F=CMPC_o#C_MbHr94.
+NS80MNH=p7 q)Y_ a1 _GMC0k\3M8n_DO$_F0kMCjs__
+G;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC#R"CMPC_o#C_MbH"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:j::(64j:gC:#P_CM#_CobrHM4jd:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH#lRCMPC_o#C_MbH_0Fkr944
+NSb8=HF#CCPMC_#oH_bM4r498
+SNH0NM =7p_qY) 1aC_MG30\k_Mn8_D$OMFk0_Csj;_G
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR#CCPMC_#oH_bM
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(j:::6j4#g:CMPC_o#C_MbHr:4djf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl#CCPMC_#oH_bMk_F0jr49b
+SNF8H=P#CC#M_Cbo_H4MrjS9
+8NN0H7M= Ypq_1) Ma_C\G03nkM_$8D_kOFMs0C_Gj_;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P#CC#M_Cbo_H;M"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::6j(j:6::4g#CCPMC_#oH_bMdr4:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRP#CC#M_Cbo_HFM_kg0r9b
+SNF8H=P#CC#M_Cbo_HgMr98
+SNH0NM =7p_qY) 1aC_MG30\k_Mn8_D$OMFk0_Csj;_G
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR#CCPMC_#oH_bM
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(j:::6j4#g:CMPC_o#C_MbHr:4djf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl#CCPMC_#oH_bMk_F09rU
+NSb8=HF#CCPMC_#oH_bM9rU
+NS80MNH=p7 q)Y_ a1 _GMC0k\3M8n_DO$_F0kMCjs__
+G;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC#R"CMPC_o#C_MbH"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:j::(64j:gC:#P_CM#_CobrHM4jd:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH#lRCMPC_o#C_MbH_0Fkr
+(9S8bNH#F=CMPC_o#C_MbHr
+(9S08NN=HM7q pY _)1_ aM0CG\M3knD_8$F_OkCM0s__jGN;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlRC"#P_CM#_Cob"HM;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nj:6:6(:jg:4:P#CC#M_Cbo_H4Mrd9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbslCR#P_CM#_Cob_HM0rsHnS9
+bHN8FC=#P_CM#_CobrHMnS9
+8NN0HeM=B
+B;N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNH3H0sR0"3s;H"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR#CCPMC_#oH_bM
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@6n:j::(64j:gC:#P_CM#_CobrHM4jd:9jRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbH#lRCMPC_o#C_MbH_H0sr
+69S8bNH#F=CMPC_o#C_MbHr
+69S08NN=HMe;BB
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRs30H3R"0"sH;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P#CC#M_Cbo_H;M"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(j:::6j4#g:CMPC_o#C_MbHr:4djf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl#CCPMC_#oH_bMs_0H9rc
+NSb8=HF#CCPMC_#oH_bM9rc
+NS80MNH=BeB;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+H0R3s"HR3H0s"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlRC"#P_CM#_Cob"HM;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::6j(j:6::4g#CCPMC_#oH_bMdr4:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRP#CC#M_Cbo_H0M_sdHr9b
+SNF8H=P#CC#M_Cbo_HdMr98
+SNH0NMB=eBN;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";N3HR0RsH"s30H
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNC#R"CMPC_o#C_MbH"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nj:6:6(:jg:4:P#CC#M_Cbo_H4Mrd9:jR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbslCR#P_CM#_Cob_HMFrk0.S9
+bHN8FC=#P_CM#_CobrHM.S9
+8NN0H7M= Ypq_1) Ma_C\G03nkM_$8D_kOFMs0C_Gj_;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"P#CC#M_Cbo_H;M"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::6j(j:6::4g#CCPMC_#oH_bMdr4:Rj9fjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHRP#CC#M_Cbo_HFM_k40r9b
+SNF8H=P#CC#M_Cbo_H4Mr98
+SNH0NM =7p_qY) 1aC_MG30\k_Mn8_D$OMFk0_Csj;_G
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CR#CCPMC_#oH_bM
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@n6(j:::6j4#g:CMPC_o#C_MbHr:4djf9RjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHl#CCPMC_#oH_bMs_0H9rj
+NSb8=HF#CCPMC_#oH_bM9rj
+NS80MNH=BeB;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+H0R3s"HR3H0s"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlRC"#P_CM#_Cob"HM;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::cU(U:c::46PM#$OH_bMjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbHPlR#O$M_MbH_0Fk
+NSb8=HFPM#$OH_bM8
+SNH0NMo=PNs_8HsPC_HkM0_3P#O$M;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"$P#MbO_H;M"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::c(((:c::46EM#$OH_bMjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbHElR#O$M_MbH_0Fk
+NSb8=HFEM#$OH_bM8
+SNH0NMo=PNs_8HsPC_HkM0_3E#O$M;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"$E#MbO_H;M"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::cn4c6:nj:.:_L4bRHMfjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR_L4b_HMF
+k0S8bNHLF=4H_bM8
+SNH0NMo=PNF_OMF0sDM_kHL03;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"_L4b"HM;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nn:c:c(:n.:4:_LjbRHMfjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR_Ljb_HMF
+k0S8bNHLF=jH_bM8
+SNH0NMo=PNF_OMF0sDM_kHL03;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"_Ljb"HM;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@n6:c::.dc.6:U.:o_MbHR:fjj Rv))BzYQ_pA0R#sHN0GF_H_ju7RHbsl.Ro_MbH_0Fk
+NSb8=HFob._HSM
+8NN0HPM=oON_FsM0FkD_M3H0oN;
+HbR3FNs0Ds8HRk"F0
+";N3HRs_0DFosHMCNlR."o_MbH"N;
+HPR3CDsHFbo_NlsN#FR"bNCs0MHF_8lFCM,Hb_k0sHCo#s0C_8lFCH,RM0bk_$N#MsO_C0#C,bHMk#0_$_MOsCC#0H,RM0bk_IbFCks_bF,Rkk0b0C_so0H#Cls_F,8CR0Fkb_k0NM#$OC_s#,C0Fbk0k#0_$_MOsCC#0F,Rkk0b0F_bI_CskFb,CC_so0H#Cls_F,8CR_FCNM#$OC_s#,C0F#C_$_MOsCC#0F,RCF_bI_CskRb,FMbC_N8sHFM_kk0b0
+";NFHRbNCs0MHF_8lFCFR"kk0b0
+";N3HR#FDbs8HoH"sRHkMF0
+";NsHRCFoHMPR'o;N'
+@sR@cn:66:4::c6.oj:4H_bMjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbHolR4H_bMk_F0b
+SNF8H=_o4b
+HMS08NN=HMP_oNO0FMs_FDk0MH3
+o;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNCoR"4H_bM
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nc(6:::c64o.:jH_bMjRf:vjR z)B)pY_Q#AR00sNHHG_F7_ujsRbHolRjH_bMk_F0b
+SNF8H=_ojb
+HMS08NN=HMP_oNO0FMs_FDk0MH3
+o;N3HRb0FsNHD8sFR"k;0"
+RNH3Ds0_HFsolMNCoR"jH_bM
+";N3HRPHCsD_FobNNsl"#RFsbCNF0HMF_l8HC,M0bk_osCHC#0sF_l8RC,HkMb0#_N$_MOsCC#0M,Hb_k0#O$M_#sCCR0,HkMb0F_bI_CskRb,Fbk0ks0_C#oH0_CslCF8,kRF00bk_$N#MsO_C0#C,0Fkb_k0#O$M_#sCCR0,Fbk0kb0_FsIC_,kbFsC_C#oH0_CslCF8,CRF_$N#MsO_C0#C,_FC#O$M_#sCCR0,FbC_FsIC_,kbRCFbMs_8N_HMFbk0k;0"
+RNHFsbCNF0HMF_l8"CRFbk0k;0"
+RNH3b#DFosH8RHs"FHMk;0"
+RNHsHCoF'MRP'oN;R
+s@:@nc.c:dc:c::.Usb._HfMRjR:jvB )z_)YpRQA#N0s0_HGHuF_7bjRsRHlsb._HFM_kS0
+bHN8F.=s_MbH
+NS80MNH=NPo_MOF0DsF_HkM0;3s
+RNH3sbF08NDH"sRF"k0;H
+NR03sDs_FHNoMl"CRsb._H;M"
+RNH3sPCHoDF_sbNNRl#"CFbsHN0FlM_F,8CHkMb0C_so0H#Cls_F,8CRbHMkN0_#O$M_#sCCH0,M0bk_M#$OC_s#,C0RbHMkb0_FsIC_,kbR0Fkb_k0sHCo#s0C_8lFCF,Rkk0b0#_N$_MOsCC#0k,F00bk_M#$OC_s#,C0R0Fkb_k0bCFIsb_k,_FCsHCo#s0C_8lFCF,RC#_N$_MOsCC#0C,F_M#$OC_s#,C0R_FCbCFIsb_k,bRFC8M_sMNH_0Fkb"k0;H
+NRCFbsHN0FlM_FR8C"0Fkb"k0;H
+NRD3#bHFsos8HRM"HF"k0;H
+NRosCHRFM'NPo's;
+Rn@@::cc4c6:cj:.:_s4bRHMfjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR_s4b_HMF
+k0S8bNHsF=4H_bM8
+SNH0NMo=PNF_OMF0sDM_kHs03;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"_s4b"HM;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';s@R@nc:c:c(:c.:4:_sjbRHMfjj:R)v BYz)_ApQRs#0NG0H__HFuR7jblsHR_sjb_HMF
+k0S8bNHsF=jH_bM8
+SNH0NMo=PNF_OMF0sDM_kHs03;H
+NRF3bsD0N8RHs"0Fk"N;
+HsR30FD_sMHoNRlC"_sjb"HM;H
+NRC3PsFHDoN_bs#NlRb"FC0sNH_FMlCF8,bHMks0_C#oH0_CslCF8,MRHb_k0NM#$OC_s#,C0HkMb0$_#MsO_C0#C,MRHb_k0bCFIsb_k,kRF00bk_osCHC#0sF_l8RC,Fbk0kN0_#O$M_#sCCF0,kk0b0$_#MsO_C0#C,kRF00bk_IbFCks_bC,F_osCHC#0sF_l8RC,FNC_#O$M_#sCCF0,C$_#MsO_C0#C,CRF_IbFCks_bF,Rb_CM8HsNMk_F00bk"N;
+HbRFC0sNH_FMlCF8Rk"F00bk"N;
+H#R3DsbFHHo8sHR"M0Fk"N;
+HCRsoMHFRo'PN
+';b@R@n4:c:c(:4d:4: OD_MbHR:fjjCR CkbLV_RtdtdR_RddO_D b_HMOo;
+brRQj
+9;N3bRHo#_N80C_FODO4 R;b
+NR#3H_FODO4 R;H
+NRosCHRFM'NPo's;
+R4@@jn:44::j4:n44.c+:NPo_H8sP_Csk0MHR:fjjFRIsP Ro8N_sCHPsCRM0#DH0oRPNs_8HsPC_HkM0D
+SH_MCOMFk0_Cs#_Hojo=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_Hjor9D
+SH_MCOMFk0_Cs#_Ho4o=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_H4or9D
+SH_MCOMFk0_Cs#_Ho.o=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_H.or9D
+SH_MCOMFk0_Cs#_Hodo=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_Hdor9D
+SH_MCOMFk0_Cs#_Hoco=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_Hcor9D
+SH_MCOMFk0_Cs#_Ho6o=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_H6or9D
+SH_MCOMFk0_Cs#_Hono=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_Hnor9D
+SH_MCOMFk0_Cs#_Ho(o=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_H(or9D
+SH_MCOMFk0_Cs#_HoUo=PNs_8HsPC_HkM0H3DMOC_F0kMC#s_HUor98
+SDO$_F0kMC4s_=$8D_kOFMs0Cr
+49S$8D_kOFMs0C_8j=DO$_F0kMCjsr9P
+S#O$M_N#00.C_=NPo_H8sP_Csk0MH3$P#M#O_0CN0r
+.9S$P#M#O_0CN0_P6=o8N_sCHPsM_kHP03#O$M_N#006Cr9P
+S#O$M_N#00dC_=NPo_H8sP_Csk0MH3$P#M#O_0CN0r
+d9S$P#M#O_0CN0_Pn=o8N_sCHPsM_kHP03#O$M_N#00nCr9P
+S#O$M_N#00cC_=NPo_H8sP_Csk0MH3$P#M#O_0CN0r
+c9S$P#M#O_0CN0_P4=o8N_sCHPsM_kHP03#O$M_N#004Cr9P
+S#O$M_N#00jC_=NPo_H8sP_Csk0MH3$P#M#O_0CN0r
+j9S$E#M#O_0CN0_P.=o8N_sCHPsM_kHE03#O$M_N#00.Cr9E
+S#O$M_N#00cC_=NPo_H8sP_Csk0MH3$E#M#O_0CN0r
+c9S$E#M#O_0CN0_Pj=o8N_sCHPsM_kHE03#O$M_N#00jCr9E
+S#O$M_N#006C_=NPo_H8sP_Csk0MH3$E#M#O_0CN0r
+69S$E#M#O_0CN0_P4=o8N_sCHPsM_kHE03#O$M_N#004Cr9E
+S#O$M_N#00dC_=NPo_H8sP_Csk0MH3$E#M#O_0CN0r
+d9S$E#M#O_0CN0_Pn=o8N_sCHPsM_kHE03#O$M_N#00nCr9O
+SFlDkMF_OkCM0sH_#o=_jP_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_Hjor9O
+SFlDkMF_OkCM0sH_#o=_4P_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_H4or9O
+SFlDkMF_OkCM0sH_#o=_.P_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_H.or9O
+SFlDkMF_OkCM0sH_#o=_dP_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_Hdor9O
+SFlDkMF_OkCM0sH_#o=_cP_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_Hcor9O
+SFlDkMF_OkCM0sH_#o=_6P_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_H6or9O
+SFlDkMF_OkCM0sH_#o=_nP_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_Hnor9O
+SFlDkMF_OkCM0sH_#o=_(P_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_H(or9O
+SFlDkMF_OkCM0sH_#o=_UP_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_HUor9O
+SFlDkMF_OkCM0sH_#o=_gP_oN8PsHCks_M3H0OkFDlOM_F0kMC#s_Hgor9P
+S#O$M_kOFMs0C_Pg=o8N_sCHPsM_kHP03#O$M_kOFMs0Cr
+g9S$P#MOO_F0kMCUs_=NPo_H8sP_Csk0MH3$P#MOO_F0kMCUsr9P
+S#O$M_kOFMs0C_P(=o8N_sCHPsM_kHP03#O$M_kOFMs0Cr
+(9S$P#MOO_F0kMCns_=NPo_H8sP_Csk0MH3$P#MOO_F0kMCnsr9P
+S#O$M_kOFMs0C_P6=o8N_sCHPsM_kHP03#O$M_kOFMs0Cr
+69S$P#MOO_F0kMCcs_=NPo_H8sP_Csk0MH3$P#MOO_F0kMCcsr9P
+S#O$M_kOFMs0C_Pd=o8N_sCHPsM_kHP03#O$M_kOFMs0Cr
+d9S$P#MOO_F0kMC.s_=NPo_H8sP_Csk0MH3$P#MOO_F0kMC.sr9P
+S#O$M_kOFMs0C_P4=o8N_sCHPsM_kHP03#O$M_kOFMs0Cr
+49S$P#MOO_F0kMCjs_=NPo_H8sP_Csk0MH3$P#MOO_F0kMCjsr9E
+S#O$M_kOFMs0C_Pg=o8N_sCHPsM_kHE03#O$M_kOFMs0Cr
+g9S$E#MOO_F0kMCUs_=NPo_H8sP_Csk0MH3$E#MOO_F0kMCUsr9E
+S#O$M_kOFMs0C_P(=o8N_sCHPsM_kHE03#O$M_kOFMs0Cr
+(9S$E#MOO_F0kMCns_=NPo_H8sP_Csk0MH3$E#MOO_F0kMCnsr9E
+S#O$M_kOFMs0C_P6=o8N_sCHPsM_kHE03#O$M_kOFMs0Cr
+69S$E#MOO_F0kMCcs_=NPo_H8sP_Csk0MH3$E#MOO_F0kMCcsr9E
+S#O$M_kOFMs0C_Pd=o8N_sCHPsM_kHE03#O$M_kOFMs0Cr
+d9S$E#MOO_F0kMC.s_=NPo_H8sP_Csk0MH3$E#MOO_F0kMC.sr9E
+S#O$M_kOFMs0C_P4=o8N_sCHPsM_kHE03#O$M_kOFMs0Cr
+49S$E#MOO_F0kMCjs_=NPo_H8sP_Csk0MH3$E#MOO_F0kMCjsr98
+S_0#C_$P#MOO_F0kMCPs=o8N_sCHPsM_kH803_0#C_$P#MOO_F0kMCSs
+P$_#MPO=o8N_sCHPsM_kHP03_M#$OE
+S_M#$Oo=PNs_8HsPC_HkM0_3E#O$M
+_SECLMND#C_HPo=o8N_sCHPsM_kHE03_NCML_DC#
+HoSCP_MDNLCH_#oo=PNs_8HsPC_HkM0_3PCLMND#C_HSo
+sCC#0H_bM=_OsCC#0H_bM
+_OSnkM_$8D_kOFMs0C_Gj_=p7 q)Y_ a1 _GMC0k\3M8n_DO$_F0kMCjs__SG
+8C_#0#_E$_MOOMFk0=CsP_oN8PsHCks_M3H08C_#0#_E$_MOOMFk0
+CsS OD_MbH_OO=Db _HOM_;b
+oRMDHCF_OkCM0sH_#o;_j
+RNb3RbVdo;
+bHRDMOC_F0kMC#s_H4o_;b
+NRV3bR
+d;oDbRH_MCOMFk0_Cs#_Ho.N;
+bbR3V;Rd
+RobDCHM_kOFMs0C_o#H_
+d;N3bRbdVR;b
+oRMDHCF_OkCM0sH_#o;_c
+RNb3RbVdo;
+bHRDMOC_F0kMC#s_H6o_;b
+NRV3bR
+d;oDbRH_MCOMFk0_Cs#_HonN;
+bbR3V;Rd
+RobDCHM_kOFMs0C_o#H_
+(;N3bRbdVR;b
+oRMDHCF_OkCM0sH_#o;_U
+RNb3RbV.o;
+bDR8$F_OkCM0s;_4
+RNb3RbV(o;
+bDR8$F_OkCM0s;_j
+RNb3RbV(o;
+b#RP$_MO#00NC;_.
+RNb3RbVdo;
+b#RP$_MO#00NC;_6
+RNb3RbVdo;
+b#RP$_MO#00NC;_d
+RNb3RbVco;
+b#RP$_MO#00NC;_n
+RNb3RbVdo;
+b#RP$_MO#00NC;_c
+RNb3RbVco;
+b#RP$_MO#00NC;_4
+RNb3RbVco;
+b#RP$_MO#00NC;_j
+RNb3RbVco;
+b#RE$_MO#00NC;_.
+RNb3RbVdo;
+b#RE$_MO#00NC;_c
+RNb3RbVco;
+b#RE$_MO#00NC;_j
+RNb3RbVdo;
+b#RE$_MO#00NC;_6
+RNb3RbVdo;
+b#RE$_MO#00NC;_4
+RNb3RbVco;
+b#RE$_MO#00NC;_d
+RNb3RbVco;
+b#RE$_MO#00NC;_n
+RNb3RbVdo;
+bFRODMkl_kOFMs0C_o#H_
+j;N3bRbcVR;b
+oRDOFk_lMOMFk0_Cs#_Ho4N;
+bbR3V;Rd
+RobOkFDlOM_F0kMC#s_H.o_;b
+NRV3bR
+d;oObRFlDkMF_OkCM0sH_#o;_d
+RNb3RbVdo;
+bFRODMkl_kOFMs0C_o#H_
+c;N3bRbdVR;b
+oRDOFk_lMOMFk0_Cs#_Ho6N;
+bbR3V;Rd
+RobOkFDlOM_F0kMC#s_Hno_;b
+NRV3bR
+d;oObRFlDkMF_OkCM0sH_#o;_(
+RNb3RbVdo;
+bFRODMkl_kOFMs0C_o#H_
+U;N3bRbdVR;b
+oRDOFk_lMOMFk0_Cs#_HogN;
+bbR3V;R.
+RobPM#$OF_OkCM0s;_g
+RNb3RbVUo;
+b#RP$_MOOMFk0_CsUN;
+bbR3V;Rc
+RobPM#$OF_OkCM0s;_(
+RNb3RbVco;
+b#RP$_MOOMFk0_CsnN;
+bbR3V;Rc
+RobPM#$OF_OkCM0s;_6
+RNb3RbVco;
+b#RP$_MOOMFk0_CscN;
+bbR3V;Rc
+RobPM#$OF_OkCM0s;_d
+RNb3RbVco;
+b#RP$_MOOMFk0_Cs.N;
+bbR3V;Rc
+RobPM#$OF_OkCM0s;_4
+RNb3RbVco;
+b#RP$_MOOMFk0_CsjN;
+bbR3V;RU
+RobEM#$OF_OkCM0s;_g
+RNb3RbV6o;
+b#RE$_MOOMFk0_CsUN;
+bbR3V;R6
+RobEM#$OF_OkCM0s;_(
+RNb3RbVno;
+b#RE$_MOOMFk0_CsnN;
+bbR3V;Rn
+RobEM#$OF_OkCM0s;_6
+RNb3RbV6o;
+b#RE$_MOOMFk0_CscN;
+bbR3V;Rn
+RobEM#$OF_OkCM0s;_d
+RNb3RbV6o;
+b#RE$_MOOMFk0_Cs.N;
+bbR3V;R6
+RobEM#$OF_OkCM0s;_4
+RNb3RbV6o;
+b#RE$_MOOMFk0_CsjN;
+bbR3V;R6
+Rob8C_#0#_P$_MOOMFk0;Cs
+RNb3RbV4o;
+b_RP#O$M;b
+NRV3bR
+4;oEbR_M#$ON;
+bbR3V;R4
+RobEM_CNCLD_o#H;b
+NRV3bR
+j;oPbR_NCML_DC#;Ho
+RNb3RbVjo;
+bCRs#_C0b_HMON;
+bbR3V;R(
+Robk_Mn8_D$OMFk0_Csj;_G
+RNb3RbV.
+4;o8bR_0#C_$E#MOO_F0kMC
+s;N3bRbcVR;b
+oR OD_MbH_
+O;N3bRHo#_N80C_FODO4 R;b
+NR#3H_FODO4 R;b
+NRV3bR;6(
+RNH3b#DFosH8RHs"FHMk;0"
+@sR@:4j4:Un.U:4n(:4+P.:oON_FsM0FkD_MRH0fjj:RsIF oRPNF_OMF0sDCRM0#DH0oRPNF_OMF0sDM_kHS0
+DCHM_kOFMs0C_o#H_Pj=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHojS9
+DCHM_kOFMs0C_o#H_P.=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHo.S9
+DCHM_kOFMs0C_o#H_P4=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHo4S9
+DCHM_kOFMs0C_o#H_Pd=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHodS9
+DCHM_kOFMs0C_o#H_Pn=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHonS9
+DCHM_kOFMs0C_o#H_P6=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHo6S9
+DCHM_kOFMs0C_o#H_Pc=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHocS9
+DCHM_kOFMs0C_o#H_P(=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHo(S9
+DCHM_kOFMs0C_o#H_PU=o8N_sCHPsM_kHD03H_MCOMFk0_Cs#rHoUS9
+OkFDlOM_F0kMC#s_Hjo_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHojS9
+OkFDlOM_F0kMC#s_H4o_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHo4S9
+OkFDlOM_F0kMC#s_H.o_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHo.S9
+OkFDlOM_F0kMC#s_HUo_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHoUS9
+OkFDlOM_F0kMC#s_Hdo_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHodS9
+OkFDlOM_F0kMC#s_H6o_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHo6S9
+OkFDlOM_F0kMC#s_Hco_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHocS9
+OkFDlOM_F0kMC#s_Hgo_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHogS9
+OkFDlOM_F0kMC#s_H(o_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHo(S9
+OkFDlOM_F0kMC#s_Hno_=NPo_H8sP_Csk0MH3DOFk_lMOMFk0_Cs#rHonS9
+0oFoDOC_F0kMC#s_Hjo_=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr
+j9So0Fo_DCOMFk0_Cs#_Ho4o=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#o9r4
+FS0oCoD_kOFMs0C_o#H_P.=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_H.or90
+SFDooCF_OkCM0sH_#o=_dP_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHodS9
+0oFoDOC_F0kMC#s_Hco_=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr
+c9So0Fo_DCOMFk0_Cs#_Ho6o=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#o9r6
+FS0oCoD_kOFMs0C_o#H_Pn=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_Hnor90
+SFDooCF_OkCM0sH_#o=_(P_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo(S9
+0oFoDOC_F0kMC#s_HUo_=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr
+U9So0Fo_DCOMFk0_Cs#_Hogo=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#o9rg
+FS0oCoD_kOFMs0C_o#H_=4jP_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo4
+j9So0Fo_DCOMFk0_Cs#_Ho4P4=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_H4or4S9
+0oFoDOC_F0kMC#s_H4o_.o=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#o.r490
+SFDooCF_OkCM0sH_#od_4=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr94d
+FS0oCoD_kOFMs0C_o#H_=4cP_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo4
+c9So0Fo_DCOMFk0_Cs#_Ho4P6=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_H4or6S9
+0oFoDOC_F0kMC#s_H4o_no=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#onr490
+SFDooCF_OkCM0sH_#o(_4=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr94(
+FS0oCoD_kOFMs0C_o#H_=4UP_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo4
+U9So0Fo_DCOMFk0_Cs#_Ho4Pg=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_H4orgS9
+0oFoDOC_F0kMC#s_H.o_jo=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#ojr.90
+SFDooCF_OkCM0sH_#o4_.=NPo_MOF0DsF_HkM0F30oCoD_kOFMs0C_o#Hr9.4
+FS0oCoD_kOFMs0C_o#H_=..P_oNO0FMs_FDk0MH3o0Fo_DCOMFk0_Cs#rHo.
+.9So0Fo_DCOMFk0_Cs#_Ho.Pd=oON_FsM0FkD_M3H00oFoDOC_F0kMC#s_H.ordS9
+0oFoDOC_F0kMC#s_H.o_co=PNF_OMF0sDM_kH003FDooCF_OkCM0sH_#ocr.9E
+S_NCML_DC#=HoP_oN8PsHCks_M3H0EM_CNCLD_o#H
+=SoP_oNO0FMs_FDk0MH3So
+Lo=PNF_OMF0sDM_kHL03
+_SPCLMND#C_HPo=o8N_sCHPsM_kHP03_NCML_DC#
+HoSPs=oON_FsM0FkD_M3H0s0
+SFDooCH_#oo=PNF_OMF0sDM_kH003FDooCH_#ok
+SM8n_DO$_F0kMCjs__7G= Ypq_1) Ma_C\G03nkM_$8D_kOFMs0C_Gj_
+DSO H_bM=_OO_D b_HMOo;
+bHRDMOC_F0kMC#s_Hjo_;b
+NRV3bR
+4;oDbRH_MCOMFk0_Cs#_Ho.N;
+bbR3V;R.
+RobDCHM_kOFMs0C_o#H_
+4;N3bRb4VR;b
+oRMDHCF_OkCM0sH_#o;_d
+RNb3RbV.o;
+bHRDMOC_F0kMC#s_Hno_;b
+NRV3bR
+.;oDbRH_MCOMFk0_Cs#_Ho6N;
+bbR3V;R.
+RobDCHM_kOFMs0C_o#H_
+c;N3bRb.VR;b
+oRMDHCF_OkCM0sH_#o;_(
+RNb3RbV4o;
+bHRDMOC_F0kMC#s_HUo_;b
+NRV3bR
+.;oObRFlDkMF_OkCM0sH_#o;_j
+RNb3RbV4o;
+bFRODMkl_kOFMs0C_o#H_
+4;N3bRb4VR;b
+oRDOFk_lMOMFk0_Cs#_Ho.N;
+bbR3V;R.
+RobOkFDlOM_F0kMC#s_HUo_;b
+NRV3bR
+4;oObRFlDkMF_OkCM0sH_#o;_d
+RNb3RbV.o;
+bFRODMkl_kOFMs0C_o#H_
+6;N3bRb.VR;b
+oRDOFk_lMOMFk0_Cs#_HocN;
+bbR3V;R.
+RobOkFDlOM_F0kMC#s_Hgo_;b
+NRV3bR
+.;oObRFlDkMF_OkCM0sH_#o;_(
+RNb3RbV.o;
+bFRODMkl_kOFMs0C_o#H_
+n;N3bRb.VR;b
+oRo0Fo_DCOMFk0_Cs#_HojN;
+bbR3V;Rd
+Rob0oFoDOC_F0kMC#s_H4o_;b
+NRV3bR
+.;o0bRFDooCF_OkCM0sH_#o;_.
+RNb3RbV.o;
+bFR0oCoD_kOFMs0C_o#H_
+d;N3bRb.VR;b
+oRo0Fo_DCOMFk0_Cs#_HocN;
+bbR3V;R.
+Rob0oFoDOC_F0kMC#s_H6o_;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#o;_n
+RNb3RbVdo;
+bFR0oCoD_kOFMs0C_o#H_
+(;N3bRbdVR;b
+oRo0Fo_DCOMFk0_Cs#_HoUN;
+bbR3V;Rd
+Rob0oFoDOC_F0kMC#s_Hgo_;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#oj_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#o4_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#o._4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#od_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#oc_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#o6_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#on_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#o(_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#oU_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#og_4;b
+NRV3bR
+d;o0bRFDooCF_OkCM0sH_#oj_.;b
+NRV3bR
+.;o0bRFDooCF_OkCM0sH_#o4_.;b
+NRV3bR
+4;o0bRFDooCF_OkCM0sH_#o._.;b
+NRV3bR
+4;o0bRFDooCF_OkCM0sH_#od_.;b
+NRV3bR
+4;o0bRFDooCF_OkCM0sH_#oc_.;b
+NRV3bR
+4;oEbR_NCML_DC#;Ho
+RNb3RbV4o;
+b;Ro
+RNb3RbVjo;
+b;RL
+RNb3RbVjo;
+b_RPCLMND#C_H
+o;N3bRb.VR;b
+oR
+s;N3bRbjVR;b
+oRo0Fo_DC#;Ho
+RNb3RbVdo;
+bMRknD_8$F_OkCM0s__jGN;
+bbR3VgR.;b
+oR OD_MbH_
+O;N3bRHo#_N80C_FODO4 R;b
+NR#3H_FODO4 R;b
+NRV3bR;.g
+RNH3b#DFosH8RHs"FHMk;0"
--- /dev/null
+#Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
+#install: /opt/synplify/fpga_c200906
+#OS: Linux
+#Hostname: ti12
+
+#Implementation: rev_1
+
+#Wed Oct 21 17:26:30 2009
+
+$ Start of Compile
+#Wed Oct 21 17:26:30 2009
+
+Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+
+@N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
+VHDL syntax check successful!
+
+Compiler output is up to date. No re-compile necessary
+
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav
+Post processing for work.vga_control.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+Post processing for work.vga_driver.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav
+Post processing for work.board_driver.behav
+Post processing for work.vga.behav
+@END
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:26:30 2009
+
+###########################################################]
+Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
+Product Version C-2009.06
+@N: MF249 |Running in 32-bit mode.
+@N: MF257 |Gated clock conversion enabled
+@N|Running in logic synthesis mode without enhanced optimization
+
+Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
+Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
+
+Available hyper_sources - for debug and ip models
+ None Found
+
+Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":267:4:267:5|Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
+@N:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":158:4:158:5|Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
+
+Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
+
+
+
+#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
+
+======================================================================================
+ Instance:Pin Generated Clock Optimization Status
+======================================================================================
+
+
+##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
+
+Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
+
+Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
+
+Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 68MB)
+
+
+Writing Analyst data base /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.srm
+Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Writing Verilog Netlist and constraint files
+Writing .vqm output for Quartus
+Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.xrf
+Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Writing VHDL Simulation files
+Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design
+Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design
+Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB)
+
+Found clock vga|clk_pin with period 39.72ns
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Oct 21 17:26:36 2009
+#
+
+
+Top view: vga
+Requested Frequency: 25.2 MHz
+Wire load mode: top
+Paths requested: 5
+Constraint File(s):
+@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 34.458
+
+ Requested Estimated Requested Estimated Clock Clock
+Starting Clock Frequency Frequency Period Period Slack Type Group
+----------------------------------------------------------------------------------------------------------------------
+vga|clk_pin 25.2 MHz 190.0 MHz 39.722 5.264 34.458 inferred Inferred_clkgroup_0
+======================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks | rise to rise | fall to fall | rise to fall | fall to rise
+-----------------------------------------------------------------------------------------------------------------
+Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
+-----------------------------------------------------------------------------------------------------------------
+vga|clk_pin vga|clk_pin | 39.722 34.458 | No paths - | No paths - | No paths -
+=================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+ 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information
+*********************
+
+ No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: vga|clk_pin
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[6] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_6 0.176 34.458
+dly_counter[0] vga|clk_pin stratix_lcell_ff regout dly_counter[0] 0.176 34.465
+dly_counter[1] vga|clk_pin stratix_lcell_ff regout dly_counter[1] 0.176 34.584
+vga_control_unit.toggle_counter_sig[5] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_5 0.176 34.585
+vga_driver_unit.vsync_counter[6] vga|clk_pin stratix_lcell_ff regout vsync_counter_6 0.176 34.836
+vga_driver_unit.vsync_counter[7] vga|clk_pin stratix_lcell_ff regout vsync_counter_7 0.176 34.865
+vga_control_unit.toggle_counter_sig[8] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_8 0.176 34.921
+vga_driver_unit.vsync_counter[3] vga|clk_pin stratix_lcell_ff regout vsync_counter_3 0.176 34.992
+vga_driver_unit.vsync_counter[8] vga|clk_pin stratix_lcell_ff regout vsync_counter_8 0.176 34.992
+vga_control_unit.toggle_counter_sig[9] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_9 0.176 35.048
+======================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[0] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[1] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[2] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[3] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[4] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[5] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[6] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[7] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[8] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+vga_control_unit.toggle_counter_sig[9] vga|clk_pin stratix_lcell_ff sclr toggle_sig_0_0_0_g1 38.930 34.458
+====================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 39.722
+ - Setup time: 0.792
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 38.930
+
+ - Propagation time: 4.472
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (critical) : 34.458
+
+ Number of logic level(s): 6
+ Starting point: vga_control_unit.toggle_counter_sig[6] / regout
+ Ending point: vga_control_unit.toggle_counter_sig[0] / sclr
+ The start point is clocked by vga|clk_pin [rising] on pin clk
+ The end point is clocked by vga|clk_pin [rising] on pin clk
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------
+vga_control_unit.toggle_counter_sig[6] stratix_lcell_ff regout Out 0.176 0.176 -
+toggle_counter_sig_6 Net - - 1.000 - 4
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6 stratix_lcell dataa In - 1.176 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglt6 stratix_lcell combout Out 0.459 1.635 -
+un1_toggle_counter_siglt6 Net - - 0.376 - 1
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9 stratix_lcell datad In - 2.011 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto9 stratix_lcell combout Out 0.087 2.098 -
+un1_toggle_counter_siglto9 Net - - 0.376 - 1
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12 stratix_lcell datad In - 2.474 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto12 stratix_lcell combout Out 0.087 2.561 -
+un1_toggle_counter_siglto12 Net - - 0.376 - 1
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15 stratix_lcell datad In - 2.938 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto15 stratix_lcell combout Out 0.087 3.025 -
+un1_toggle_counter_siglto15 Net - - 0.376 - 1
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18 stratix_lcell datad In - 3.401 -
+vga_control_unit.BLINKER_next\.un1_toggle_counter_siglto18 stratix_lcell combout Out 0.087 3.488 -
+un1_toggle_counter_siglto18 Net - - 0.376 - 1
+vga_control_unit.toggle_sig_0_0_0_g1 stratix_lcell datad In - 3.864 -
+vga_control_unit.toggle_sig_0_0_0_g1 stratix_lcell combout Out 0.087 3.951 -
+toggle_sig_0_0_0_g1 Net - - 0.521 - 22(6)
+vga_control_unit.toggle_counter_sig[0] stratix_lcell_ff sclr In - 4.472 -
+=======================================================================================================================================
+Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.264 is 1.862(35.4%) logic and 3.402(64.6%) route.
+Fanout format: logic fanout (physical fanout)
+Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
+*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
+
+
+
+##### END OF TIMING REPORT #####]
+
+##### START OF AREA REPORT #####[
+Design view:work.vga(behav)
+Selecting part EP1S25F672C6
+@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
+
+I/O ATOMs: 117
+
+Total LUTs: 179 of 25660 ( 0%)
+Logic resources: 181 ATOMs of 25660 ( 0%)
+
+Number of I/O registers
+ Output DDRs :0
+
+ATOM count by mode:
+ normal: 128
+ arithmetic: 53
+
+DSP Blocks: 0 (0 nine-bit DSP elements).
+DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
+ShiftTap: 0 (0 registers)
+MRAM: 0 (0% of 2)
+M4Ks: 0 (0% of 138)
+M512s: 0 (0% of 224)
+Total ESB: 0 bits
+
+ATOMs using regout pin: 88
+ also using enable pin: 12
+ also using combout pin: 1
+ATOMs using combout pin: 91
+Number of Inputs on ATOMs: 760
+Number of Nets: 54954
+
+##### END OF AREA REPORT #####]
+
+Mapper successful!
+Process took 0h:00m:05s realtime, 0h:00m:04s cputime
+# Wed Oct 21 17:26:36 2009
+
+###########################################################]
--- /dev/null
+%%% protect protected_file
+@E
+@
+#
+#
+#
+# Created by Synplify VHDL Compiler version comp400rc, Build 020R from Synplicity, Inc.
+# Copyright 1994-2009 Synopsys, Inc. , All rights reserved.
+# Synthesis Netlist written on Wed Oct 21 17:23:09 2009
+#
+#
+#OPTIONS:"|-top|vga|-infer_seqShift|-primux|-fixsmult|-dspmac|-nram|-divnmod|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"/opt/synplify/fpga_c200906/linux/c_vhdl":1242928055
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/location.map":1242864830
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":1242776237
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":1255952276
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd":1242776237
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd":1242776237
+#CUR:"/opt/synplify/fpga_c200906/lib/vhd/arith.vhd":1242776237
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":1256135047
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd":1256135072
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd":1255952276
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd":1256138582
+#CUR:"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd":1256135040
+f "/opt/synplify/fpga_c200906/lib/vhd/std.vhd"; # file 0
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd"; # file 1
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd"; # file 2
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd"; # file 3
+af .is_vhdl 1;
+f "/opt/synplify/fpga_c200906/lib/vhd/arith.vhd"; # file 4
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd"; # file 5
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd"; # file 6
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd"; # file 7
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd"; # file 8
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd"; # file 9
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd"; # file 10
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd"; # file 11
+af .is_vhdl 1;
+f "/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd"; # file 12
+af .is_vhdl 1;
+@E
+@
+ftell;
+@E@MR@dn:n::(d4n:UFRIsL RF8Ns_H8sPRCsLNCEPN;
+PHR3#8PED;R4
+RNP3_H#PDE8R
+4;N3PRFosHhCNlRF"LN_s88PsHC;s"
+RNP#_$Mb#sCCCsPR
+4;
+@HR@dn:g::Ud4g:.CRs#RC0sCC#0N;
+HsR30FD_sMHoNRlC"#sCC;0"
+@FR@cn:j::Uc4j:nCR#P_CM#rCo4jd:9sR0k8C,H0oH_VDC09rj,o8HHD0_CrV0j89,H0oH_VDC09rj,o8HHD0_CrV0j89,H0oH_VDC09rj,o8HHD0_CrV0j09,s,kC0Csk,k0sCs,0k8C,H0oH_VDC09rj,o8HHD0_CrV0j09,s;kC
+RNH3Ds0_HFsolMNC#R"CMPC_o#C"b;
+Rj@@:44::.4:Rk0sCsR0k0CRs;kC
+@bR@4j::44::V.RNCD#RDVN#VCRNCD#;R
+b@j@4::ndcd:n:l6Rk8GRH0oH_VDC09rjRo8HHD0_CrV0j09RsRkCV#NDCCRs#;C0
+-y---------------------------------
+
+@
+ftell;
+@E@MR@dU:(::(d4(:nFRIsP Ro8N_sCHPsCRLE;NP
+RNP3PH#ER8D4N;
+PHR3#E_P84DR;P
+NRs3FHNohl"CRP_oN8PsHC;s"
+RNP#_$Mb#sCCCsPR
+4;
+@HR@dU:U::(dgU:R ODR OD;H
+NR03sDs_FHNoMl"CRO"D ;
+
+
+
+@HR@dU:g::(d4g:4CRs#RC0sCC#0N;
+HsR30FD_sMHoNRlC"#sCC;0"
+@FR@cU:j::(c.j:jFRODMkl_kOFMs0Crjg:9FRODMkl_kOFMs0C_o#Hrjg:9N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0"Cs;
+
+
+
+@FR@cU:4::(c44:UHRDMOC_F0kMCUsr:Rj9DCHM_kOFMs0C_o#HrjU:9N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0s
+";
+@FR@cU:.::(c4.:c_RECLMNDECR_NCML_DC#;Ho
+RNH3Ds0_HFsolMNCER"_NCML"DC;
+
+
+
+@FR@cU:d::(c4d:c_RPCLMNDPCR_NCML_DC#;Ho
+RNH3Ds0_HFsolMNCPR"_NCML"DC;
+
+
+
+@FR@cU:c::(c4c:4#RE$RMOE$_#M
+O;N3HRs_0DFosHMCNlR#"E$"MO;
+
+
+
+@FR@cU:cc:4::cc4PUR#O$MR#P_$;MO
+RNH3Ds0_HFsolMNCPR"#O$M"
+;
+
+@FR@cU:n::(c4n:g_R8EM#$O0_#Nr0Cj9:nR$E#M#O_0CN0rnj:9N;
+HsR30FD_sMHoNRlC"E8_#O$M_N#00;C"
+@FR@cU:(::(c4(:g_R8PM#$O0_#Nr0Cj9:nR$P#M#O_0CN0rnj:9N;
+HsR30FD_sMHoNRlC"P8_#O$M_N#00;C"
+@FR@cU:U::(c.U:4_R8EM#$OF_OkCM0s:rgjE9R#O$M_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"E8_#O$M_kOFMs0C"
+;
+
+@FR@cU:g::(c.g:4_R8PM#$OF_OkCM0s:rgjP9R#O$M_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"P8_#O$M_kOFMs0C"
+;
+
+@FR@6U:j::(6.j:6_R8#_C0EM#$OF_OkCM0s_R8#_C0EM#$OF_OkCM0sN;
+HsR30FD_sMHoNRlC"#8_CE0_#O$M_kOFMs0C"
+;
+
+@FR@6U:4::(6.4:6_R8#_C0PM#$OF_OkCM0s_R8#_C0PM#$OF_OkCM0sN;
+HsR30FD_sMHoNRlC"#8_CP0_#O$M_kOFMs0C"
+;
+
+@FR@6U:.::(6..:n_R8#_C0OkFDlOM_F0kMC8sR_0#C_DOFk_lMOMFk0;Cs
+RNH3Ds0_HFsolMNC8R"_0#C_DOFk_lMOMFk0"Cs;
+
+
+
+@FR@6U:d::(6.d:c_R8#_C0DCHM_kOFMs0CR#8_CD0_H_MCOMFk0;Cs
+RNH3Ds0_HFsolMNC8R"_0#C_MDHCF_OkCM0s
+";b@R@Ug:d:d(:g4:4RPHMR4kM_#sCCk0RMs4_C0#CR#sCC
+0;b@R@4..:j4j:gj:.j6:.RPHMR4kM_$E#MOO_F0kMCjsr9MRk4#_E$_MOOMFk0rCsjE9R#O$M_kOFMs0Cr;j9
+@bR@:4..:jj4.g:j.j:6MRHPMRk4#_E$_MOOMFk0rCsg9:.R4kM_$E#MOO_F0kMCgsr:R.9EM#$OF_OkCM0s:rg.
+9;b@R@4..:c4d:Uc:.dc:.RPHMR4kM_$E#M#O_0CN0r6.:9MRk4#_E$_MO#00NC:r.6E9R#O$M_N#00.Cr:;69
+@bR@:4..:cUcc:.UR:(LRkV8C_#0F_ODMkl_kOFMs0CR#8_CO0_FlDkMF_OkCM0s#RE$_MO#00NC9r4;R
+b@.@4:U.c:.c:c(U:RPHMRDOFk_lMOMFk0_CsM0CG4OjRFlDkMF_OkCM0sC_MGj04R$E#M#O_0CN0r;49
+@bR@:4.d:4d4dg:4.d:6MRHPMRk4#_P$_MOOMFk0rCsg9:jR4kM_$P#MOO_F0kMCgsr:Rj9PM#$OF_OkCM0s:rgj
+9;b@R@4d.:64n:U6:dnc:.RPHMR4kM_$P#M#O_0CN0r6.:9MRk4#_P$_MO#00NC:r.6P9R#O$M_N#00.Cr:;69
+@bR@:4.d:n4cn:d4R:(LRkV8C_#0H_DMOC_F0kMC8sR_0#C_MDHCF_OkCM0s#RP$_MO#00NC9r4;R
+b@.@4:4dn:dc:n(4:RPHMRMDHCF_OkCM0sC_MGd04RMDHCF_OkCM0sC_MGd04R$P#M#O_0CN0r;49
+@bR@4j::44::0.RsRkC0CskRk0sCb;
+Rj@@:44::.4:RDVN#VCRNCD#RDVN#
+C;b@R@4g.:(::cg6(:R8NMP#RE$_MO#00NCC_MGc0__l#JkRGNEM#$O0_#N_0CM0CG_#c_JGlkNCRs#
+C0RRRREM#$O0_#Nr0C4
+9;b@R@4g.:(::cg6(:R8NMP#RP$_MO#00NCC_MGc0__l#JkRGNPM#$O0_#N_0CM0CG_#c_JGlkNCRs#
+C0RRRRPM#$O0_#Nr0C4
+9;b@R@44.:j(U::U4j:RddNPM8RDOFk_lMOMFk0_CsM0CG_#j_JGlkNFRODMkl_kOFMs0C_GMC0__j#kJlGRN
+RsRRC0#CR$E#M#O_0CN0r;49
+@bR@:4.4:dn(d:4n4:dR8NMPHRDMOC_F0kMCMs_C_G0jJ_#lNkGRMDHCF_OkCM0sC_MGj0__l#Jk
+GNRRRRsCC#0#RP$_MO#00NC9r4;R
+b@.@4:n.j:.c:j(n:RPFsR4kM_$E#M#O_0CN0_k4RME4_#O$M_N#004C_R$E#M#O_0CN0rRn9EM#$O0_#Nr0Cj
+9;b@R@4..:jcn::n.j:F(RskPRME4_#O$M_N#00.C_R4kM_$E#M#O_0CN0_E.R#O$M_N#00dCr9#RE$_MO#00NC9r4;R
+b@.@4:n.j:.c:j(n:RPFsR4kM_$E#M#O_0CN0_kdRME4_#O$M_N#00dC_R$E#M#O_0CN0rR49EM#$O0_#Nr0CdR9
+RERR#O$M_N#00.Cr9b;
+R4@@.j:.n::c.:jn(sRFPMRk4#_E$_MO#00NCR_ck_M4EM#$O0_#N_0Cc#RE$_MO#00NC9r6R$E#M#O_0CN0r;c9
+@bR@:4.d:4gc4:dgR:(FRsPk_M4PM#$O0_#N_0C4MRk4#_P$_MO#00NCR_4PM#$O0_#Nr0CnP9R#O$M_N#00jCr9b;
+R4@@.4:dg::cd:4g(sRFPMRk4#_P$_MO#00NCR_.k_M4PM#$O0_#N_0C.#RP$_MO#00NC9r4R$P#M#O_0CN0r
+d9RRRRPM#$O0_#Nr0C.
+9;b@R@4d.:4cg::gd4:F(RskPRMP4_#O$M_N#00dC_R4kM_$P#M#O_0CN0_PdR#O$M_N#00dCr9#RP$_MO#00NC9r4;R
+b@.@4:gd4:dc:4(g:RPFsR4kM_$P#M#O_0CN0_kcRMP4_#O$M_N#00cC_R$P#M#O_0CN0rR69PM#$O0_#Nr0Cc
+9;b@R@44.:j(U::U4j:RddNPM8RDOFk_lMOMFk0_CsM0CG_#4_JGlkNFRODMkl_kOFMs0C_GMC0__4#kJlGRN
+RsRRC0#CRDOFk_lMOMFk0_CsM0CG4
+j;b@R@44.:d(n::n4d:Rd4NPM8RMDHCF_OkCM0sC_MG40__l#JkRGNDCHM_kOFMs0C_GMC0__4#kJlGRN
+RsRRC0#CRMDHCF_OkCM0sC_MGd04;R
+b@.@4:n.j:.c:j(n:RPHMR4kM_$E#M#O_0CN0_k6RME4_#O$M_N#006C_R4kM_$E#M#O_0CN0_
+c;b@R@4..:jcn::n.j:H(RMkPRME4_#O$M_N#00nC_R4kM_$E#M#O_0CN0_knRME4_#O$M_N#00dC_;R
+b@.@4:gd4:dc:4(g:RPHMR4kM_$P#M#O_0CN0_k6RMP4_#O$M_N#006C_R4kM_$P#M#O_0CN0_
+c;b@R@4d.:4cg::gd4:H(RMkPRMP4_#O$M_N#00nC_R4kM_$P#M#O_0CN0_knRMP4_#O$M_N#00.C_;R
+b@.@4:(4U:4c:U6(:RV#8VRsCPM_CNCLD_o#HRCP_MDNLCH_#oMRk4#_E$_MO#00NCR_.ORD k_M4sCC#0R
+RRMRk4#_E$_MO#00NC;_6
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlR_"PCLMND#C_H;o"
+@bR@:4..:cUgc:.Ug:4R8NMP1R]Y_hBw_1vF\k034kM_$E#M#O_0CN0RY]1hwB_1Fv_k30\k_M4EM#$O0_#N
+0CRRRRk_M4EM#$O0_#Nr0C6k9RME4_#O$M_N#00cCr9MRk4#_E$_MO#00NC9rdR4kM_$E#M#O_0CN0r;.9
+@bR@:4.d:jjcj:djR:6#V8VsECR_NCML_DC#RHoEM_CNCLD_o#HR4kM_$P#M#O_0CN0_OdRDk RMs4_C0#C
+RRRR4kM_$P#M#O_0CN0_
+6;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"CE_MDNLCH_#o
+";b@R@4d.:ng4::4dn:R4gNPM8RYe1hwB_1Fv_k30\k_M4PM#$O0_#NR0Ceh1YB1_wvk_F0k\3MP4_#O$M_N#00RC
+RkRRMP4_#O$M_N#006Cr9MRk4#_P$_MO#00NC9rcR4kM_$P#M#O_0CN0rRd9k_M4PM#$O0_#Nr0C.
+9;b@R@4g.:(::cg6(:R8NMP#RE$_MO#00NCC_MGj0__l#JkRGNEM#$O0_#N_0CM0CG_#j_JGlkNCRs#
+C0RRRRk_M4EM#$O0_#N_0C4b;
+R4@@.(:g:gc:(R:6NPM8R$P#M#O_0CN0_GMC0__j#kJlGPNR#O$M_N#00MC_C_G0jJ_#lNkGR#sCCR0
+RkRRMP4_#O$M_N#004C_;R
+b@.@4:U.c:.g:c4U:gMRHPCR#0#_E$_MOOMFk0(CsR0#C_$E#MOO_F0kMCRs(]h1YB1_wvk_F0k\3ME4_#O$M_N#00
+C;b@R@4d.:ng4::4dn:R4gHRMP#_C0PM#$OF_OkCM0s#(RCP0_#O$M_kOFMs0C(1ReY_hBw_1vF\k034kM_$P#M#O_0CN0;R
+b@.@4:d.4::44.:4ddN.RMR8P]h1YB1_wvC_MG30\kjM4_$E#MOO_F0kMC]sR1BYh_vw1_GMC0k\3M_4jEM#$OF_OkCM0sR
+RRMRk4#_E$_MOOMFk0rCsjE9R#O$M_kOFMs0CrR49k_M4EM#$OF_OkCM0s9r.
+RRRR$E#MOO_F0kMCdsr9#RE$_MOOMFk0rCsck9RME4_#O$M_kOFMs0CrR69EM#$OF_OkCM0s9rn
+RRRR4kM_$E#MOO_F0kMC(sr9MRk4#_E$_MOOMFk0rCsUk9RME4_#O$M_kOFMs0Cr;g9
+@bR@:4..:4U4.4:4dU:dMRN8]PR1BYh_vw1_GMC0k\3M_44EM#$OF_OkCM0s1R]Y_hBw_1vM0CG\M3k4E4_#O$M_kOFMs0C
+RRRR$E#MOO_F0kMCjsr9#RE$_MOOMFk0rCs4E9R#O$M_kOFMs0CrR.9k_M4EM#$OF_OkCM0s9rd
+RRRR4kM_$E#MOO_F0kMCcsr9MRk4#_E$_MOOMFk0rCs6k9RME4_#O$M_kOFMs0Cr
+n9RRRREM#$OF_OkCM0s9r(R4kM_$E#MOO_F0kMCUsr9MRk4#_E$_MOOMFk0rCsg
+9;b@R@4..:.4n:4.:.nc:dR8NMP1R]Y_hBw_1vM0CG\M3k4E._#O$M_kOFMs0CRY]1hwB_1Mv_C\G034kM.#_E$_MOOMFk0
+CsRRRREM#$OF_OkCM0s9rjR$E#MOO_F0kMC4sr9#RE$_MOOMFk0rCs.k9RME4_#O$M_kOFMs0Cr
+d9RRRRk_M4EM#$OF_OkCM0s9rcR4kM_$E#MOO_F0kMC6sr9MRk4#_E$_MOOMFk0rCsnR9
+RkRRME4_#O$M_kOFMs0CrR(9EM#$OF_OkCM0s9rUR$E#MOO_F0kMCgsr9b;
+R4@@.d:.44:4:4.d:Rd.NPM8RY]1hwB_1Mv_C\G034kMd#_E$_MOOMFk0RCs]h1YB1_wvC_MG30\kdM4_$E#MOO_F0kMCRs
+RERR#O$M_kOFMs0CrRj9EM#$OF_OkCM0s9r4R$E#MOO_F0kMC.sr9#RE$_MOOMFk0rCsdR9
+RERR#O$M_kOFMs0CrRc9k_M4EM#$OF_OkCM0s9r6R4kM_$E#MOO_F0kMCnsr9R
+RRMRk4#_E$_MOOMFk0rCs(E9R#O$M_kOFMs0CrRU9EM#$OF_OkCM0s9rg;R
+b@.@4:nd.::44d:.ndN.RMR8Peh1YB1_wvC_MG30\k.M4_$P#MOO_F0kMCesR1BYh_vw1_GMC0k\3M_4.PM#$OF_OkCM0sR
+RR#RP$_MOOMFk0rCsjk9RMP4_#O$M_kOFMs0CrR49k_M4PM#$OF_OkCM0s9r.
+RRRR4kM_$P#MOO_F0kMCdsr9MRk4#_P$_MOOMFk0rCsck9RMP4_#O$M_kOFMs0Cr
+69RRRRk_M4PM#$OF_OkCM0s9rnR4kM_$P#MOO_F0kMC(sr9MRk4#_P$_MOOMFk0rCsUR9
+RkRRMP4_#O$M_kOFMs0Cr;g9
+@bR@:4.d:d44d4:dd4:dMRN8ePR1BYh_vw1_GMC0k\3M_4dPM#$OF_OkCM0s1ReY_hBw_1vM0CG\M3k4Pd_#O$M_kOFMs0C
+RRRR$P#MOO_F0kMCjsr9MRk4#_P$_MOOMFk0rCs4k9RMP4_#O$M_kOFMs0Cr
+.9RRRRk_M4PM#$OF_OkCM0s9rdR4kM_$P#MOO_F0kMCcsr9#RP$_MOOMFk0rCs6R9
+RkRRMP4_#O$M_kOFMs0CrRn9k_M4PM#$OF_OkCM0s9r(R4kM_$P#MOO_F0kMCUsr9R
+RRMRk4#_P$_MOOMFk0rCsg
+9;b@R@4d.:d4g:4d:dgc:dR8NMP1ReY_hBw_1vM0CG\M3k4Pc_#O$M_kOFMs0CRYe1hwB_1Mv_C\G034kMc#_P$_MOOMFk0
+CsRRRRPM#$OF_OkCM0s9rjR4kM_$P#MOO_F0kMC4sr9MRk4#_P$_MOOMFk0rCs.R9
+RkRRMP4_#O$M_kOFMs0CrRd9k_M4PM#$OF_OkCM0s9rcR4kM_$P#MOO_F0kMC6sr9R
+RRMRk4#_P$_MOOMFk0rCsnk9RMP4_#O$M_kOFMs0CrR(9k_M4PM#$OF_OkCM0s9rU
+RRRR$P#MOO_F0kMCgsr9b;
+R4@@.c:dc4:4:cdc:Rd.NPM8RYe1hwB_1Mv_C\G034kM6#_P$_MOOMFk0RCseh1YB1_wvC_MG30\k6M4_$P#MOO_F0kMCRs
+RkRRMP4_#O$M_kOFMs0CrRj9k_M4PM#$OF_OkCM0s9r4R4kM_$P#MOO_F0kMC.sr9R
+RR#RP$_MOOMFk0rCsdk9RMP4_#O$M_kOFMs0CrRc9k_M4PM#$OF_OkCM0s9r6
+RRRR4kM_$P#MOO_F0kMCnsr9MRk4#_P$_MOOMFk0rCs(k9RMP4_#O$M_kOFMs0Cr
+U9RRRRPM#$OF_OkCM0s9rg;R
+b@.@4:d.4::44.:4ddH.RMEPR#O$M_N#00MC_C6G0R$E#M#O_0CN0_GMC0]6R1BYh_vw1_GMC0k\3M_4jEM#$OF_OkCM0sb;
+R4@@.4:.U4:4:U.4:RddHRMPEM#$O0_#N_0CM0CGg#RE$_MO#00NCC_MGR0g]h1YB1_wvC_MG30\k4M4_$E#MOO_F0kMC
+s;b@R@4..:.4n:4.:.nc:dRPHMR$E#M#O_0CN0_GMC0R4cEM#$O0_#N_0CM0CG4]cR1BYh_vw1_GMC0k\3M_4.EM#$OF_OkCM0sb;
+R4@@.d:.44:4:4.d:Rd.HRMPEM#$O0_#N_0CM0CG4EUR#O$M_N#00MC_C4G0U1R]Y_hBw_1vM0CG\M3k4Ed_#O$M_kOFMs0C;R
+b@.@4:nd.::44d:.ndH.RMPPR#O$M_N#00MC_C6G0R$P#M#O_0CN0_GMC0e6R1BYh_vw1_GMC0k\3M_4.PM#$OF_OkCM0sb;
+R4@@.d:d44:4:4dd:RddHRMPPM#$O0_#N_0CM0CGg#RP$_MO#00NCC_MGR0geh1YB1_wvC_MG30\kdM4_$P#MOO_F0kMC
+s;b@R@4d.:d4g:4d:dgc:dRPHMR$P#M#O_0CN0_GMC0R4cPM#$O0_#N_0CM0CG4ecR1BYh_vw1_GMC0k\3M_4cPM#$OF_OkCM0sb;
+R4@@.c:dc4:4:cdc:Rd.HRMPPM#$O0_#N_0CM0CG4PUR#O$M_N#00MC_C4G0U1ReY_hBw_1vM0CG\M3k4P6_#O$M_kOFMs0C;R
+b@.@4::g(c(:g:N6RMR8PEM#$O0_#N_0CM0CG_#4_JGlkN#RE$_MO#00NCC_MG40__l#JkRGNsCC#0R
+RR#RE$_MO#00NC9r6RY]1hwB_1Mv_C\G034kMj#_E$_MOOMFk0;Cs
+@bR@:4.gc(:::g(6MRN8EPR#O$M_N#00MC_C_G0dJ_#lNkGR$E#M#O_0CN0_GMC0__d#kJlGsNRC0#C
+RRRR$E#M#O_0CN0rRc9]h1YB1_wvC_MG30\k4M4_$E#MOO_F0kMC
+s;b@R@4g.:(::cg6(:R8NMP#RE$_MO#00NCC_MG60__l#JkRGNEM#$O0_#N_0CM0CG_#6_JGlkNCRs#
+C0RRRREM#$O0_#Nr0Cd]9R1BYh_vw1_GMC0k\3M_4.EM#$OF_OkCM0sb;
+R4@@.(:g:gc:(R:6NPM8R$E#M#O_0CN0_GMC0__n#kJlGENR#O$M_N#00MC_C_G0nJ_#lNkGR#sCCR0
+RERR#O$M_N#00.Cr91R]Y_hBw_1vM0CG\M3k4Ed_#O$M_kOFMs0C;R
+b@.@4::g(c(:g:N6RMR8PPM#$O0_#N_0CM0CG_#4_JGlkN#RP$_MO#00NCC_MG40__l#JkRGNsCC#0R
+RR#RP$_MO#00NC9r6RYe1hwB_1Mv_C\G034kM.#_P$_MOOMFk0;Cs
+@bR@:4.gc(:::g(6MRN8PPR#O$M_N#00MC_C_G0dJ_#lNkGR$P#M#O_0CN0_GMC0__d#kJlGsNRC0#C
+RRRR$P#M#O_0CN0rRc9eh1YB1_wvC_MG30\kdM4_$P#MOO_F0kMC
+s;b@R@4g.:(::cg6(:R8NMP#RP$_MO#00NCC_MG60__l#JkRGNPM#$O0_#N_0CM0CG_#6_JGlkNCRs#
+C0RRRRPM#$O0_#Nr0Cde9R1BYh_vw1_GMC0k\3M_4cPM#$OF_OkCM0sb;
+R4@@.(:g:gc:(R:6NPM8R$P#M#O_0CN0_GMC0__n#kJlG3N\PM#$O0_#N_0CM0CG_#n_JGlkN#RP$_MO#00NCC_MGn0__l#Jk\GN3$P#M#O_0CN0_GMC0__n#kJlGRN
+RPRR#O$M_N#00.Cr91ReY_hBw_1vM0CG\M3k4P6_#O$M_kOFMs0C;R
+b@.@4::g(c(:g:N6RMR8PPM#$O0_#N_0CM0CG_#n_JGlkN#RP$_MO#00NCC_MGn0__l#JkRGNsCC#0R
+RR#RP$_MO#00NC9r.RYe1hwB_1Mv_C\G034kM6#_P$_MOOMFk0;Cs
+@bR@:4.4:44g4:444:cRRD0BzmpvBh_mazh_GMC0k\3M_4jOkFDlOM_F0kMC#s_HBoRmvpzhm_Bz_haM0CG\M3k4Oj_FlDkMF_OkCM0sH_#oR
+RRFRODMkl_kOFMs0C_o#Hrjg:9sR0kVC,NCD#,DVN#0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCb;
+R4@@.d:4g::g4:dgcDjR0QRphB _mazh_GMC0k\3M_4jDCHM_kOFMs0C_o#HRhpQ m_Bz_haM0CG\M3k4Dj_H_MCOMFk0_Cs#
+HoRRRRDCHM_kOFMs0C_o#HrjU:9sR0k0C,s,kC0Csk,DVN#0C,s,kC0Csk,k0sCs,0k0C,s;kC
+@bR@:4.4:(.g(:4.n:dRRD0]h1YBm_Bz_haM0CG\M3kg#_E$_MOOMFk0RCs]h1YBm_Bz_haM0CG\M3kg#_E$_MOOMFk0
+CsRRRREM#$OF_OkCM0s:rgj09Rs,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk;R
+b@.@4:d.4::44.:4ddN.RMR8PEM#$O0_#N_0CM0CG_#4_JGlkNR_4EM#$O0_#N_0CM0CG_#4_JGlkN
+_4RRRREM#$O0_#Nr0C6E9R#O$M_N#00MC_C6G0;R
+b@.@4:U.4::44.:4UdNdRMR8PEM#$O0_#N_0CM0CG_#4_JGlkNR_.EM#$O0_#N_0CM0CG_#4_JGlkN
+_.RRRREM#$O0_#Nr0CcE9R#O$M_N#00MC_CgG0;R
+b@.@4:n..::44.:.ndNcRMR8PEM#$O0_#N_0CM0CG_#4_JGlkNR_dEM#$O0_#N_0CM0CG_#4_JGlkN
+_dRRRREM#$O0_#Nr0CdE9R#O$M_N#00MC_C4G0cb;
+R4@@.d:.44:4:4.d:Rd.NPM8R$E#M#O_0CN0_GMC0__4#kJlGcN_R$E#M#O_0CN0_GMC0__4#kJlGcN_
+RRRR$E#M#O_0CN0rR.9EM#$O0_#N_0CM0CG4
+U;b@R@4..:Ug4::4.U:RdnDe0R1BYh_zBmhMa_C\G03gkM_$P#MOO_F0kMCesR1BYh_zBmhMa_C\G03gkM_$P#MOO_F0kMCRs
+RPRR#O$M_kOFMs0Crjg:9sR0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s;kC
+@bR@:4.d:.n4d4:.dn:.MRN8PPR#O$M_N#00MC_C_G04J_#lNkG_P4R#O$M_N#00MC_C_G04J_#lNkG_R4
+RPRR#O$M_N#006Cr9#RP$_MO#00NCC_MG;06
+@bR@:4.d:d44d4:dd4:dMRN8PPR#O$M_N#00MC_C_G04J_#lNkG_P.R#O$M_N#00MC_C_G04J_#lNkG_R.
+RPRR#O$M_N#00cCr9#RP$_MO#00NCC_MG;0g
+@bR@:4.d:dg4d4:ddg:cMRN8PPR#O$M_N#00MC_C_G04J_#lNkG_PdR#O$M_N#00MC_C_G04J_#lNkG_Rd
+RPRR#O$M_N#00dCr9#RP$_MO#00NCC_MGc04;R
+b@.@4:cdc::44d:ccdN.RMR8PPM#$O0_#N_0CM0CG_#4_JGlkNR_cPM#$O0_#N_0CM0CG_#4_JGlkN
+_cRRRRPM#$O0_#Nr0C.P9R#O$M_N#00MC_C4G0Ub;
+R4@@.4:44::g4:44cH4RMOPRFlDkMF_OkCM0sC_MGR0(OkFDlOM_F0kMCMs_C(G0RpBmz_vhBhmzaC_MG30\kjM4_DOFk_lMOMFk0_Cs#;Ho
+@bR@:4.4:dggd:4gj:cRPHMRMDHCF_OkCM0sC_MGj04RMDHCF_OkCM0sC_MGj04RhpQ m_Bz_haM0CG\M3k4Dj_H_MCOMFk0_Cs#;Ho
+@bR@:4.4:(.g(:4.n:dRPHMR$E#MOO_F0kMCMs_C(G0R$E#MOO_F0kMCMs_C(G0RY]1hBB_mazh_GMC0k\3MEg_#O$M_kOFMs0C;R
+b@.@4:4.U:.g:Ud4:nMRHP#RP$_MOOMFk0_CsM0CG4PjR#O$M_kOFMs0C_GMC0R4jeh1YBm_Bz_haM0CG\M3kg#_P$_MOOMFk0;Cs
+@bR@:4.4:44g4:444:cR8NMPFRODMkl_kOFMs0C_GMC0__j#kJlG4N_RDOFk_lMOMFk0_CsM0CG_#j_JGlkN
+_4RRRRBzmpvBh_mazh_GMC0k\3M_4jOkFDlOM_F0kMC#s_HOoRFlDkMF_OkCM0sC_MG40__l#Jk;GN
+@bR@:4.4:4.d44:46.:c8RN8MRk.F_ODMkl_kOFMs0C_GMC0:rgjk9RMO._FlDkMF_OkCM0sC_MGg0r:
+j9RRRROkFDlOM_F0kMC#s_Hgor:Rj90Csk;R
+b@.@4:g4d:4g:dcg:jMRN8DPRH_MCOMFk0_CsM0CG_#j_JGlkNR_4DCHM_kOFMs0C_GMC0__j#kJlG4N_
+RRRRhpQ m_Bz_haM0CG\M3k4Dj_H_MCOMFk0_Cs#RHoDCHM_kOFMs0C_GMC0__4#kJlG
+N;b@R@44.:(dd:j(:4dU:cR8N8R.kM_$E#MOO_F0kMCMs_CrG0g9:jR.kM_$E#MOO_F0kMCMs_CrG0g9:j
+RRRR$E#MOO_F0kMCgsr:Rj90Csk;R
+b@.@4:U.c:.c:c(U:RkblG_R8#_C0EM#$OF_OkCM0s_R8#_C0EM#$OF_OkCM0ssR0kEC,#O$M_N#00nCr9R
+RRNRVD,#CEM#$O0_#Nr0C409Rs,kCEM#$O0_#Nr0CjV9RNCD#,0#C_$E#MOO_F0kMC;s(
+@bR@:4.d:n4cn:d4R:(bGlkR#8_CP0_#O$M_kOFMs0CR#8_CP0_#O$M_kOFMs0CRk0sC#,P$_MO#00NC9rn
+RRRRDVN#PC,#O$M_N#004Cr9sR0kPC,#O$M_N#00jCr9NRVD,#C#_C0PM#$OF_OkCM0s
+(;b@R@44.:4g4::444:Rc4NPM8RDOFk_lMOMFk0_CsM0CG_#4_JGlkNR_4OkFDlOM_F0kMCMs_C_G04J_#lNkG_R4
+RORRFlDkMF_OkCM0sC_MGR0(OkFDlOM_F0kMCMs_C_G04J_#lNkG;R
+b@.@4:g4d:4g:dcg:jMRN8DPRH_MCOMFk0_CsM0CG_#4_JGlkNR_4DCHM_kOFMs0C_GMC0__4#kJlG4N_
+RRRRMDHCF_OkCM0sC_MGj04RMDHCF_OkCM0sC_MG40__l#Jk;GN
+@bR@:4..:cUcc:.UR:(HRMPk4M4_$P#MOO_F0kMCksRM_44PM#$OF_OkCM0s_R8#_C0EM#$OF_OkCM0sb;
+R4@@.n:d4::cd:n4(MRHP#RP$_MOOMFk0_CsM0CG4PdR#O$M_kOFMs0C_GMC0R4d8C_#0#_P$_MOOMFk0;Cs
+@bR@:4..:jncj:.nR:(FRsPk_M4EM#$O0_#N_0CM0CG_#4_JGlkNMRk4#_E$_MO#00NCC_MG40__l#Jk
+GNRRRREM#$O0_#N_0CM0CG_#4_JGlkNR_4EM#$O0_#N_0CM0CG_#4_JGlkNR_.EM#$O0_#N_0CM0CG_#4_JGlkN
+_dRRRREM#$O0_#N_0CM0CG_#4_JGlkN;_c
+@bR@:4.d:4gc4:dgR:(FRsPk_M4PM#$O0_#N_0CM0CG_#4_JGlkNMRk4#_P$_MO#00NCC_MG40__l#Jk
+GNRRRRPM#$O0_#N_0CM0CG_#4_JGlkNR_4PM#$O0_#N_0CM0CG_#4_JGlkNR_.PM#$O0_#N_0CM0CG_#4_JGlkN
+_dRRRRPM#$O0_#N_0CM0CG_#4_JGlkN;_c
+@bR@:4.4:ng(n:4g.:dR8NMP#RE$_MOOMFk0_CsM0CG_#j_JGlkN#RE$_MOOMFk0_CsM0CG_#j_JGlkNR
+RRCRs#RC08C_#0#_E$_MOOMFk0;Cs
+@bR@:4..:(U((:.U.:dR8NMP#RP$_MOOMFk0_CsM0CG_#j_JGlkN#RP$_MOOMFk0_CsM0CG_#j_JGlkNR
+RRCRs#RC08C_#0#_P$_MOOMFk0;Cs
+@bR@:4.4:ng(n:4g.:dR8NMP#RE$_MOOMFk0_CsM0CG_#4_JGlkN#RE$_MOOMFk0_CsM0CG_#4_JGlkNR
+RRCRs#RC0k4M4_$P#MOO_F0kMC
+s;b@R@4..:((U::U.(:Rd.NPM8R$P#MOO_F0kMCMs_C_G04J_#lNkGR$P#MOO_F0kMCMs_C_G04J_#lNkG
+RRRR#sCCP0R#O$M_kOFMs0C_GMC0;4d
+@bR@:4.gc(:::g(6MRN8EPR#O$M_N#00MC_C_G0.J_#lNkGR$E#M#O_0CN0_GMC0__.#kJlGsNRC0#C
+RRRR4kM_$E#M#O_0CN0_GMC0__4#kJlG
+N;b@R@4g.:(::cg6(:R8NMP#RP$_MO#00NCC_MG.0__l#JkRGNPM#$O0_#N_0CM0CG_#._JGlkNCRs#
+C0RRRRk_M4PM#$O0_#N_0CM0CG_#4_JGlkNb;
+R4@@.j:d4::nd:j4(sRFPMRk4#_P$_MO#00NCC_MG40__l#Jk_GN4MRk4#_P$_MO#00NCC_MG40__l#Jk_GN4R
+RRMRk4#_P$_MO#00NCC_MG40__l#JkRGNPM#$O0_#N_0CM0CG_#n_JGlkNP\3#O$M_N#00MC_C_G0nJ_#lNkG;R
+b@.@4:U4U:4n:U(U:RkblG#RE$_MO#00NCM_O#j0r:R69EM#$O0_#N_0CO0M#r6j:9NRVD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCM,k4C_s#
+C0RRRRV#NDCN,VD,#CV#NDCN,VD,#CV#NDCs,0kEC,#O$M_N#00MC_C_G0jJ_#lNkGRDVN#VC,NCD#,DVN#VC,NCD#,k0sCN,VD,#CEM#$O0_#N_0CM0CG_#4_JGlkNR
+RRNRVD,#C0Csk,DVN#VC,NCD#,DVN#VC,NCD#,$E#M#O_0CN0_GMC0__d#kJlGVNRNCD#,DVN#VC,NCD#,k0sCN,VD,#CV#NDC#,E$_MO#00NCC_MGc0__l#Jk
+GNRRRRV#NDCN,VD,#C0Csk,DVN#VC,NCD#,DVN#EC,#O$M_N#00MC_C_G06J_#lNkGRk0sCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CEM#$O0_#N_0CM0CG_#n_JGlkNb;
+R4@@.j:dj::cd:jj6MRHPMRk4#_E$_MO#00NCC_MG.0__l#JkRGNk_M4EM#$O0_#N_0CM0CG_#._JGlkNR
+RR#RE$_MO#00NCC_MG.0__l#Jk;GN
+@bR@:4.d:jjcj:djR:6HRMPk_M4PM#$O0_#N_0CM0CG_#._JGlkNMRk4#_P$_MO#00NCC_MG.0__l#Jk
+GNRRRRPM#$O0_#N_0CM0CG_#._JGlkNb;
+R4@@.j:d4::nd:j4(lRbkPGR#O$M_N#00OC_Mr#0.9:6R$P#M#O_0CN0_#OM0:r.6V9RNCD#,DVN#VC,NCD#,DVN#kC,Ms4_C0#C
+RRRRDVN#VC,NCD#,DVN#0C,s,kCPM#$O0_#N_0CM0CG_#j_JGlkNNRVD,#CV#NDCs,0kVC,NCD#,$P#M#O_0CN0_GMC0__4#kJlGRN
+RVRRNCD#,DVN#VC,NCD#,DVN#PC,#O$M_N#00MC_C_G0dJ_#lNkGRDVN#0C,s,kCV#NDCN,VD,#CPM#$O0_#N_0CM0CG_#c_JGlkNR
+RRsR0kVC,NCD#,DVN#VC,NCD#,$P#M#O_0CN0_GMC0__6#kJlGVNRNCD#,DVN#VC,NCD#,DVN#PC,#O$M_N#00MC_C_G0nJ_#lNkG;R
+b@.@4:.4(:4g:(d.:nMRN8EPR#O$M_kOFMs0C_GMC0__j#kJlG4N_R$E#MOO_F0kMCMs_C_G0jJ_#lNkG_R4
+R]RR1BYh_zBmhMa_C\G03gkM_$E#MOO_F0kMCEsR#O$M_kOFMs0C_GMC0__4#kJlG
+N;b@R@44.:(g.::.4(:RdnNPM8R$E#MOO_F0kMCMs_C_G04J_#lNkG_E4R#O$M_kOFMs0C_GMC0__4#kJlG4N_
+RRRR$E#MOO_F0kMCMs_C(G0R$E#MOO_F0kMCMs_C_G04J_#lNkG;R
+b@.@4:4.U:.g:Ud4:nMRN8PPR#O$M_kOFMs0C_GMC0__j#kJlG4N_R$P#MOO_F0kMCMs_C_G0jJ_#lNkG_R4
+ReRR1BYh_zBmhMa_C\G03gkM_$P#MOO_F0kMCPsR#O$M_kOFMs0C_GMC0__4#kJlG
+N;b@R@4..:Ug4::4.U:RdnNPM8R$P#MOO_F0kMCMs_C_G04J_#lNkG_P4R#O$M_kOFMs0C_GMC0__4#kJlG4N_
+RRRR$P#MOO_F0kMCMs_C4G0j#RP$_MOOMFk0_CsM0CG_#4_JGlkNb;
+R4@@.j:d4::nd:j4(MRN8kPRMs4_C0#C_k4RMs4_C0#C_s4RC0#CR4kM_$P#M#O_0CN0_GMC0__4#kJlG4N_;R
+b@.@4::gUnU:g:b(RlRkGBzmpvBh_mazh_M#$\F3ODMkl_kOFMs0C_o#H_gdr:Rj9BzmpvBh_mazh_M#$\F3ODMkl_kOFMs0C_o#H_gdr:
+j9RRRRV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#Ck_M4sCC#0R
+RRNRVD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCF,ODMkl_kOFMs0C_GMC0__j#kJlGRN
+RkRRMO._FlDkMF_OkCM0sC_MGg0r:,j9OkFDlOM_F0kMCMs_C_G0jJ_#lNkG_R4
+R0RRs,kCV#NDCN,VD,#C0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0kOC,FlDkMF_OkCM0sC_MG40__l#Jk_GN4b;
+R4@@.j:d4::nd:j4(MRHPMRk4C_s#_C0.MRk4C_s#_C0.MRk4C_s#_C04b;
+R4@@.(:g:gc:(R:68RVVOkFDlOM_F0kMC#s_Hgor:Rj9OkFDlOM_F0kMC#s_Hgor:Rj9BzmpvBh_mazh_M#$\F3ODMkl_kOFMs0C_o#H_gdr:
+j9RRRRO;D
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRF"ODMkl_kOFMs0C_o#H"b;
+R4@@.U:4U::n4:UU(lRbkEGR#O$M_N#00dC_r6j:9#RE$_MO#00NCr_dj9:6R$E#M#O_0CN0r6j:9#,E$_MO#00NCC_MG.0__l#Jk
+GNRRRREM#$O0_#N_0CO0M#r6j:9M,k4#_E$_MO#00NCC_MG.0__l#Jk;GN
+@bR@:4.d:j4nj:d4R:(bGlkR$P#M#O_0CN0_.dr:R69PM#$O0_#N_0Cd:r.6P9R#O$M_N#00.Cr:,69PM#$O0_#N_0CM0CG_#._JGlkNR
+RR#RP$_MO#00NCM_O#.0r:,69k_M4PM#$O0_#N_0CM0CG_#._JGlkNb;
+R4@@.c:444:d:44c:R6.NR88k_M4DCHM_kOFMs0C_o#Hr4g:9MRk4H_DMOC_F0kMC#s_Hgor:R49DCHM_kOFMs0C_o#HrjU:9R
+RR_R8#_C0EM#$OF_OkCM0sb;
+R4@@.U:.d.:d:d.U:R6jNR88k_M4PM#$OF_OkCM0sr_444j:9MRk4#_P$_MOOMFk0_Cs4jr4:R49PM#$OF_OkCM0s:rgjR9
+R8RR_0#C_$E#MOO_F0kMC
+s;b@R@44.:6ng::g46:b(RlRkG]h1YBm_Bz_ha#\$M3$E#MOO_F0kMCds_rjg:91R]Y_hBBhmza$_#ME\3#O$M_kOFMs0C_gdr:
+j9RRRRV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#Ck_M4sCC#0R
+RRNRVD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDC#,E$_MOOMFk0_CsM0CG_#j_JGlkNR
+RRMRk.#_E$_MOOMFk0_CsM0CGrjg:9#,E$_MOOMFk0_CsM0CG_#j_JGlkNR_40Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sC#,E$_MOOMFk0_CsM0CG_#4_JGlkN;_4
+@bR@:4.4:U(cU:4(R:68RVVEM#$O0_#Nr0Cj9:nR$E#M#O_0CN0rnj:9#RE$_MO#00NCr_dj9:6,4kM_#sCCR0
+RORRD
+ ;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$E#M#O_0CN0"b;
+R4@@.6:4U::c4:6U6VR8V#RE$_MOOMFk0rCsg9:jR$E#MOO_F0kMCgsr:Rj9]h1YBm_Bz_ha#\$M3$E#MOO_F0kMCds_rjg:9R
+RRDRO N;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CREM#$OF_OkCM0s
+";b@R@44.:Uc(::(4U:#6R8#VVC_RE#O$MR#E_$RMOEM#$O0_#Nr0CcO9RDk RMs4_C0#CR4kM_$E#M#O_0CN0_
+n;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"#E_$"MO;R
+b@.@4:4dj:dn:j(4:RkblG#RP$_MO#00NCr_djP9R#O$M_N#00dC_rRj9V#NDCM,k4C_s#_C0.#RP$_MO#00NC9rj,$P#M#O_0CN0_GMC0__.#kJlGRN
+R0RRs,kCPM#$O0_#N_0CM0CG_#n_JGlkNb;
+R4@@..:4n::n4:.n(lRbkpGRQ_h Bhmza$_#MD\3H_MCOMFk0_Cs#_Hod:rUjp9RQ_h Bhmza$_#MD\3H_MCOMFk0_Cs#_Hod:rUjR9
+RVRRNCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,4kM_#sCCV0RNCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,MDHCF_OkCM0sC_MGj0__l#Jk
+GNRRRRk_M4DCHM_kOFMs0C_o#Hr4g:9H,DMOC_F0kMCMs_C_G0jJ_#lNkG_04Rs,kC0Csk,k0sCN,VD,#C0Csk,k0sCs,0k0C,s,kC0Csk,MDHCF_OkCM0sC_MG40__l#Jk_GN4b;
+R4@@.n:.U::n.:nU(lRbkeGR1BYh_zBmh#a_$3M\PM#$OF_OkCM0sr_dg9:jRYe1hBB_mazh_M#$\#3P$_MOOMFk0_Csd:rgjR9
+RVRRNCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#kC,Ms4_C0#C
+RRRRDVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,$P#MOO_F0kMCMs_C_G0jJ_#lNkG
+RRRR4kM_$P#MOO_F0kMC4s_r:4j4P9,#O$M_kOFMs0C_GMC0__j#kJlG4N_Rk0sCs,0k0C,s,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0kPC,#O$M_kOFMs0C_GMC0__4#kJlG4N_;R
+b@.@4:jdj:dc:j6j:RV8VR$P#M#O_0CN0rnj:9#RP$_MO#00NC:rjnP9R#O$M_N#00dC_r,j9PM#$O0_#N_0CM0CG_#d_JGlkN#,P$_MO#00NCr_d.9:6,4kM_#sCCR0
+RORRD
+ ;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"$P#M#O_0CN0"b;
+R4@@..:46::c4:.66VR8VHRDMOC_F0kMC#s_HUor:Rj9DCHM_kOFMs0C_o#HrjU:9QRphB _mazh_M#$\H3DMOC_F0kMC#s_Hdo_rjU:9R
+RRDRO N;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRDCHM_kOFMs0C_o#H"b;
+R4@@.n:.(::c.:n(6VR8V#RP$_MOOMFk0rCsg9:jR$P#MOO_F0kMCgsr:Rj9eh1YBm_Bz_ha#\$M3$P#MOO_F0kMCds_rjg:9R
+RRDRO N;
+H$R#Ms_bCs#CP4CR;H
+NR03sDs_FHNoMl"CRPM#$OF_OkCM0s
+";b@R@4d.:jcj::jdj:#6R8#VVC_RP#O$MR#P_$RMOPM#$O0_#Nr0CcO9RDk RMs4_C0#CR4kM_$P#M#O_0CN0_
+n;N#HR$bM_sCC#sRPC4N;
+HsR30FD_sMHoNRlC"#P_$"MO;-
+y---------------------------------
+@
+ftell;
+@E@MR@d(:(::(d4(:(FRIsP RoON_FsM0FLDRCPEN;P
+NR#3HPDE8R
+4;N3PRHP#_ER8D4N;
+PFR3shHoNRlC"NPo_MOF0DsF"N;
+P$R#Ms_bCs#CP4CR;
+
+
+
+@HR@d(:U::(dgU:R ODR OD;H
+NR03sDs_FHNoMl"CRO"D ;
+
+
+
+@HR@d(:g::(d4g:4CRs#RC0sCC#0N;
+HsR30FD_sMHoNRlC"#sCC;0"
+@HR@c(:j::(c.j:jFRODMkl_kOFMs0Crjg:9FRODMkl_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"DOFk_lMOMFk0"Cs;
+
+
+
+@FR@c(:4::(c.4:jFR0oCoD_kOFMs0Cr:.cj09RFDooCF_OkCM0sH_#ocr.:;j9
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0s
+";
+@FR@c(:.::(c4.:.FR0oCoDRo0Fo_DC#;Ho
+RNH3Ds0_HFsolMNC0R"FDooC
+";
+@HR@c(:d::(c4d:UHRDMOC_F0kMCUsr:Rj9DCHM_kOFMs0CrjU:9N;
+HsR30FD_sMHoNRlC"MDHCF_OkCM0s
+";
+@HR@c(:c::(c4c:c_RPCLMNDPCR_NCML;DC
+RNH3Ds0_HFsolMNCPR"_NCML"DC;
+
+
+
+@HR@c(:6::(c46:c_RECLMNDECR_NCML;DC
+RNH3Ds0_HFsolMNCER"_NCML"DC;
+
+
+
+@FR@c(:n::(c(n:RssR;H
+NR03sDs_FHNoMl"CRs
+";
+@FR@c(:nj:4::cn4ojRR
+o;N3HRs_0DFosHMCNlR""o;
+
+
+
+@FR@c(:nd:4::cn4LdRR
+L;N3HRs_0DFosHMCNlR""L;R
+b@:@(d(g:::dg4H4RMkPRMs4_C0#CR4kM_#sCCs0RC0#C;R
+b@4@4::ggcg:g:H6RMLPR_GMC0_RLM0CGRo0Fo_DC#;Ho
+@bR@4j::44::0.RsRkC0CskRk0sCb;
+Rj@@:44::.4:RDVN#VCRNCD#RDVN#
+C;b@R@4n4:j::cn6j:RV8VsRRooNRVDR#CORD k_M4sCC#0N;
+HsR30FD_sMHoNRlC";o"
+RNH#_$Mb#sCCCsPR
+4;b@R@4(4:6U:d::(6nDjR0)R7q1W_T)zq C_MG30\k_M6PM_CNCLDRq7)WT_1z q)_GMC0k\3MP6__NCML
+DCRRRRV#NDCN,VD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,DVN#VC,NCD#RDOFk_lMOMFk0rCsg9:j;R
+b@4@4::(64(j:6.:dRRD07W)q_z1Tq_) M0CG\M3kg__PCLMND7CR)_qW1qTz)M _C\G03gkM_CP_MDNLCR
+RRFRODMkl_kOFMs0Crjg:9NRVD,#CV#NDCN,VD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,DVN#
+C;b@R@4(4:nj:4::(ndD.R0)R7q1W_T)zq C_MG30\kdM4_CP_MDNLC)R7q1W_T)zq C_MG30\kdM4_CP_MDNLCR
+RRHRDMOC_F0kMCUsr:Rj9V#NDCN,VD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,DVN#
+C;b@R@4(4:nU:d::(nnDjR0)R7q1W_T)zq C_MG30\k(M4_CP_MDNLC)R7q1W_T)zq C_MG30\k(M4_CP_MDNLCR
+RRNRVD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,DVN#VC,NCD#RMDHCF_OkCM0s:rUj
+9;b@R@4(4:6U:d::(6nHjRMkPRMPn__NCMLRDCk_MnPM_CNCLDRq7)WT_1z q)_GMC0k\3MP6__NCML;DC
+@bR@:44(46:j6:(:Rd.HRMPkjM4_CP_MDNLCMRk4Pj__NCMLRDC7W)q_z1Tq_) M0CG\M3kg__PCLMND
+C;b@R@4(4:nj:4::(ndH.RMkPRM_4cPM_CNCLDR4kMc__PCLMND7CR)_qW1qTz)M _C\G034kMd__PCLMND
+C;b@R@4(4:nU:d::(nnHjRMkPRM_4UPM_CNCLDR4kMU__PCLMND7CR)_qW1qTz)M _C\G034kM(__PCLMND
+C;b@R@444:4(4::444:RdUDA0RpiQh M)_C\G034kM_o0Fo_DCOMFk0_Cs#RHoAhpQi_ )M0CG\M3k4F_0oCoD_kOFMs0C_o#H
+RRRRo0Fo_DCOMFk0_Cs#rHo.jc:9NRVD,#CV#NDCN,VD,#CV#NDCs,0kVC,NCD#,k0sCs,0kVC,NCD#,k0sCs,0k0C,s,kCV#NDCN,VD,#CV#NDCs,0k0C,s,kCV#NDCs,0k0C,s,kCV#NDCN,VD,#CV#NDCN,VD,#CV#NDCb;
+R4@@44:44::(4:44dHURMkPRM04_FDooCF_OkCM0sH_#oMRk4F_0oCoD_kOFMs0C_o#HRQAph)i _GMC0k\3M04_FDooCF_OkCM0sH_#ob;
+R4@@4g:g:gc:gR:68sVVCFR0oCoD_o#HRo0Fo_DC#RHoLC_MGO0RDk RMs4_C0#CR4kM_o0Fo_DCOMFk0_Cs#;Ho
+RNH3Ds0_HFsolMNC0R"FDooCH_#o
+";N#HR$bM_sCC#sRPC4b;
+R4@@46:(::4j(nn:jMRN8LPR_GMC0__j#kJlGLNR_GMC0__j#kJlGPNR_NCMLRDCEM_CNCLDRnkM_CP_MDNLCR
+RRMRk4Pj__NCMLRDCkcM4_CP_MDNLCMRk4PU__NCML;DC
+@bR@:444:46.4g:466:.8RN8MRk.F_0oCoD_kOFMs0C_GMC0jr.:Rj9k_M.0oFoDOC_F0kMCMs_CrG0.jj:9R
+RRFR0oCoD_kOFMs0C_o#Hr:.jj09Rs;kC
+@bR@:44(cc:::(c6kRlG_RLM0CG_L4R_GMC0R_4V#NDC_RLM0CGRML_C_G0jJ_#lNkG;R
+b@4@4::(ccc:(:l6RksGR_GMC0_RsM0CGRDVN#0CRFDooCH_#o_RLM0CG_#j_JGlkNb;
+R4@@44:44::c4:446kRlGFR0oCoD_kOFMs0C_GMC0jr.:Rj90oFoDOC_F0kMCMs_CrG0.jj:9NRVD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD
+#CRRRRk_M.0oFoDOC_F0kMCMs_CrG0.jj:9pRAQ hi)C_MG30\k_M40oFoDOC_F0kMC#s_H
+o;b@R@4n4:j::cn6j:RV8VsRRLL_RLM0CG_O4RDk RMs4_C0#C;H
+NR03sDs_FHNoMl"CRL
+";N#HR$bM_sCC#sRPC4b;
+R4@@4j:n:nc:jR:68sVVRssRRMs_CRG0ORD k_M4sCC#0N;
+HsR30FD_sMHoNRlC";s"
+RNH#_$Mb#sCCCsPR
+4;b@R@4g4:g::cg6g:RV8VsFR0oCoD_kOFMs0C_o#Hr:.cj09RFDooCF_OkCM0sH_#ocr.:Rj9V#NDCN,VD,#CV#NDCN,VD,#C0oFoDOC_F0kMCMs_CrG0.jj:9R
+RRDRO MRk4C_s#;C0
+RNH3Ds0_HFsolMNC0R"FDooCF_OkCM0sH_#o
+";N#HR$bM_sCC#sRPC4y;
+---------------------------------@-
+
+
+
+
+ftell;
+@E@MR@d6:U::(dgU:RsIF oRPNCRLE;NP
+RNP3PH#ER8D4N;
+PHR3#E_P84DR;P
+NR$3#Ml_VN"bRI FsR/\"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oNb3N P\E8"F
+Is\ R"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNM_C0E3P8
+\"I FsR/\"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oNN3sOP\E8"F
+Is\ R"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#OF/LN_s88PsHCCs_MP03E"8\
+sIF "R\/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NLFs88_sCHPss_NOE3P8
+\"I FsR/\"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oNO0FMs_FDC3M0P\E8"F
+Is\ R"F/El/C#LLksN8M/HD8CkH/884C_n#/Lb7./Co#HMFVDIs/#Oo/PNF_OMF0sDs_NOE3P8
+\"I FsR/\"ECFl#k/LsMLN/88HC/Dk8CH8_/4nL.#b/#7CHVoMD/FI#/sOP_oN8PsHCCs_MP03E"8\
+sIF "R\/lEFCL#/kNsLMH/88kCD/88HCn_4/bL#.C/7#MHoVIDF/O#s/NPo_H8sP_CsN3sOP\E8";
+"
+RNP#_$Mb#sCCCsPR
+4;
+@HR@c6:4::(c44:dDRO H_bMDRO H_bMN;
+HsR30FD_sMHoNRlC" OD_MbH"
+;
+
+@HR@c6:.::(c4.:6CRs#_C0bRHMsCC#0H_bMN;
+HsR30FD_sMHoNRlC"#sCCb0_H;M"
+@FR@c6:c::(c4c:.jRs_MbHR_sjb;HM
+RNH3Ds0_HFsolMNCsR"jH_bM
+";
+@FR@c6:c6:4::cc.sjR4H_bM4Rs_MbH;H
+NR03sDs_FHNoMl"CRsb4_H;M"
+@FR@c6:cd:.::cc.sUR.H_bM.Rs_MbH;H
+NR03sDs_FHNoMl"CRsb._H;M"
+@FR@c6:6::(c46:.jRo_MbHR_ojb;HM
+RNH3Ds0_HFsolMNCoR"jH_bM
+";
+@FR@c6:66:4::c6.ojR4H_bM4Ro_MbH;H
+NR03sDs_FHNoMl"CRob4_H;M"
+@FR@c6:6d:.::c6.oUR.H_bM.Ro_MbH;H
+NR03sDs_FHNoMl"CRob._H;M"
+@FR@c6:n::(c4n:.jRL_MbHR_Ljb;HM
+RNH3Ds0_HFsolMNCLR"jH_bM
+";
+@FR@c6:n6:4::cn.LjR4H_bM4RL_MbH;H
+NR03sDs_FHNoMl"CRLb4_H;M"
+@FR@c6:(::(c4(:6#RE$_MObRHMEM#$OH_bMN;
+HsR30FD_sMHoNRlC"$E#MbO_H;M"
+@FR@c6:U::(c4U:6#RP$_MObRHMPM#$OH_bMN;
+HsR30FD_sMHoNRlC"$P#MbO_H;M"
+@FR@66:j::(64j:gCR#P_CM#_CobrHM4jd:9CR#P_CM#_CobrHM4jd:9N;
+HsR30FD_sMHoNRlC"P#CC#M_Cbo_H;M"
+@FR@66:.::(64.:d_R8EM#$O_R8EM#$ON;
+HsR30FD_sMHoNRlC"E8_#O$M"
+;
+
+@FR@66:.n:4::6..8.R_$P#M8OR_$P#M
+O;N3HRs_0DFosHMCNlR_"8PM#$O
+";
+@FR@66:d::(6.d:._R8OkFDlOM_F0kMCgsr:Rj98F_ODMkl_kOFMs0Crjg:9N;
+HsR30FD_sMHoNRlC"O8_FlDkMF_OkCM0s
+";
+@FR@66:c::(6.c:j_R8DCHM_kOFMs0CrjU:9_R8DCHM_kOFMs0CrjU:9N;
+HsR30FD_sMHoNRlC"D8_H_MCOMFk0"Cs;
+
+
+
+@FR@66:6::(6.6:n_R8#_C0OkFDlOM_F0kMC8sR_0#C_DOFk_lMOMFk0;Cs
+RNH3Ds0_HFsolMNC8R"_0#C_DOFk_lMOMFk0"Cs;
+
+
+
+@FR@66:6g:.::66c8nR_0#C_MDHCF_OkCM0s_R8#_C0DCHM_kOFMs0C;H
+NR03sDs_FHNoMl"CR8C_#0H_DMOC_F0kMC;s"
+@FR@66:n::(6.n:4_R8EM#$OF_OkCM0s:rgj89R_$E#MOO_F0kMCgsr:;j9
+RNH3Ds0_HFsolMNC8R"_$E#MOO_F0kMC;s"
+@FR@66:(::(6.(:4_R8PM#$OF_OkCM0s:rgj89R_$P#MOO_F0kMCgsr:;j9
+RNH3Ds0_HFsolMNC8R"_$P#MOO_F0kMC;s"
+@FR@66:U::(6.U:6_R8#_C0EM#$OF_OkCM0s_R8#_C0EM#$OF_OkCM0sN;
+HsR30FD_sMHoNRlC"#8_CE0_#O$M_kOFMs0C"
+;
+
+@FR@66:UU:.::6Uc8nR_0#C_$P#MOO_F0kMC8sR_0#C_$P#MOO_F0kMC
+s;N3HRs_0DFosHMCNlR_"8#_C0PM#$OF_OkCM0s
+";
+@FR@66:g::(64g:n_R8EM_CNCLDRE8__NCML;DC
+RNH3Ds0_HFsolMNC8R"_CE_MDNLC
+";
+@FR@n6:j::(n4j:n_R8PM_CNCLDRP8__NCML;DC
+RNH3Ds0_HFsolMNC8R"_CP_MDNLC
+";
+@FR@n6:4::(ng4:Rs8_Rs8_;H
+NR03sDs_FHNoMl"CR8"_s;
+
+
+
+@FR@n6:4.:4::n448cR_8oR_
+o;N3HRs_0DFosHMCNlR_"8o
+";
+@FR@n6:4(:4::n448gR_8LR_
+L;N3HRs_0DFosHMCNlR_"8L
+";
+@FR@n6:.::(n4.:g_R8EM#$O0_#Nr0Cj9:nRE8_#O$M_N#00jCr:;n9
+RNH3Ds0_HFsolMNC8R"_$E#M#O_0CN0"
+;
+
+@FR@n6:d::(n4d:g_R8PM#$O0_#Nr0Cj9:nRP8_#O$M_N#00jCr:;n9
+RNH3Ds0_HFsolMNC8R"_$P#M#O_0CN0"
+;
+
+@FR@n6:c::(n4c:(_R8#00NCD_O _R8#00NCD_O N;
+HsR30FD_sMHoNRlC"#8_0CN0_ OD"
+;
+
+@FR@n6:6::(n46:c_R80oFoD8CR_o0Fo;DC
+RNH3Ds0_HFsolMNC8R"_o0Fo"DC;
+
+
+
+@FR@n6:n::(n.n:._R80oFoDOC_F0kMC.src9:jR08_FDooCF_OkCM0scr.:;j9
+RNH3Ds0_HFsolMNC8R"_o0Fo_DCOMFk0"Cs;R
+s@:@g4:66j6:46n:4RsIF FRLN_s88PsHCLsRCPENRNLFs88_sCHPsM_kHS0
+sCC#0N=#VsC_C0#C
+CS#P_CM#rCo4jd:9C=#P_CM#_CobrHM4jd:9s;
+Rg@@:44n:4j:n44:cFRIsP Ro8N_sCHPsCRLERNPP_oN8PsHCks_M
+H0S OD= OD_MbH
+CSs#=C0#CNV_#sCCS0
+OkFDlOM_F0kMCgsr:=j98F_ODMkl_kOFMs0Crjg:9D
+SH_MCOMFk0rCsU9:j=D8_H_MCOMFk0rCsU9:j
+_SECLMND8C=_CE_MDNLCP
+S_NCML=DC8__PCLMNDSC
+EM#$O#=E$_MO#
+HoS$P#MPO=#O$M_o#H
+_S8EM#$O0_#Nr0Cj9:n=E8_#O$M_N#00jCr:
+n9SP8_#O$M_N#00jCr:=n98#_P$_MO#00NC:rjnS9
+8#_E$_MOOMFk0rCsg9:j=E8_#O$M_kOFMs0Crjg:98
+S_$P#MOO_F0kMCgsr:=j98#_P$_MOOMFk0rCsg9:j
+_S8#_C0EM#$OF_OkCM0s_=8#_C0EM#$OF_OkCM0s8
+S_0#C_$P#MOO_F0kMC8s=_0#C_$P#MOO_F0kMCSs
+8C_#0F_ODMkl_kOFMs0C=#8_CO0_FlDkMF_OkCM0s8
+S_0#C_MDHCF_OkCM0s_=8#_C0DCHM_kOFMs0C;R
+s@:@g4:Un.U:4n(:4RsIF oRPNF_OMF0sDCRLERNPP_oNO0FMs_FDk0MH
+DSO D=O H_bMs
+SC0#C=V#NCC_s#
+C0SDOFk_lMOMFk0rCsg9:j=O8_FlDkMF_OkCM0s:rgjS9
+0oFoDOC_F0kMC.src9:j=08_FDooCF_OkCM0scr.:
+j9So0Fo=DC8F_0oCoD
+HSDMOC_F0kMCUsr:=j98H_DMOC_F0kMCUsr:
+j9SCP_MDNLC_=8PM_CNCLD
+_SECLMND8C=_CE_MDNLCs
+S=#s_HSo
+o_=o#
+HoSLL=_o#H;R
+b@:@6c(4:::c44LdRk8VR_N#00OC_D8 R_N#00OC_DO RDb _H
+M;b@R@6.:c:c(:.6:4RPHMR4kM_#sCCb0_HkMRMs4_C0#C_MbHR#sCCb0_H
+M;b@R@gn:4gU:.:g4n:RdnLRkV8#_E$RMO8#_E$RMOEM#$OH_#ob;
+Rg@@:g4n::.U4:ngdLnRkEVR#O$M_MbHR$E#MbO_HEMR#O$M_o#H;R
+b@:@g4:(j.4U:(dj:nkRLV_R8PM#$O_R8PM#$O#RP$_MO#;Ho
+@bR@4g:(.j:U(:4jn:dRVLkR$P#MbO_HPMR#O$M_MbHR$P#M#O_H
+o;b@R@gg:4nc:.:n4g:R.ULRkV8R_s8R_ssH_#ob;
+Rg@@:n4g::.c4:gn.LURksVRjH_bMjRs_MbHR#s_H
+o;b@R@gg:4nc:.:n4g:R.ULRkVsb4_HsMR4H_bM_Rs#;Ho
+@bR@4g:g.n:cg:4nU:.RVLkR_s.bRHMsb._HsMR_o#H;R
+b@:@g4:g(.4c:g.(:UkRLV_R8o_R8o_Ro#;Ho
+@bR@4g:g.(:cg:4(U:.RVLkR_ojbRHMobj_HoMR_o#H;R
+b@:@g4:g(.4c:g.(:UkRLV4Ro_MbHR_o4bRHMoH_#ob;
+Rg@@:(4g::.c4:g(.LURkoVR.H_bM.Ro_MbHR#o_H
+o;b@R@gg:4Uc:.:U4g:R.ULRkVLbj_HLMRjH_bM_RL#;Ho
+@bR@4g:g.U:cg:4UU:.RVLkR_L4bRHMLb4_HLMR_o#H;R
+b@:@g4:gU.4c:g.U:UkRLV_R8L_R8L_RL#;Ho
+@bR@4j::44::0.RsRkC0CskRk0sCb;
+Rj@@:44::.4:RDVN#VCRNCD#RDVN#
+C;b@R@g.:4.j:4:.4.:RdjD70R Ypq_1) Ma_C\G036kM_$8D_kOFMs0CRp7 q)Y_ a1 _GMC0k\3M86_DO$_F0kMCRs
+R8RRDO$_F0kMC4sr:Rj90Csk,k0sCb;
+Rg@@:.4.::4j4:..dFjRs7PR Ypq_1) Ma_C\G03nkM_$8D_kOFMs0CRp7 q)Y_ a1 _GMC0k\3M8n_DO$_F0kMCRs
+RkRRMs4_C0#C_MbHRp7 q)Y_ a1 _GMC0k\3M86_DO$_F0kMC
+s;b@R@g.:4dn:.:d4.:Rc.NR88k_M48_D$OMFk0rCs.9:4R4kM_$8D_kOFMs0Cr4.:9DR8$F_OkCM0s:r4jR9
+R7RR Ypq_1) Ma_C\G036kM_$8D_kOFMs0C;R
+b@:@g4:c.cc:4.R:6lRkG#CNV_#sCC#0RN_VCsCC#0sR0kVCRNCD#Rp7 q)Y_ a1 _GMC0k\3M8n_DO$_F0kMC
+s;b@R@g.:4j::c4:.j6kRlGDR8$F_OkCM0sC_MG40r:Rj98_D$OMFk0_CsM0CGrj4:9NRVD,#CV#NDCR
+RRMRk4D_8$F_OkCM0s:r.4s9RC0#C_MbH;R
+b@:@g4:4dc4:4dR:68RVV8_D$OMFk0rCs49:jR$8D_kOFMs0Crj4:9DR8$F_OkCM0sC_MG40r:
+j9RRRRO_D b;HM
+RNH#_$Mb#sCCCsPR
+4;N3HRs_0DFosHMCNlRD"8$F_OkCM0s
+";C
+;
+
--- /dev/null
+
+BeginView vga NoName
+Inst: dly_counter[1] dly_counter_1_ stratix_lcell_ff
+Inst: dly_counter[0] dly_counter_0_ stratix_lcell_ff
+Inst: d_toggle_counter_out[24] d_toggle_counter_out_24_ stratix_io
+Inst: d_toggle_counter_out[23] d_toggle_counter_out_23_ stratix_io
+Inst: d_toggle_counter_out[22] d_toggle_counter_out_22_ stratix_io
+Inst: d_toggle_counter_out[21] d_toggle_counter_out_21_ stratix_io
+Inst: d_toggle_counter_out[20] d_toggle_counter_out_20_ stratix_io
+Inst: d_toggle_counter_out[19] d_toggle_counter_out_19_ stratix_io
+Inst: d_toggle_counter_out[18] d_toggle_counter_out_18_ stratix_io
+Inst: d_toggle_counter_out[17] d_toggle_counter_out_17_ stratix_io
+Inst: d_toggle_counter_out[16] d_toggle_counter_out_16_ stratix_io
+Inst: d_toggle_counter_out[15] d_toggle_counter_out_15_ stratix_io
+Inst: d_toggle_counter_out[14] d_toggle_counter_out_14_ stratix_io
+Inst: d_toggle_counter_out[13] d_toggle_counter_out_13_ stratix_io
+Inst: d_toggle_counter_out[12] d_toggle_counter_out_12_ stratix_io
+Inst: d_toggle_counter_out[11] d_toggle_counter_out_11_ stratix_io
+Inst: d_toggle_counter_out[10] d_toggle_counter_out_10_ stratix_io
+Inst: d_toggle_counter_out[9] d_toggle_counter_out_9_ stratix_io
+Inst: d_toggle_counter_out[8] d_toggle_counter_out_8_ stratix_io
+Inst: d_toggle_counter_out[7] d_toggle_counter_out_7_ stratix_io
+Inst: d_toggle_counter_out[6] d_toggle_counter_out_6_ stratix_io
+Inst: d_toggle_counter_out[5] d_toggle_counter_out_5_ stratix_io
+Inst: d_toggle_counter_out[4] d_toggle_counter_out_4_ stratix_io
+Inst: d_toggle_counter_out[3] d_toggle_counter_out_3_ stratix_io
+Inst: d_toggle_counter_out[2] d_toggle_counter_out_2_ stratix_io
+Inst: d_toggle_counter_out[1] d_toggle_counter_out_1_ stratix_io
+Inst: d_toggle_counter_out[0] d_toggle_counter_out_0_ stratix_io
+Inst: d_vsync_state_out[0] d_vsync_state_out_0_ stratix_io
+Inst: d_vsync_state_out[1] d_vsync_state_out_1_ stratix_io
+Inst: d_vsync_state_out[2] d_vsync_state_out_2_ stratix_io
+Inst: d_vsync_state_out[3] d_vsync_state_out_3_ stratix_io
+Inst: d_vsync_state_out[4] d_vsync_state_out_4_ stratix_io
+Inst: d_vsync_state_out[5] d_vsync_state_out_5_ stratix_io
+Inst: d_vsync_state_out[6] d_vsync_state_out_6_ stratix_io
+Inst: d_hsync_state_out[0] d_hsync_state_out_0_ stratix_io
+Inst: d_hsync_state_out[1] d_hsync_state_out_1_ stratix_io
+Inst: d_hsync_state_out[2] d_hsync_state_out_2_ stratix_io
+Inst: d_hsync_state_out[3] d_hsync_state_out_3_ stratix_io
+Inst: d_hsync_state_out[4] d_hsync_state_out_4_ stratix_io
+Inst: d_hsync_state_out[5] d_hsync_state_out_5_ stratix_io
+Inst: d_hsync_state_out[6] d_hsync_state_out_6_ stratix_io
+Inst: d_vsync_counter_out[9] d_vsync_counter_out_9_ stratix_io
+Inst: d_vsync_counter_out[8] d_vsync_counter_out_8_ stratix_io
+Inst: d_vsync_counter_out[7] d_vsync_counter_out_7_ stratix_io
+Inst: d_vsync_counter_out[6] d_vsync_counter_out_6_ stratix_io
+Inst: d_vsync_counter_out[5] d_vsync_counter_out_5_ stratix_io
+Inst: d_vsync_counter_out[4] d_vsync_counter_out_4_ stratix_io
+Inst: d_vsync_counter_out[3] d_vsync_counter_out_3_ stratix_io
+Inst: d_vsync_counter_out[2] d_vsync_counter_out_2_ stratix_io
+Inst: d_vsync_counter_out[1] d_vsync_counter_out_1_ stratix_io
+Inst: d_vsync_counter_out[0] d_vsync_counter_out_0_ stratix_io
+Inst: d_hsync_counter_out[9] d_hsync_counter_out_9_ stratix_io
+Inst: d_hsync_counter_out[8] d_hsync_counter_out_8_ stratix_io
+Inst: d_hsync_counter_out[7] d_hsync_counter_out_7_ stratix_io
+Inst: d_hsync_counter_out[6] d_hsync_counter_out_6_ stratix_io
+Inst: d_hsync_counter_out[5] d_hsync_counter_out_5_ stratix_io
+Inst: d_hsync_counter_out[4] d_hsync_counter_out_4_ stratix_io
+Inst: d_hsync_counter_out[3] d_hsync_counter_out_3_ stratix_io
+Inst: d_hsync_counter_out[2] d_hsync_counter_out_2_ stratix_io
+Inst: d_hsync_counter_out[1] d_hsync_counter_out_1_ stratix_io
+Inst: d_hsync_counter_out[0] d_hsync_counter_out_0_ stratix_io
+Inst: d_line_counter_out[8] d_line_counter_out_8_ stratix_io
+Inst: d_line_counter_out[7] d_line_counter_out_7_ stratix_io
+Inst: d_line_counter_out[6] d_line_counter_out_6_ stratix_io
+Inst: d_line_counter_out[5] d_line_counter_out_5_ stratix_io
+Inst: d_line_counter_out[4] d_line_counter_out_4_ stratix_io
+Inst: d_line_counter_out[3] d_line_counter_out_3_ stratix_io
+Inst: d_line_counter_out[2] d_line_counter_out_2_ stratix_io
+Inst: d_line_counter_out[1] d_line_counter_out_1_ stratix_io
+Inst: d_line_counter_out[0] d_line_counter_out_0_ stratix_io
+Inst: d_column_counter_out[9] d_column_counter_out_9_ stratix_io
+Inst: d_column_counter_out[8] d_column_counter_out_8_ stratix_io
+Inst: d_column_counter_out[7] d_column_counter_out_7_ stratix_io
+Inst: d_column_counter_out[6] d_column_counter_out_6_ stratix_io
+Inst: d_column_counter_out[5] d_column_counter_out_5_ stratix_io
+Inst: d_column_counter_out[4] d_column_counter_out_4_ stratix_io
+Inst: d_column_counter_out[3] d_column_counter_out_3_ stratix_io
+Inst: d_column_counter_out[2] d_column_counter_out_2_ stratix_io
+Inst: d_column_counter_out[1] d_column_counter_out_1_ stratix_io
+Inst: d_column_counter_out[0] d_column_counter_out_0_ stratix_io
+Inst: seven_seg_pin_tri[13] seven_seg_pin_tri_13_ stratix_io
+Inst: seven_seg_pin_out[12] seven_seg_pin_out_12_ stratix_io
+Inst: seven_seg_pin_out[11] seven_seg_pin_out_11_ stratix_io
+Inst: seven_seg_pin_out[10] seven_seg_pin_out_10_ stratix_io
+Inst: seven_seg_pin_out[9] seven_seg_pin_out_9_ stratix_io
+Inst: seven_seg_pin_out[8] seven_seg_pin_out_8_ stratix_io
+Inst: seven_seg_pin_out[7] seven_seg_pin_out_7_ stratix_io
+Inst: seven_seg_pin_tri[6] seven_seg_pin_tri_6_ stratix_io
+Inst: seven_seg_pin_tri[5] seven_seg_pin_tri_5_ stratix_io
+Inst: seven_seg_pin_tri[4] seven_seg_pin_tri_4_ stratix_io
+Inst: seven_seg_pin_tri[3] seven_seg_pin_tri_3_ stratix_io
+Inst: seven_seg_pin_out[2] seven_seg_pin_out_2_ stratix_io
+Inst: seven_seg_pin_out[1] seven_seg_pin_out_1_ stratix_io
+Inst: seven_seg_pin_tri[0] seven_seg_pin_tri_0_ stratix_io
+Net: DELAY_RESET_next\.un6_dly_counter_0_x DELAY_RESET_next_un6_dly_counter_0_x
+Net: vga_driver_unit.h_sync vga_driver_unit_h_sync
+Net: vga_driver_unit.v_sync vga_driver_unit_v_sync
+Net: vga_driver_unit.column_counter_sig[0] vga_driver_unit_column_counter_sig[0]
+Net: vga_driver_unit.column_counter_sig[1] vga_driver_unit_column_counter_sig[1]
+Net: vga_driver_unit.column_counter_sig[2] vga_driver_unit_column_counter_sig[2]
+Net: vga_driver_unit.column_counter_sig[3] vga_driver_unit_column_counter_sig[3]
+Net: vga_driver_unit.column_counter_sig[4] vga_driver_unit_column_counter_sig[4]
+Net: vga_driver_unit.column_counter_sig[5] vga_driver_unit_column_counter_sig[5]
+Net: vga_driver_unit.column_counter_sig[6] vga_driver_unit_column_counter_sig[6]
+Net: vga_driver_unit.column_counter_sig[7] vga_driver_unit_column_counter_sig[7]
+Net: vga_driver_unit.column_counter_sig[8] vga_driver_unit_column_counter_sig[8]
+Net: vga_driver_unit.column_counter_sig[9] vga_driver_unit_column_counter_sig[9]
+Net: vga_driver_unit.line_counter_sig[0] vga_driver_unit_line_counter_sig[0]
+Net: vga_driver_unit.line_counter_sig[1] vga_driver_unit_line_counter_sig[1]
+Net: vga_driver_unit.line_counter_sig[2] vga_driver_unit_line_counter_sig[2]
+Net: vga_driver_unit.line_counter_sig[3] vga_driver_unit_line_counter_sig[3]
+Net: vga_driver_unit.line_counter_sig[4] vga_driver_unit_line_counter_sig[4]
+Net: vga_driver_unit.line_counter_sig[5] vga_driver_unit_line_counter_sig[5]
+Net: vga_driver_unit.line_counter_sig[6] vga_driver_unit_line_counter_sig[6]
+Net: vga_driver_unit.line_counter_sig[7] vga_driver_unit_line_counter_sig[7]
+Net: vga_driver_unit.line_counter_sig[8] vga_driver_unit_line_counter_sig[8]
+Net: vga_driver_unit.hsync_counter[0] vga_driver_unit_hsync_counter[0]
+Net: vga_driver_unit.hsync_counter[1] vga_driver_unit_hsync_counter[1]
+Net: vga_driver_unit.hsync_counter[2] vga_driver_unit_hsync_counter[2]
+Net: vga_driver_unit.hsync_counter[3] vga_driver_unit_hsync_counter[3]
+Net: vga_driver_unit.hsync_counter[4] vga_driver_unit_hsync_counter[4]
+Net: vga_driver_unit.hsync_counter[5] vga_driver_unit_hsync_counter[5]
+Net: vga_driver_unit.hsync_counter[6] vga_driver_unit_hsync_counter[6]
+Net: vga_driver_unit.hsync_counter[7] vga_driver_unit_hsync_counter[7]
+Net: vga_driver_unit.hsync_counter[8] vga_driver_unit_hsync_counter[8]
+Net: vga_driver_unit.hsync_counter[9] vga_driver_unit_hsync_counter[9]
+Net: vga_driver_unit.vsync_counter[0] vga_driver_unit_vsync_counter[0]
+Net: vga_driver_unit.vsync_counter[1] vga_driver_unit_vsync_counter[1]
+Net: vga_driver_unit.vsync_counter[2] vga_driver_unit_vsync_counter[2]
+Net: vga_driver_unit.vsync_counter[3] vga_driver_unit_vsync_counter[3]
+Net: vga_driver_unit.vsync_counter[4] vga_driver_unit_vsync_counter[4]
+Net: vga_driver_unit.vsync_counter[5] vga_driver_unit_vsync_counter[5]
+Net: vga_driver_unit.vsync_counter[6] vga_driver_unit_vsync_counter[6]
+Net: vga_driver_unit.vsync_counter[7] vga_driver_unit_vsync_counter[7]
+Net: vga_driver_unit.vsync_counter[8] vga_driver_unit_vsync_counter[8]
+Net: vga_driver_unit.vsync_counter[9] vga_driver_unit_vsync_counter[9]
+Net: vga_driver_unit.d_set_hsync_counter vga_driver_unit_d_set_hsync_counter
+Net: vga_driver_unit.d_set_vsync_counter vga_driver_unit_d_set_vsync_counter
+Net: vga_driver_unit.h_enable_sig vga_driver_unit_h_enable_sig
+Net: vga_driver_unit.v_enable_sig vga_driver_unit_v_enable_sig
+Net: vga_control_unit.r vga_control_unit_r
+Net: vga_control_unit.g vga_control_unit_g
+Net: vga_control_unit.b vga_control_unit_b
+Net: vga_driver_unit.hsync_state[6] vga_driver_unit_hsync_state[6]
+Net: vga_driver_unit.hsync_state[5] vga_driver_unit_hsync_state[5]
+Net: vga_driver_unit.hsync_state[4] vga_driver_unit_hsync_state[4]
+Net: vga_driver_unit.hsync_state[3] vga_driver_unit_hsync_state[3]
+Net: vga_driver_unit.hsync_state[2] vga_driver_unit_hsync_state[2]
+Net: vga_driver_unit.hsync_state[1] vga_driver_unit_hsync_state[1]
+Net: vga_driver_unit.hsync_state[0] vga_driver_unit_hsync_state[0]
+Net: vga_driver_unit.vsync_state[6] vga_driver_unit_vsync_state[6]
+Net: vga_driver_unit.vsync_state[5] vga_driver_unit_vsync_state[5]
+Net: vga_driver_unit.vsync_state[4] vga_driver_unit_vsync_state[4]
+Net: vga_driver_unit.vsync_state[3] vga_driver_unit_vsync_state[3]
+Net: vga_driver_unit.vsync_state[2] vga_driver_unit_vsync_state[2]
+Net: vga_driver_unit.vsync_state[1] vga_driver_unit_vsync_state[1]
+Net: vga_driver_unit.vsync_state[0] vga_driver_unit_vsync_state[0]
+Net: vga_control_unit.toggle_sig vga_control_unit_toggle_sig
+Net: vga_control_unit.toggle_counter_sig[0] vga_control_unit_toggle_counter_sig[0]
+Net: vga_control_unit.toggle_counter_sig[1] vga_control_unit_toggle_counter_sig[1]
+Net: vga_control_unit.toggle_counter_sig[2] vga_control_unit_toggle_counter_sig[2]
+Net: vga_control_unit.toggle_counter_sig[3] vga_control_unit_toggle_counter_sig[3]
+Net: vga_control_unit.toggle_counter_sig[4] vga_control_unit_toggle_counter_sig[4]
+Net: vga_control_unit.toggle_counter_sig[5] vga_control_unit_toggle_counter_sig[5]
+Net: vga_control_unit.toggle_counter_sig[6] vga_control_unit_toggle_counter_sig[6]
+Net: vga_control_unit.toggle_counter_sig[7] vga_control_unit_toggle_counter_sig[7]
+Net: vga_control_unit.toggle_counter_sig[8] vga_control_unit_toggle_counter_sig[8]
+Net: vga_control_unit.toggle_counter_sig[9] vga_control_unit_toggle_counter_sig[9]
+Net: vga_control_unit.toggle_counter_sig[10] vga_control_unit_toggle_counter_sig[10]
+Net: vga_control_unit.toggle_counter_sig[11] vga_control_unit_toggle_counter_sig[11]
+Net: vga_control_unit.toggle_counter_sig[12] vga_control_unit_toggle_counter_sig[12]
+Net: vga_control_unit.toggle_counter_sig[13] vga_control_unit_toggle_counter_sig[13]
+Net: vga_control_unit.toggle_counter_sig[14] vga_control_unit_toggle_counter_sig[14]
+Net: vga_control_unit.toggle_counter_sig[15] vga_control_unit_toggle_counter_sig[15]
+Net: vga_control_unit.toggle_counter_sig[16] vga_control_unit_toggle_counter_sig[16]
+Net: vga_control_unit.toggle_counter_sig[17] vga_control_unit_toggle_counter_sig[17]
+Net: vga_control_unit.toggle_counter_sig[18] vga_control_unit_toggle_counter_sig[18]
+Net: vga_control_unit.toggle_counter_sig[19] vga_control_unit_toggle_counter_sig[19]
+Net: vga_control_unit.toggle_counter_sig[20] vga_control_unit_toggle_counter_sig[20]
+Net: vga_control_unit.toggle_counter_sig[21] vga_control_unit_toggle_counter_sig[21]
+Net: vga_control_unit.toggle_counter_sig[22] vga_control_unit_toggle_counter_sig[22]
+Net: vga_control_unit.toggle_counter_sig[23] vga_control_unit_toggle_counter_sig[23]
+Net: vga_control_unit.toggle_counter_sig[24] vga_control_unit_toggle_counter_sig[24]
+Net: clk_pin_c G_33
+EndView vga NoName
+
+BeginView vga_driver NoName
+Inst: hsync_counter[0] hsync_counter_0_ stratix_lcell_ff
+Inst: hsync_counter[1] hsync_counter_1_ stratix_lcell_ff
+Inst: hsync_counter[2] hsync_counter_2_ stratix_lcell_ff
+Inst: hsync_counter[3] hsync_counter_3_ stratix_lcell_ff
+Inst: hsync_counter[4] hsync_counter_4_ stratix_lcell_ff
+Inst: hsync_counter[5] hsync_counter_5_ stratix_lcell_ff
+Inst: hsync_counter[6] hsync_counter_6_ stratix_lcell_ff
+Inst: hsync_counter[7] hsync_counter_7_ stratix_lcell_ff
+Inst: hsync_counter[8] hsync_counter_8_ stratix_lcell_ff
+Inst: hsync_counter[9] hsync_counter_9_ stratix_lcell_ff
+Inst: vsync_counter[0] vsync_counter_0_ stratix_lcell_ff
+Inst: vsync_counter[1] vsync_counter_1_ stratix_lcell_ff
+Inst: vsync_counter[2] vsync_counter_2_ stratix_lcell_ff
+Inst: vsync_counter[3] vsync_counter_3_ stratix_lcell_ff
+Inst: vsync_counter[4] vsync_counter_4_ stratix_lcell_ff
+Inst: vsync_counter[5] vsync_counter_5_ stratix_lcell_ff
+Inst: vsync_counter[6] vsync_counter_6_ stratix_lcell_ff
+Inst: vsync_counter[7] vsync_counter_7_ stratix_lcell_ff
+Inst: vsync_counter[8] vsync_counter_8_ stratix_lcell_ff
+Inst: vsync_counter[9] vsync_counter_9_ stratix_lcell_ff
+Inst: column_counter_sig[9] column_counter_sig_9_ stratix_lcell_ff
+Inst: column_counter_sig[8] column_counter_sig_8_ stratix_lcell_ff
+Inst: column_counter_sig[7] column_counter_sig_7_ stratix_lcell_ff
+Inst: column_counter_sig[6] column_counter_sig_6_ stratix_lcell_ff
+Inst: column_counter_sig[5] column_counter_sig_5_ stratix_lcell_ff
+Inst: column_counter_sig[4] column_counter_sig_4_ stratix_lcell_ff
+Inst: column_counter_sig[3] column_counter_sig_3_ stratix_lcell_ff
+Inst: column_counter_sig[2] column_counter_sig_2_ stratix_lcell_ff
+Inst: column_counter_sig[1] column_counter_sig_1_ stratix_lcell_ff
+Inst: column_counter_sig[0] column_counter_sig_0_ stratix_lcell_ff
+Inst: hsync_state[6] hsync_state_6_ stratix_lcell_ff
+Inst: vsync_state[0] vsync_state_0_ stratix_lcell_ff
+Inst: vsync_state[1] vsync_state_1_ stratix_lcell_ff
+Inst: vsync_state[6] vsync_state_6_ stratix_lcell_ff
+Inst: line_counter_sig[8] line_counter_sig_8_ stratix_lcell_ff
+Inst: line_counter_sig[7] line_counter_sig_7_ stratix_lcell_ff
+Inst: line_counter_sig[6] line_counter_sig_6_ stratix_lcell_ff
+Inst: line_counter_sig[5] line_counter_sig_5_ stratix_lcell_ff
+Inst: line_counter_sig[4] line_counter_sig_4_ stratix_lcell_ff
+Inst: line_counter_sig[3] line_counter_sig_3_ stratix_lcell_ff
+Inst: line_counter_sig[2] line_counter_sig_2_ stratix_lcell_ff
+Inst: line_counter_sig[1] line_counter_sig_1_ stratix_lcell_ff
+Inst: line_counter_sig[0] line_counter_sig_0_ stratix_lcell_ff
+Inst: v_enable_sig v_enable_sig_Z stratix_lcell_ff
+Inst: h_enable_sig h_enable_sig_Z stratix_lcell_ff
+Inst: h_sync h_sync_Z stratix_lcell_ff
+Inst: v_sync v_sync_Z stratix_lcell_ff
+Inst: vsync_state[5] vsync_state_5_ stratix_lcell_ff
+Inst: vsync_state[4] vsync_state_4_ stratix_lcell_ff
+Inst: vsync_state[3] vsync_state_3_ stratix_lcell_ff
+Inst: vsync_state[2] vsync_state_2_ stratix_lcell_ff
+Inst: hsync_state[5] hsync_state_5_ stratix_lcell_ff
+Inst: hsync_state[4] hsync_state_4_ stratix_lcell_ff
+Inst: hsync_state[3] hsync_state_3_ stratix_lcell_ff
+Inst: hsync_state[2] hsync_state_2_ stratix_lcell_ff
+Inst: hsync_state[1] hsync_state_1_ stratix_lcell_ff
+Inst: hsync_state[0] hsync_state_0_ stratix_lcell_ff
+Inst: vsync_state_next_2_sqmuxa vsync_state_next_2_sqmuxa_cZ stratix_lcell
+Inst: hsync_state_3_0_0_0__g0_0 hsync_state_3_0_0_0__g0_0_cZ stratix_lcell
+Inst: un1_hsync_state_next_1_sqmuxa_0 un1_hsync_state_next_1_sqmuxa_0_cZ stratix_lcell
+Inst: un1_vsync_state_next_1_sqmuxa_0 un1_vsync_state_next_1_sqmuxa_0_cZ stratix_lcell
+Inst: vsync_state_3_iv_0_0__g0_0_a3_0 vsync_state_3_iv_0_0__g0_0_a3_0_cZ stratix_lcell
+Inst: LINE_COUNT_next\.un10_line_counter_siglto8 LINE_COUNT_next_un10_line_counter_siglto8 stratix_lcell
+Inst: vsync_state_next_1_sqmuxa_1 vsync_state_next_1_sqmuxa_1_cZ stratix_lcell
+Inst: vsync_state_next_1_sqmuxa_2 vsync_state_next_1_sqmuxa_2_cZ stratix_lcell
+Inst: vsync_state_next_1_sqmuxa_3 vsync_state_next_1_sqmuxa_3_cZ stratix_lcell
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglto9 COLUMN_COUNT_next_un10_column_counter_siglto9 stratix_lcell
+Inst: hsync_state_next_1_sqmuxa_2 hsync_state_next_1_sqmuxa_2_cZ stratix_lcell
+Inst: hsync_state_next_1_sqmuxa_1 hsync_state_next_1_sqmuxa_1_cZ stratix_lcell
+Inst: HSYNC_FSM_next\.un13_hsync_counter HSYNC_FSM_next_un13_hsync_counter stratix_lcell
+Inst: HSYNC_COUNT_next\.un9_hsync_counterlt9 HSYNC_COUNT_next_un9_hsync_counterlt9 stratix_lcell
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9 VSYNC_COUNT_next_un9_vsync_counterlt9 stratix_lcell
+Inst: HSYNC_FSM_next\.un12_hsync_counter HSYNC_FSM_next_un12_hsync_counter stratix_lcell
+Inst: LINE_COUNT_next\.un10_line_counter_siglto5 LINE_COUNT_next_un10_line_counter_siglto5 stratix_lcell
+Inst: VSYNC_FSM_next\.un15_vsync_counter_4 VSYNC_FSM_next_un15_vsync_counter_4 stratix_lcell
+Inst: VSYNC_FSM_next\.un13_vsync_counter_4 VSYNC_FSM_next_un13_vsync_counter_4 stratix_lcell
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglt6 COLUMN_COUNT_next_un10_column_counter_siglt6 stratix_lcell
+Inst: hsync_counter_next_1_sqmuxa hsync_counter_next_1_sqmuxa_cZ stratix_lcell
+Inst: VSYNC_FSM_next\.un14_vsync_counter_8 VSYNC_FSM_next_un14_vsync_counter_8 stratix_lcell
+Inst: line_counter_next_0_sqmuxa_1_1 line_counter_next_0_sqmuxa_1_1_cZ stratix_lcell
+Inst: v_sync_1_0_0_0_g1 v_sync_1_0_0_0_g1_cZ stratix_lcell
+Inst: h_enable_sig_1_0_0_0_g0_i_o4 h_enable_sig_1_0_0_0_g0_i_o4_cZ stratix_lcell
+Inst: vsync_counter_next_1_sqmuxa vsync_counter_next_1_sqmuxa_cZ stratix_lcell
+Inst: v_enable_sig_1_0_0_0_g0_i_o4 v_enable_sig_1_0_0_0_g0_i_o4_cZ stratix_lcell
+Inst: h_sync_1_0_0_0_g1 h_sync_1_0_0_0_g1_cZ stratix_lcell
+Inst: column_counter_next_0_sqmuxa_1_1 column_counter_next_0_sqmuxa_1_1_cZ stratix_lcell
+Inst: HSYNC_FSM_next\.un12_hsync_counter_4 HSYNC_FSM_next_un12_hsync_counter_4 stratix_lcell
+Inst: HSYNC_FSM_next\.un12_hsync_counter_3 HSYNC_FSM_next_un12_hsync_counter_3 stratix_lcell
+Inst: HSYNC_FSM_next\.un11_hsync_counter_3 HSYNC_FSM_next_un11_hsync_counter_3 stratix_lcell
+Inst: HSYNC_FSM_next\.un11_hsync_counter_2 HSYNC_FSM_next_un11_hsync_counter_2 stratix_lcell
+Inst: HSYNC_COUNT_next\.un9_hsync_counterlt9_3 HSYNC_COUNT_next_un9_hsync_counterlt9_3 stratix_lcell
+Inst: HSYNC_FSM_next\.un13_hsync_counter_2 HSYNC_FSM_next_un13_hsync_counter_2 stratix_lcell
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9_6 VSYNC_COUNT_next_un9_vsync_counterlt9_6 stratix_lcell
+Inst: VSYNC_COUNT_next\.un9_vsync_counterlt9_5 VSYNC_COUNT_next_un9_vsync_counterlt9_5 stratix_lcell
+Inst: HSYNC_FSM_next\.un10_hsync_counter_4 HSYNC_FSM_next_un10_hsync_counter_4 stratix_lcell
+Inst: HSYNC_FSM_next\.un10_hsync_counter_3 HSYNC_FSM_next_un10_hsync_counter_3 stratix_lcell
+Inst: VSYNC_FSM_next\.un15_vsync_counter_3 VSYNC_FSM_next_un15_vsync_counter_3 stratix_lcell
+Inst: VSYNC_FSM_next\.un13_vsync_counter_3 VSYNC_FSM_next_un13_vsync_counter_3 stratix_lcell
+Inst: COLUMN_COUNT_next\.un10_column_counter_siglt6_4 COLUMN_COUNT_next_un10_column_counter_siglt6_4 stratix_lcell
+Inst: LINE_COUNT_next\.un10_line_counter_siglt4_2 LINE_COUNT_next_un10_line_counter_siglt4_2 stratix_lcell
+Inst: HSYNC_FSM_next\.un10_hsync_counter_1 HSYNC_FSM_next_un10_hsync_counter_1 stratix_lcell
+Inst: VSYNC_FSM_next\.un12_vsync_counter_6 VSYNC_FSM_next_un12_vsync_counter_6 stratix_lcell
+Inst: VSYNC_FSM_next\.un12_vsync_counter_7 VSYNC_FSM_next_un12_vsync_counter_7 stratix_lcell
+Inst: HSYNC_FSM_next\.un13_hsync_counter_7 HSYNC_FSM_next_un13_hsync_counter_7 stratix_lcell
+Inst: un1_hsync_state_3_0 un1_hsync_state_3_0_cZ stratix_lcell
+Inst: un1_vsync_state_2_0 un1_vsync_state_2_0_cZ stratix_lcell
+Inst: d_set_hsync_counter d_set_hsync_counter_cZ stratix_lcell
+Inst: d_set_vsync_counter d_set_vsync_counter_cZ stratix_lcell
+Inst: un1_line_counter_sig[9] un1_line_counter_sig_9_ stratix_lcell
+Inst: un1_line_counter_sig[8] un1_line_counter_sig_8_ stratix_lcell
+Inst: un1_line_counter_sig[7] un1_line_counter_sig_7_ stratix_lcell
+Inst: un1_line_counter_sig[6] un1_line_counter_sig_6_ stratix_lcell
+Inst: un1_line_counter_sig[5] un1_line_counter_sig_5_ stratix_lcell
+Inst: un1_line_counter_sig[4] un1_line_counter_sig_4_ stratix_lcell
+Inst: un1_line_counter_sig[3] un1_line_counter_sig_3_ stratix_lcell
+Inst: un1_line_counter_sig[2] un1_line_counter_sig_2_ stratix_lcell
+Inst: un1_line_counter_sig_a[1] un1_line_counter_sig_a_1_ stratix_lcell
+Inst: un1_line_counter_sig[1] un1_line_counter_sig_1_ stratix_lcell
+Inst: un2_column_counter_next[9] un2_column_counter_next_9_ stratix_lcell
+Inst: un2_column_counter_next[8] un2_column_counter_next_8_ stratix_lcell
+Inst: un2_column_counter_next[7] un2_column_counter_next_7_ stratix_lcell
+Inst: un2_column_counter_next[6] un2_column_counter_next_6_ stratix_lcell
+Inst: un2_column_counter_next[5] un2_column_counter_next_5_ stratix_lcell
+Inst: un2_column_counter_next[4] un2_column_counter_next_4_ stratix_lcell
+Inst: un2_column_counter_next[3] un2_column_counter_next_3_ stratix_lcell
+Inst: un2_column_counter_next[2] un2_column_counter_next_2_ stratix_lcell
+Inst: un2_column_counter_next[1] un2_column_counter_next_1_ stratix_lcell
+Inst: un2_column_counter_next[0] un2_column_counter_next_0_ stratix_lcell
+Inst: line_counter_next_0_sqmuxa_1_1_i line_counter_next_0_sqmuxa_1_1_i_cZ inv
+Inst: column_counter_next_0_sqmuxa_1_1_i column_counter_next_0_sqmuxa_1_1_i_cZ inv
+Inst: un9_vsync_counterlt9_i un9_vsync_counterlt9_i_cZ inv
+Inst: G_16_i_i G_16_i_i_cZ inv
+Inst: un9_hsync_counterlt9_i un9_hsync_counterlt9_i_cZ inv
+Inst: G_2_i_i G_2_i_i_cZ inv
+EndView vga_driver NoName
+
+BeginView vga_control NoName
+Inst: toggle_counter_sig[24] toggle_counter_sig_24_ stratix_lcell_ff
+Inst: toggle_counter_sig[23] toggle_counter_sig_23_ stratix_lcell_ff
+Inst: toggle_counter_sig[22] toggle_counter_sig_22_ stratix_lcell_ff
+Inst: toggle_counter_sig[21] toggle_counter_sig_21_ stratix_lcell_ff
+Inst: toggle_counter_sig[20] toggle_counter_sig_20_ stratix_lcell_ff
+Inst: toggle_counter_sig[19] toggle_counter_sig_19_ stratix_lcell_ff
+Inst: toggle_counter_sig[18] toggle_counter_sig_18_ stratix_lcell_ff
+Inst: toggle_counter_sig[17] toggle_counter_sig_17_ stratix_lcell_ff
+Inst: toggle_counter_sig[16] toggle_counter_sig_16_ stratix_lcell_ff
+Inst: toggle_counter_sig[15] toggle_counter_sig_15_ stratix_lcell_ff
+Inst: toggle_counter_sig[14] toggle_counter_sig_14_ stratix_lcell_ff
+Inst: toggle_counter_sig[13] toggle_counter_sig_13_ stratix_lcell_ff
+Inst: toggle_counter_sig[12] toggle_counter_sig_12_ stratix_lcell_ff
+Inst: toggle_counter_sig[11] toggle_counter_sig_11_ stratix_lcell_ff
+Inst: toggle_counter_sig[10] toggle_counter_sig_10_ stratix_lcell_ff
+Inst: toggle_counter_sig[9] toggle_counter_sig_9_ stratix_lcell_ff
+Inst: toggle_counter_sig[8] toggle_counter_sig_8_ stratix_lcell_ff
+Inst: toggle_counter_sig[7] toggle_counter_sig_7_ stratix_lcell_ff
+Inst: toggle_counter_sig[6] toggle_counter_sig_6_ stratix_lcell_ff
+Inst: toggle_counter_sig[5] toggle_counter_sig_5_ stratix_lcell_ff
+Inst: toggle_counter_sig[4] toggle_counter_sig_4_ stratix_lcell_ff
+Inst: toggle_counter_sig[3] toggle_counter_sig_3_ stratix_lcell_ff
+Inst: toggle_counter_sig[2] toggle_counter_sig_2_ stratix_lcell_ff
+Inst: toggle_counter_sig[1] toggle_counter_sig_1_ stratix_lcell_ff
+Inst: toggle_counter_sig[0] toggle_counter_sig_0_ stratix_lcell_ff
+Inst: toggle_sig toggle_sig_Z stratix_lcell_ff
+Inst: r r_Z stratix_lcell_ff
+Inst: b b_Z stratix_lcell_ff
+Inst: g g_Z stratix_lcell_ff
+Inst: toggle_sig_0_0_0_g1 toggle_sig_0_0_0_g1_cZ stratix_lcell
+Inst: BLINKER_next\.un1_toggle_counter_siglto18 BLINKER_next_un1_toggle_counter_siglto18 stratix_lcell
+Inst: b_next_0_sqmuxa_7_5 b_next_0_sqmuxa_7_5_cZ stratix_lcell
+Inst: b_next_0_sqmuxa_7_4 b_next_0_sqmuxa_7_4_cZ stratix_lcell
+Inst: b_next_0_sqmuxa_7_4_a b_next_0_sqmuxa_7_4_a_cZ stratix_lcell
+Inst: b_next_0_sqmuxa_7_3 b_next_0_sqmuxa_7_3_cZ stratix_lcell
+Inst: BLINKER_next\.un1_toggle_counter_siglto15 BLINKER_next_un1_toggle_counter_siglto15 stratix_lcell
+Inst: DRAW_SQUARE_next\.un5_v_enablelto5 DRAW_SQUARE_next_un5_v_enablelto5 stratix_lcell
+Inst: BLINKER_next\.un1_toggle_counter_siglto12 BLINKER_next_un1_toggle_counter_siglto12 stratix_lcell
+Inst: DRAW_SQUARE_next\.un13_v_enablelto6 DRAW_SQUARE_next_un13_v_enablelto6 stratix_lcell
+Inst: DRAW_SQUARE_next\.un9_v_enablelto6 DRAW_SQUARE_next_un9_v_enablelto6 stratix_lcell
+Inst: BLINKER_next\.un1_toggle_counter_siglto9 BLINKER_next_un1_toggle_counter_siglto9 stratix_lcell
+Inst: DRAW_SQUARE_next\.un17_v_enablelto3 DRAW_SQUARE_next_un17_v_enablelto3 stratix_lcell
+Inst: toggle_sig_0_0_0_g1_2 toggle_sig_0_0_0_g1_2_cZ stratix_lcell
+Inst: b_next_0_sqmuxa_7_2 b_next_0_sqmuxa_7_2_cZ stratix_lcell
+Inst: DRAW_SQUARE_next\.un9_v_enablelto4 DRAW_SQUARE_next_un9_v_enablelto4 stratix_lcell
+Inst: DRAW_SQUARE_next\.un5_v_enablelt2 DRAW_SQUARE_next_un5_v_enablelt2 stratix_lcell
+Inst: DRAW_SQUARE_next\.un13_v_enablelto4_0 DRAW_SQUARE_next_un13_v_enablelto4_0 stratix_lcell
+Inst: BLINKER_next\.un1_toggle_counter_siglt6 BLINKER_next_un1_toggle_counter_siglt6 stratix_lcell
+Inst: un2_toggle_counter_next[0] un2_toggle_counter_next_0_ stratix_lcell
+Inst: toggle_sig_0_0_0_g1_i toggle_sig_0_0_0_g1_i_cZ inv
+EndView vga_control NoName
--- /dev/null
+# Run with quartus_sh -t <x_cons.tcl>
+
+# Global assignments
+set_global_assignment -name TOP_LEVEL_ENTITY "|vga"
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE NORMAL
+set_global_assignment -name FAMILY "STRATIX"
+set_global_assignment -name DEVICE "EP1S25F672C6"
+set_global_assignment -section_id vga -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "SYNPLIFY"
+set_global_assignment -section_id eda_design_synthesis -name EDA_USE_LMF synplcty.lmf
+set_global_assignment -name TAO_FILE "myresults.tao"
+set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000"
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "OFF"
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF"
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF"
+# set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+#set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY"
+set_global_assignment -name ENABLE_CLOCK_LATENCY "ON"
+
+# Clock assignments
+
+create_base_clock clk_pin_setting -fmax 25.175mhz -duty_cycle 50.00 -target clk_pin
+
+
+# False path constraints
+
+# Multicycle constraints
+
+# Path delay constraints
+if {[file exists ___quartus_options.tcl]} {
+ source ___quartus_options.tcl
+}
+
+
+# Incremental Compilation
+ # this will synchronize any existing partitions declared in Synpilfy
+ # with partitions existing in Quartus. If partitions exist,
+ # incremental compilation will be enabled
+ variable compile_point_list
+ set compile_point_list [list]
+ source "/opt/synplify/fpga_c200906/lib/altera/qic.tcl"
--- /dev/null
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav
+Post processing for work.vga_control.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
+@N: CD231 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
+Post processing for work.vga_driver.behav
+@N: CD630 :"/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav
+Post processing for work.board_driver.behav
+Post processing for work.vga.behav
--- /dev/null
+--
+-- Written by Synplicity
+-- Product Version "C-2009.06"
+-- Program "Synplify Pro", Mapper "map450rc, Build 029R"
+-- Wed Oct 21 17:26:36 2009
+--
+
+--
+-- Written by Synplify Pro version Build 029R
+-- Wed Oct 21 17:26:36 2009
+--
+
+--
+library ieee, stratix;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+use stratix.stratix_components.all;
+
+entity vga_control is
+port(
+ line_counter_sig_0 : in std_logic;
+ line_counter_sig_2 : in std_logic;
+ line_counter_sig_1 : in std_logic;
+ line_counter_sig_3 : in std_logic;
+ line_counter_sig_6 : in std_logic;
+ line_counter_sig_5 : in std_logic;
+ line_counter_sig_4 : in std_logic;
+ line_counter_sig_7 : in std_logic;
+ line_counter_sig_8 : in std_logic;
+ column_counter_sig_0 : in std_logic;
+ column_counter_sig_1 : in std_logic;
+ column_counter_sig_2 : in std_logic;
+ column_counter_sig_8 : in std_logic;
+ column_counter_sig_3 : in std_logic;
+ column_counter_sig_5 : in std_logic;
+ column_counter_sig_4 : in std_logic;
+ column_counter_sig_9 : in std_logic;
+ column_counter_sig_7 : in std_logic;
+ column_counter_sig_6 : in std_logic;
+ toggle_counter_sig_0 : out std_logic;
+ toggle_counter_sig_1 : out std_logic;
+ toggle_counter_sig_2 : out std_logic;
+ toggle_counter_sig_3 : out std_logic;
+ toggle_counter_sig_4 : out std_logic;
+ toggle_counter_sig_5 : out std_logic;
+ toggle_counter_sig_6 : out std_logic;
+ toggle_counter_sig_7 : out std_logic;
+ toggle_counter_sig_8 : out std_logic;
+ toggle_counter_sig_9 : out std_logic;
+ toggle_counter_sig_10 : out std_logic;
+ toggle_counter_sig_11 : out std_logic;
+ toggle_counter_sig_12 : out std_logic;
+ toggle_counter_sig_13 : out std_logic;
+ toggle_counter_sig_14 : out std_logic;
+ toggle_counter_sig_15 : out std_logic;
+ toggle_counter_sig_16 : out std_logic;
+ toggle_counter_sig_17 : out std_logic;
+ toggle_counter_sig_18 : out std_logic;
+ toggle_counter_sig_19 : out std_logic;
+ toggle_counter_sig_20 : out std_logic;
+ toggle_counter_sig_21 : out std_logic;
+ toggle_counter_sig_22 : out std_logic;
+ toggle_counter_sig_23 : out std_logic;
+ toggle_counter_sig_24 : out std_logic;
+ h_enable_sig : in std_logic;
+ g : out std_logic;
+ b : out std_logic;
+ v_enable_sig : in std_logic;
+ r : out std_logic;
+ toggle_sig : out std_logic;
+ un6_dly_counter_0_x : in std_logic;
+ clk_pin_c : in std_logic);
+end vga_control;
+
+architecture beh of vga_control is
+ signal devclrn : std_logic := '1';
+ signal devpor : std_logic := '1';
+ signal devoe : std_logic := '0';
+ signal TOGGLE_COUNTER_SIG_COUT : std_logic_vector(18 downto 1);
+ signal UN2_TOGGLE_COUNTER_NEXT_COUT : std_logic_vector(0 to 0);
+ signal GND : std_logic ;
+ signal TOGGLE_SIG_0_0_0_G1 : std_logic ;
+ signal TOGGLE_SIG_83 : std_logic ;
+ signal B_NEXT_0_SQMUXA_7_4 : std_logic ;
+ signal B_NEXT_0_SQMUXA_7_5 : std_logic ;
+ signal TOGGLE_SIG_0_0_0_G1_2 : std_logic ;
+ signal UN1_TOGGLE_COUNTER_SIGLTO18 : std_logic ;
+ signal UN1_TOGGLE_COUNTER_SIGLTO15 : std_logic ;
+ signal UN5_V_ENABLELTO5 : std_logic ;
+ signal B_NEXT_0_SQMUXA_7_3 : std_logic ;
+ signal UN13_V_ENABLELTO6 : std_logic ;
+ signal B_NEXT_0_SQMUXA_7_4_A : std_logic ;
+ signal UN17_V_ENABLELTO3 : std_logic ;
+ signal B_NEXT_0_SQMUXA_7_2 : std_logic ;
+ signal UN9_V_ENABLELTO6 : std_logic ;
+ signal UN1_TOGGLE_COUNTER_SIGLTO12 : std_logic ;
+ signal UN5_V_ENABLELT2 : std_logic ;
+ signal UN1_TOGGLE_COUNTER_SIGLTO9 : std_logic ;
+ signal UN13_V_ENABLELTO4_0 : std_logic ;
+ signal UN9_V_ENABLELTO4 : std_logic ;
+ signal UN1_TOGGLE_COUNTER_SIGLT6 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_58 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_59 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_60 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_61 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_62 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_63 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_64 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_65 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_66 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_67 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_68 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_69 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_70 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_71 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_72 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_73 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_74 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_75 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_76 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_77 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_78 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_79 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_80 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_81 : std_logic ;
+ signal TOGGLE_COUNTER_SIG_82 : std_logic ;
+ signal VCC : std_logic ;
+ signal TOGGLE_SIG_0_0_0_G1_I : std_logic ;
+begin
+\TOGGLE_COUNTER_SIG_24_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff00")
+port map (
+regout => TOGGLE_COUNTER_SIG_82,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+ devpor => devpor,
+ devclrn => devclrn,
+ dataa => VCC,
+ datab => VCC,
+ datac => VCC,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_23_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff00")
+port map (
+regout => TOGGLE_COUNTER_SIG_81,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+ devpor => devpor,
+ devclrn => devclrn,
+ dataa => VCC,
+ datab => VCC,
+ datac => VCC,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_22_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff00")
+port map (
+regout => TOGGLE_COUNTER_SIG_80,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+ devpor => devpor,
+ devclrn => devclrn,
+ dataa => VCC,
+ datab => VCC,
+ datac => VCC,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_21_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff00")
+port map (
+regout => TOGGLE_COUNTER_SIG_79,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+ devpor => devpor,
+ devclrn => devclrn,
+ dataa => VCC,
+ datab => VCC,
+ datac => VCC,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_20_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a5a")
+port map (
+regout => TOGGLE_COUNTER_SIG_78,
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_78,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(18),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_19_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c6c")
+port map (
+regout => TOGGLE_COUNTER_SIG_77,
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_76,
+datab => TOGGLE_COUNTER_SIG_77,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(17),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_18_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_76,
+cout => TOGGLE_COUNTER_SIG_COUT(18),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_76,
+datab => TOGGLE_COUNTER_SIG_77,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(16),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_17_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_75,
+cout => TOGGLE_COUNTER_SIG_COUT(17),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_74,
+datab => TOGGLE_COUNTER_SIG_75,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(15),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_16_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_74,
+cout => TOGGLE_COUNTER_SIG_COUT(16),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_74,
+datab => TOGGLE_COUNTER_SIG_75,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(14),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_15_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_73,
+cout => TOGGLE_COUNTER_SIG_COUT(15),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_72,
+datab => TOGGLE_COUNTER_SIG_73,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(13),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_14_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_72,
+cout => TOGGLE_COUNTER_SIG_COUT(14),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_72,
+datab => TOGGLE_COUNTER_SIG_73,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(12),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_13_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_71,
+cout => TOGGLE_COUNTER_SIG_COUT(13),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_70,
+datab => TOGGLE_COUNTER_SIG_71,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(11),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_12_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_70,
+cout => TOGGLE_COUNTER_SIG_COUT(12),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_70,
+datab => TOGGLE_COUNTER_SIG_71,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(10),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_11_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_69,
+cout => TOGGLE_COUNTER_SIG_COUT(11),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_68,
+datab => TOGGLE_COUNTER_SIG_69,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(9),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_10_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_68,
+cout => TOGGLE_COUNTER_SIG_COUT(10),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_68,
+datab => TOGGLE_COUNTER_SIG_69,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(8),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_9_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_67,
+cout => TOGGLE_COUNTER_SIG_COUT(9),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_66,
+datab => TOGGLE_COUNTER_SIG_67,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(7),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_8_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_66,
+cout => TOGGLE_COUNTER_SIG_COUT(8),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_66,
+datab => TOGGLE_COUNTER_SIG_67,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(6),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_7_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_65,
+cout => TOGGLE_COUNTER_SIG_COUT(7),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_64,
+datab => TOGGLE_COUNTER_SIG_65,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(5),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_6_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_64,
+cout => TOGGLE_COUNTER_SIG_COUT(6),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_64,
+datab => TOGGLE_COUNTER_SIG_65,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(4),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_5_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_63,
+cout => TOGGLE_COUNTER_SIG_COUT(5),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_62,
+datab => TOGGLE_COUNTER_SIG_63,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(3),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_4_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_62,
+cout => TOGGLE_COUNTER_SIG_COUT(4),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_62,
+datab => TOGGLE_COUNTER_SIG_63,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(2),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_3_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+regout => TOGGLE_COUNTER_SIG_61,
+cout => TOGGLE_COUNTER_SIG_COUT(3),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_60,
+datab => TOGGLE_COUNTER_SIG_61,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => TOGGLE_COUNTER_SIG_COUT(1),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_2_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+regout => TOGGLE_COUNTER_SIG_60,
+cout => TOGGLE_COUNTER_SIG_COUT(2),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_60,
+datab => TOGGLE_COUNTER_SIG_61,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+cin => UN2_TOGGLE_COUNTER_NEXT_COUT(0),
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_1_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "6688")
+port map (
+regout => TOGGLE_COUNTER_SIG_59,
+cout => TOGGLE_COUNTER_SIG_COUT(1),
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_58,
+datab => TOGGLE_COUNTER_SIG_59,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\TOGGLE_COUNTER_SIG_0_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "5555")
+port map (
+regout => TOGGLE_COUNTER_SIG_58,
+clk => clk_pin_c,
+dataa => TOGGLE_COUNTER_SIG_58,
+aclr => un6_dly_counter_0_x,
+sclr => TOGGLE_SIG_0_0_0_G1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datac => VCC,
+ datad => VCC,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+TOGGLE_SIG_Z146: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "9999")
+port map (
+regout => TOGGLE_SIG_83,
+clk => clk_pin_c,
+dataa => TOGGLE_SIG_83,
+datab => TOGGLE_SIG_0_0_0_G1,
+aclr => un6_dly_counter_0_x,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+R_Z147: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8000")
+port map (
+regout => r,
+clk => clk_pin_c,
+dataa => TOGGLE_SIG_83,
+datab => v_enable_sig,
+datac => B_NEXT_0_SQMUXA_7_4,
+datad => B_NEXT_0_SQMUXA_7_5,
+aclr => un6_dly_counter_0_x,
+ devpor => devpor,
+ devclrn => devclrn,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+B_Z148: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "4000")
+port map (
+regout => b,
+clk => clk_pin_c,
+dataa => TOGGLE_SIG_83,
+datab => v_enable_sig,
+datac => B_NEXT_0_SQMUXA_7_4,
+datad => B_NEXT_0_SQMUXA_7_5,
+aclr => un6_dly_counter_0_x,
+ devpor => devpor,
+ devclrn => devclrn,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+G_Z149: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff00")
+port map (
+regout => g,
+clk => clk_pin_c,
+datad => GND,
+aclr => un6_dly_counter_0_x,
+ devpor => devpor,
+ devclrn => devclrn,
+ dataa => VCC,
+ datab => VCC,
+ datac => VCC,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+TOGGLE_SIG_0_0_0_G1_Z150: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0703")
+port map (
+combout => TOGGLE_SIG_0_0_0_G1,
+dataa => TOGGLE_COUNTER_SIG_77,
+datab => TOGGLE_COUNTER_SIG_78,
+datac => TOGGLE_SIG_0_0_0_G1_2,
+datad => UN1_TOGGLE_COUNTER_SIGLTO18,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO18: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7f77")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLTO18,
+dataa => TOGGLE_COUNTER_SIG_75,
+datab => TOGGLE_COUNTER_SIG_76,
+datac => TOGGLE_COUNTER_SIG_74,
+datad => UN1_TOGGLE_COUNTER_SIGLTO15,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+B_NEXT_0_SQMUXA_7_5_Z152: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7f00")
+port map (
+combout => B_NEXT_0_SQMUXA_7_5,
+dataa => column_counter_sig_6,
+datab => column_counter_sig_7,
+datac => UN5_V_ENABLELTO5,
+datad => B_NEXT_0_SQMUXA_7_3,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+B_NEXT_0_SQMUXA_7_4_Z153: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ef23")
+port map (
+combout => B_NEXT_0_SQMUXA_7_4,
+dataa => line_counter_sig_8,
+datab => line_counter_sig_7,
+datac => UN13_V_ENABLELTO6,
+datad => B_NEXT_0_SQMUXA_7_4_A,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+B_NEXT_0_SQMUXA_7_4_A_Z154: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0f1f")
+port map (
+combout => B_NEXT_0_SQMUXA_7_4_A,
+dataa => line_counter_sig_4,
+datab => line_counter_sig_5,
+datac => line_counter_sig_6,
+datad => UN17_V_ENABLELTO3,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+B_NEXT_0_SQMUXA_7_3_Z155: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "e0f0")
+port map (
+combout => B_NEXT_0_SQMUXA_7_3,
+dataa => column_counter_sig_7,
+datab => column_counter_sig_9,
+datac => B_NEXT_0_SQMUXA_7_2,
+datad => UN9_V_ENABLELTO6,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO15: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff7f")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLTO15,
+dataa => TOGGLE_COUNTER_SIG_71,
+datab => TOGGLE_COUNTER_SIG_72,
+datac => TOGGLE_COUNTER_SIG_73,
+datad => UN1_TOGGLE_COUNTER_SIGLTO12,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+DRAW_SQUARE_NEXT_UN5_V_ENABLELTO5: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "feee")
+port map (
+combout => UN5_V_ENABLELTO5,
+dataa => column_counter_sig_4,
+datab => column_counter_sig_5,
+datac => column_counter_sig_3,
+datad => UN5_V_ENABLELT2,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO12: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0100")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLTO12,
+dataa => TOGGLE_COUNTER_SIG_68,
+datab => TOGGLE_COUNTER_SIG_69,
+datac => TOGGLE_COUNTER_SIG_70,
+datad => UN1_TOGGLE_COUNTER_SIGLTO9,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+DRAW_SQUARE_NEXT_UN13_V_ENABLELTO6: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7f77")
+port map (
+combout => UN13_V_ENABLELTO6,
+dataa => line_counter_sig_5,
+datab => line_counter_sig_6,
+datac => line_counter_sig_3,
+datad => UN13_V_ENABLELTO4_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+DRAW_SQUARE_NEXT_UN9_V_ENABLELTO6: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "f7f7")
+port map (
+combout => UN9_V_ENABLELTO6,
+dataa => column_counter_sig_5,
+datab => column_counter_sig_6,
+datac => UN9_V_ENABLELTO4,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO9: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7f77")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLTO9,
+dataa => TOGGLE_COUNTER_SIG_66,
+datab => TOGGLE_COUNTER_SIG_67,
+datac => TOGGLE_COUNTER_SIG_65,
+datad => UN1_TOGGLE_COUNTER_SIGLT6,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+DRAW_SQUARE_NEXT_UN17_V_ENABLELTO3: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "fe00")
+port map (
+combout => UN17_V_ENABLELTO3,
+dataa => line_counter_sig_1,
+datab => line_counter_sig_2,
+datac => line_counter_sig_0,
+datad => line_counter_sig_3,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+TOGGLE_SIG_0_0_0_G1_2_Z163: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "fffe")
+port map (
+combout => TOGGLE_SIG_0_0_0_G1_2,
+dataa => TOGGLE_COUNTER_SIG_81,
+datab => TOGGLE_COUNTER_SIG_82,
+datac => TOGGLE_COUNTER_SIG_79,
+datad => TOGGLE_COUNTER_SIG_80,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+B_NEXT_0_SQMUXA_7_2_Z164: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0004")
+port map (
+combout => B_NEXT_0_SQMUXA_7_2,
+dataa => column_counter_sig_8,
+datab => h_enable_sig,
+datac => column_counter_sig_9,
+datad => line_counter_sig_8,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+DRAW_SQUARE_NEXT_UN9_V_ENABLELTO4: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0101")
+port map (
+combout => UN9_V_ENABLELTO4,
+dataa => column_counter_sig_3,
+datab => column_counter_sig_4,
+datac => column_counter_sig_2,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+DRAW_SQUARE_NEXT_UN5_V_ENABLELT2: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "fefe")
+port map (
+combout => UN5_V_ENABLELT2,
+dataa => column_counter_sig_1,
+datab => column_counter_sig_2,
+datac => column_counter_sig_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+DRAW_SQUARE_NEXT_UN13_V_ENABLELTO4_0: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "1111")
+port map (
+combout => UN13_V_ENABLELTO4_0,
+dataa => line_counter_sig_4,
+datab => line_counter_sig_2,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLT6: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7777")
+port map (
+combout => UN1_TOGGLE_COUNTER_SIGLT6,
+dataa => TOGGLE_COUNTER_SIG_64,
+datab => TOGGLE_COUNTER_SIG_63,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\UN2_TOGGLE_COUNTER_NEXT_0_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "5588")
+port map (
+cout => UN2_TOGGLE_COUNTER_NEXT_COUT(0),
+dataa => TOGGLE_COUNTER_SIG_58,
+datab => TOGGLE_COUNTER_SIG_59,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+GND <= '0';
+VCC <= '1';
+TOGGLE_SIG_0_0_0_G1_I <= not TOGGLE_SIG_0_0_0_G1;
+toggle_counter_sig_0 <= TOGGLE_COUNTER_SIG_58;
+toggle_counter_sig_1 <= TOGGLE_COUNTER_SIG_59;
+toggle_counter_sig_2 <= TOGGLE_COUNTER_SIG_60;
+toggle_counter_sig_3 <= TOGGLE_COUNTER_SIG_61;
+toggle_counter_sig_4 <= TOGGLE_COUNTER_SIG_62;
+toggle_counter_sig_5 <= TOGGLE_COUNTER_SIG_63;
+toggle_counter_sig_6 <= TOGGLE_COUNTER_SIG_64;
+toggle_counter_sig_7 <= TOGGLE_COUNTER_SIG_65;
+toggle_counter_sig_8 <= TOGGLE_COUNTER_SIG_66;
+toggle_counter_sig_9 <= TOGGLE_COUNTER_SIG_67;
+toggle_counter_sig_10 <= TOGGLE_COUNTER_SIG_68;
+toggle_counter_sig_11 <= TOGGLE_COUNTER_SIG_69;
+toggle_counter_sig_12 <= TOGGLE_COUNTER_SIG_70;
+toggle_counter_sig_13 <= TOGGLE_COUNTER_SIG_71;
+toggle_counter_sig_14 <= TOGGLE_COUNTER_SIG_72;
+toggle_counter_sig_15 <= TOGGLE_COUNTER_SIG_73;
+toggle_counter_sig_16 <= TOGGLE_COUNTER_SIG_74;
+toggle_counter_sig_17 <= TOGGLE_COUNTER_SIG_75;
+toggle_counter_sig_18 <= TOGGLE_COUNTER_SIG_76;
+toggle_counter_sig_19 <= TOGGLE_COUNTER_SIG_77;
+toggle_counter_sig_20 <= TOGGLE_COUNTER_SIG_78;
+toggle_counter_sig_21 <= TOGGLE_COUNTER_SIG_79;
+toggle_counter_sig_22 <= TOGGLE_COUNTER_SIG_80;
+toggle_counter_sig_23 <= TOGGLE_COUNTER_SIG_81;
+toggle_counter_sig_24 <= TOGGLE_COUNTER_SIG_82;
+toggle_sig <= TOGGLE_SIG_83;
+end beh;
+
+--
+library ieee, stratix;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+use stratix.stratix_components.all;
+
+entity vga_driver is
+port(
+line_counter_sig_0 : out std_logic;
+line_counter_sig_1 : out std_logic;
+line_counter_sig_2 : out std_logic;
+line_counter_sig_3 : out std_logic;
+line_counter_sig_4 : out std_logic;
+line_counter_sig_5 : out std_logic;
+line_counter_sig_6 : out std_logic;
+line_counter_sig_7 : out std_logic;
+line_counter_sig_8 : out std_logic;
+dly_counter_1 : in std_logic;
+dly_counter_0 : in std_logic;
+vsync_state_2 : out std_logic;
+vsync_state_5 : out std_logic;
+vsync_state_3 : out std_logic;
+vsync_state_6 : out std_logic;
+vsync_state_4 : out std_logic;
+vsync_state_1 : out std_logic;
+vsync_state_0 : out std_logic;
+hsync_state_2 : out std_logic;
+hsync_state_4 : out std_logic;
+hsync_state_0 : out std_logic;
+hsync_state_5 : out std_logic;
+hsync_state_1 : out std_logic;
+hsync_state_3 : out std_logic;
+hsync_state_6 : out std_logic;
+column_counter_sig_0 : out std_logic;
+column_counter_sig_1 : out std_logic;
+column_counter_sig_2 : out std_logic;
+column_counter_sig_3 : out std_logic;
+column_counter_sig_4 : out std_logic;
+column_counter_sig_5 : out std_logic;
+column_counter_sig_6 : out std_logic;
+column_counter_sig_7 : out std_logic;
+column_counter_sig_8 : out std_logic;
+column_counter_sig_9 : out std_logic;
+vsync_counter_9 : out std_logic;
+vsync_counter_8 : out std_logic;
+vsync_counter_7 : out std_logic;
+vsync_counter_6 : out std_logic;
+vsync_counter_5 : out std_logic;
+vsync_counter_4 : out std_logic;
+vsync_counter_3 : out std_logic;
+vsync_counter_2 : out std_logic;
+vsync_counter_1 : out std_logic;
+vsync_counter_0 : out std_logic;
+hsync_counter_9 : out std_logic;
+hsync_counter_8 : out std_logic;
+hsync_counter_7 : out std_logic;
+hsync_counter_6 : out std_logic;
+hsync_counter_5 : out std_logic;
+hsync_counter_4 : out std_logic;
+hsync_counter_3 : out std_logic;
+hsync_counter_2 : out std_logic;
+hsync_counter_1 : out std_logic;
+hsync_counter_0 : out std_logic;
+d_set_vsync_counter : out std_logic;
+v_sync : out std_logic;
+h_sync : out std_logic;
+h_enable_sig : out std_logic;
+v_enable_sig : out std_logic;
+reset_pin_c : in std_logic;
+un6_dly_counter_0_x : out std_logic;
+d_set_hsync_counter : out std_logic;
+clk_pin_c : in std_logic);
+end vga_driver;
+
+architecture beh of vga_driver is
+signal devclrn : std_logic := '1';
+signal devpor : std_logic := '1';
+signal devoe : std_logic := '0';
+signal HSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
+signal VSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
+signal UN2_COLUMN_COUNTER_NEXT_COMBOUT : std_logic_vector(9 downto 1);
+signal UN1_LINE_COUNTER_SIG_COMBOUT : std_logic_vector(9 downto 1);
+signal UN1_LINE_COUNTER_SIG_COUT : std_logic_vector(7 downto 1);
+signal UN1_LINE_COUNTER_SIG_A_COUT : std_logic_vector(1 to 1);
+signal UN2_COLUMN_COUNTER_NEXT_COUT : std_logic_vector(7 downto 0);
+signal HSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
+signal G_2_I : std_logic ;
+signal UN9_HSYNC_COUNTERLT9 : std_logic ;
+signal VSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
+signal G_16_I : std_logic ;
+signal UN9_VSYNC_COUNTERLT9 : std_logic ;
+signal UN10_COLUMN_COUNTER_SIGLTO9 : std_logic ;
+signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
+signal \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\ : std_logic ;
+signal UN6_DLY_COUNTER_0_X_56 : std_logic ;
+signal VSYNC_STATE_NEXT_2_SQMUXA : std_logic ;
+signal UN12_VSYNC_COUNTER_7 : std_logic ;
+signal UN13_VSYNC_COUNTER_4 : std_logic ;
+signal UN10_LINE_COUNTER_SIGLTO8 : std_logic ;
+signal LINE_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
+signal V_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
+signal H_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
+signal H_SYNC_1_0_0_0_G1 : std_logic ;
+signal V_SYNC_1_0_0_0_G1 : std_logic ;
+signal UN14_VSYNC_COUNTER_8 : std_logic ;
+signal \HSYNC_STATE_3_0_0_0__G0_0\ : std_logic ;
+signal UN10_HSYNC_COUNTER_3 : std_logic ;
+signal UN10_HSYNC_COUNTER_1 : std_logic ;
+signal UN10_HSYNC_COUNTER_4 : std_logic ;
+signal UN12_HSYNC_COUNTER : std_logic ;
+signal UN11_HSYNC_COUNTER_2 : std_logic ;
+signal UN11_HSYNC_COUNTER_3 : std_logic ;
+signal UN13_HSYNC_COUNTER : std_logic ;
+signal VSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
+signal VSYNC_STATE_NEXT_1_SQMUXA_3 : std_logic ;
+signal UN1_VSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
+signal HSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
+signal HSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
+signal UN1_HSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
+signal UN12_VSYNC_COUNTER_6 : std_logic ;
+signal UN15_VSYNC_COUNTER_4 : std_logic ;
+signal VSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
+signal UN10_LINE_COUNTER_SIGLTO5 : std_logic ;
+signal UN10_COLUMN_COUNTER_SIGLT6 : std_logic ;
+signal UN13_HSYNC_COUNTER_2 : std_logic ;
+signal UN13_HSYNC_COUNTER_7 : std_logic ;
+signal UN9_HSYNC_COUNTERLT9_3 : std_logic ;
+signal UN9_VSYNC_COUNTERLT9_5 : std_logic ;
+signal UN9_VSYNC_COUNTERLT9_6 : std_logic ;
+signal UN12_HSYNC_COUNTER_3 : std_logic ;
+signal UN12_HSYNC_COUNTER_4 : std_logic ;
+signal UN10_LINE_COUNTER_SIGLT4_2 : std_logic ;
+signal UN15_VSYNC_COUNTER_3 : std_logic ;
+signal UN13_VSYNC_COUNTER_3 : std_logic ;
+signal UN10_COLUMN_COUNTER_SIGLT6_4 : std_logic ;
+signal D_SET_HSYNC_COUNTER_57 : std_logic ;
+signal V_SYNC_54 : std_logic ;
+signal UN1_VSYNC_STATE_2_0 : std_logic ;
+signal H_SYNC_55 : std_logic ;
+signal UN1_HSYNC_STATE_3_0 : std_logic ;
+signal D_SET_VSYNC_COUNTER_53 : std_logic ;
+signal VCC : std_logic ;
+signal LINE_COUNTER_SIG_0_0 : std_logic ;
+signal LINE_COUNTER_SIG_1_0 : std_logic ;
+signal LINE_COUNTER_SIG_2_0 : std_logic ;
+signal LINE_COUNTER_SIG_3_0 : std_logic ;
+signal LINE_COUNTER_SIG_4_0 : std_logic ;
+signal LINE_COUNTER_SIG_5_0 : std_logic ;
+signal LINE_COUNTER_SIG_6_0 : std_logic ;
+signal LINE_COUNTER_SIG_7_0 : std_logic ;
+signal LINE_COUNTER_SIG_8_0 : std_logic ;
+signal VSYNC_STATE_9 : std_logic ;
+signal VSYNC_STATE_10 : std_logic ;
+signal VSYNC_STATE_11 : std_logic ;
+signal VSYNC_STATE_12 : std_logic ;
+signal VSYNC_STATE_13 : std_logic ;
+signal VSYNC_STATE_14 : std_logic ;
+signal VSYNC_STATE_15 : std_logic ;
+signal HSYNC_STATE_16 : std_logic ;
+signal HSYNC_STATE_17 : std_logic ;
+signal HSYNC_STATE_18 : std_logic ;
+signal HSYNC_STATE_19 : std_logic ;
+signal HSYNC_STATE_20 : std_logic ;
+signal HSYNC_STATE_21 : std_logic ;
+signal HSYNC_STATE_22 : std_logic ;
+signal COLUMN_COUNTER_SIG_23 : std_logic ;
+signal COLUMN_COUNTER_SIG_24 : std_logic ;
+signal COLUMN_COUNTER_SIG_25 : std_logic ;
+signal COLUMN_COUNTER_SIG_26 : std_logic ;
+signal COLUMN_COUNTER_SIG_27 : std_logic ;
+signal COLUMN_COUNTER_SIG_28 : std_logic ;
+signal COLUMN_COUNTER_SIG_29 : std_logic ;
+signal COLUMN_COUNTER_SIG_30 : std_logic ;
+signal COLUMN_COUNTER_SIG_31 : std_logic ;
+signal COLUMN_COUNTER_SIG_32 : std_logic ;
+signal VSYNC_COUNTER_33 : std_logic ;
+signal VSYNC_COUNTER_34 : std_logic ;
+signal VSYNC_COUNTER_35 : std_logic ;
+signal VSYNC_COUNTER_36 : std_logic ;
+signal VSYNC_COUNTER_37 : std_logic ;
+signal VSYNC_COUNTER_38 : std_logic ;
+signal VSYNC_COUNTER_39 : std_logic ;
+signal VSYNC_COUNTER_40 : std_logic ;
+signal VSYNC_COUNTER_41 : std_logic ;
+signal VSYNC_COUNTER_42 : std_logic ;
+signal HSYNC_COUNTER_43 : std_logic ;
+signal HSYNC_COUNTER_44 : std_logic ;
+signal HSYNC_COUNTER_45 : std_logic ;
+signal HSYNC_COUNTER_46 : std_logic ;
+signal HSYNC_COUNTER_47 : std_logic ;
+signal HSYNC_COUNTER_48 : std_logic ;
+signal HSYNC_COUNTER_49 : std_logic ;
+signal HSYNC_COUNTER_50 : std_logic ;
+signal HSYNC_COUNTER_51 : std_logic ;
+signal HSYNC_COUNTER_52 : std_logic ;
+signal GND : std_logic ;
+signal LINE_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
+signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
+signal G_16_I_I : std_logic ;
+signal UN9_VSYNC_COUNTERLT9_I : std_logic ;
+signal G_2_I_I : std_logic ;
+signal UN9_HSYNC_COUNTERLT9_I : std_logic ;
+begin
+\HSYNC_COUNTER_0_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "55aa")
+port map (
+regout => HSYNC_COUNTER_52,
+cout => HSYNC_COUNTER_COUT(0),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_52,
+datab => VCC,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_1_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_51,
+cout => HSYNC_COUNTER_COUT(1),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_51,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(0),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_2_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_50,
+cout => HSYNC_COUNTER_COUT(2),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_50,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(1),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_3_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_49,
+cout => HSYNC_COUNTER_COUT(3),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_49,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(2),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_4_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_48,
+cout => HSYNC_COUNTER_COUT(4),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_48,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(3),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_5_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_47,
+cout => HSYNC_COUNTER_COUT(5),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_47,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(4),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_6_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_46,
+cout => HSYNC_COUNTER_COUT(6),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_46,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(5),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_7_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_45,
+cout => HSYNC_COUNTER_COUT(7),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(6),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_8_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => HSYNC_COUNTER_44,
+cout => HSYNC_COUNTER_COUT(8),
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_44,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(7),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\HSYNC_COUNTER_9_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a5a")
+port map (
+regout => HSYNC_COUNTER_43,
+clk => clk_pin_c,
+dataa => HSYNC_COUNTER_43,
+datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_2_I_I,
+sload => UN9_HSYNC_COUNTERLT9_I,
+cin => HSYNC_COUNTER_COUT(8),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_0_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "6688")
+port map (
+regout => VSYNC_COUNTER_42,
+cout => VSYNC_COUNTER_COUT(0),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_42,
+datab => D_SET_HSYNC_COUNTER_57,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_1_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_41,
+cout => VSYNC_COUNTER_COUT(1),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_41,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(0),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_2_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_40,
+cout => VSYNC_COUNTER_COUT(2),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_40,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(1),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_3_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_39,
+cout => VSYNC_COUNTER_COUT(3),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_39,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(2),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_4_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_38,
+cout => VSYNC_COUNTER_COUT(4),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_38,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(3),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_5_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_37,
+cout => VSYNC_COUNTER_COUT(5),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_37,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(4),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_6_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_36,
+cout => VSYNC_COUNTER_COUT(6),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_36,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(5),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_7_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_35,
+cout => VSYNC_COUNTER_COUT(7),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_35,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(6),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_8_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "reg_and_comb",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5aa0")
+port map (
+regout => VSYNC_COUNTER_34,
+cout => VSYNC_COUNTER_COUT(8),
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_34,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(7),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\VSYNC_COUNTER_9_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a5a")
+port map (
+regout => VSYNC_COUNTER_33,
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_33,
+datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
+sclr => G_16_I_I,
+sload => UN9_VSYNC_COUNTERLT9_I,
+cin => VSYNC_COUNTER_COUT(8),
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datad => VCC,
+ aclr => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_9_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_32,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_8_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8080")
+port map (
+regout => COLUMN_COUNTER_SIG_31,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
+ devpor => devpor,
+ devclrn => devclrn,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_7_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8080")
+port map (
+regout => COLUMN_COUNTER_SIG_30,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
+ devpor => devpor,
+ devclrn => devclrn,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_6_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_29,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_5_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_28,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_4_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_27,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_3_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_26,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_2_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_25,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_1_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "bbbb")
+port map (
+regout => COLUMN_COUNTER_SIG_24,
+clk => clk_pin_c,
+dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\COLUMN_COUNTER_SIG_0_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "7777")
+port map (
+regout => COLUMN_COUNTER_SIG_23,
+clk => clk_pin_c,
+dataa => COLUMN_COUNTER_SIG_23,
+datab => UN10_COLUMN_COUNTER_SIGLTO9,
+sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_STATE_6_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff00")
+port map (
+regout => HSYNC_STATE_22,
+clk => clk_pin_c,
+datad => UN6_DLY_COUNTER_0_X_56,
+ devpor => devpor,
+ devclrn => devclrn,
+ dataa => VCC,
+ datab => VCC,
+ datac => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_STATE_0_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0cae")
+port map (
+regout => VSYNC_STATE_15,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_15,
+datab => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
+datac => UN6_DLY_COUNTER_0_X_56,
+datad => VSYNC_STATE_NEXT_2_SQMUXA,
+ devpor => devpor,
+ devclrn => devclrn,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_STATE_1_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0080")
+port map (
+regout => VSYNC_STATE_14,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_13,
+datab => UN12_VSYNC_COUNTER_7,
+datac => UN13_VSYNC_COUNTER_4,
+datad => UN6_DLY_COUNTER_0_X_56,
+ devpor => devpor,
+ devclrn => devclrn,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_STATE_6_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_and_comb",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7f7f")
+port map (
+combout => UN6_DLY_COUNTER_0_X_56,
+regout => VSYNC_STATE_12,
+clk => clk_pin_c,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+ devpor => devpor,
+ devclrn => devclrn,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_8_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(9),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_7_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(8),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_6_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(7),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8080")
+port map (
+regout => LINE_COUNTER_SIG_5_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(6),
+datac => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
+ devpor => devpor,
+ devclrn => devclrn,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_4_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(5),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_3_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(4),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_2_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(3),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "dddd")
+port map (
+regout => LINE_COUNTER_SIG_1_0,
+clk => clk_pin_c,
+dataa => UN10_LINE_COUNTER_SIGLTO8,
+datab => UN1_LINE_COUNTER_SIG_COMBOUT(2),
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\LINE_COUNTER_SIG_0_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "bbbb")
+port map (
+regout => LINE_COUNTER_SIG_0_0,
+clk => clk_pin_c,
+dataa => UN1_LINE_COUNTER_SIG_COMBOUT(1),
+datab => UN10_LINE_COUNTER_SIGLTO8,
+sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+V_ENABLE_SIG_Z283: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "eeee")
+port map (
+regout => v_enable_sig,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_21,
+datab => HSYNC_STATE_20,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+H_ENABLE_SIG_Z284: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "eeee")
+port map (
+regout => h_enable_sig,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_11,
+datab => VSYNC_STATE_14,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+H_SYNC_Z285: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff7f")
+port map (
+regout => H_SYNC_55,
+clk => clk_pin_c,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => H_SYNC_1_0_0_0_G1,
+ devpor => devpor,
+ devclrn => devclrn,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+V_SYNC_Z286: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff7f")
+port map (
+regout => V_SYNC_54,
+clk => clk_pin_c,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => V_SYNC_1_0_0_0_G1,
+ devpor => devpor,
+ devclrn => devclrn,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_STATE_5_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "eeee")
+port map (
+regout => VSYNC_STATE_10,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_12,
+datab => VSYNC_STATE_15,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => VSYNC_STATE_NEXT_2_SQMUXA,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_STATE_4_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "2000")
+port map (
+regout => VSYNC_STATE_13,
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_STATE_10,
+datad => UN14_VSYNC_COUNTER_8,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => VSYNC_STATE_NEXT_2_SQMUXA,
+ devpor => devpor,
+ devclrn => devclrn,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_STATE_3_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "aaaa")
+port map (
+regout => VSYNC_STATE_11,
+clk => clk_pin_c,
+dataa => VSYNC_STATE_14,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => VSYNC_STATE_NEXT_2_SQMUXA,
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_STATE_2_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "8000")
+port map (
+regout => VSYNC_STATE_9,
+clk => clk_pin_c,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_STATE_11,
+datad => UN14_VSYNC_COUNTER_8,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => VSYNC_STATE_NEXT_2_SQMUXA,
+ devpor => devpor,
+ devclrn => devclrn,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_STATE_5_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "eeee")
+port map (
+regout => HSYNC_STATE_19,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_22,
+datab => HSYNC_STATE_18,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_STATE_4_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "8000")
+port map (
+regout => HSYNC_STATE_17,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_19,
+datab => UN10_HSYNC_COUNTER_3,
+datac => UN10_HSYNC_COUNTER_1,
+datad => UN10_HSYNC_COUNTER_4,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+ devpor => devpor,
+ devclrn => devclrn,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_STATE_3_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "aaaa")
+port map (
+regout => HSYNC_STATE_21,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_20,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+ devpor => devpor,
+ devclrn => devclrn,
+ datab => VCC,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_STATE_2_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "8888")
+port map (
+regout => HSYNC_STATE_16,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_21,
+datab => UN12_HSYNC_COUNTER,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_STATE_1_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "8000")
+port map (
+regout => HSYNC_STATE_20,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_17,
+datab => UN11_HSYNC_COUNTER_2,
+datac => UN10_HSYNC_COUNTER_1,
+datad => UN11_HSYNC_COUNTER_3,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+ devpor => devpor,
+ devclrn => devclrn,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_STATE_0_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "on",
+ sum_lutc_input => "datac",
+ lut_mask => "8888")
+port map (
+regout => HSYNC_STATE_18,
+clk => clk_pin_c,
+dataa => HSYNC_STATE_16,
+datab => UN13_HSYNC_COUNTER,
+sclr => UN6_DLY_COUNTER_0_X_56,
+ena => \HSYNC_STATE_3_0_0_0__G0_0\,
+ devpor => devpor,
+ devclrn => devclrn,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sload => GND,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_STATE_NEXT_2_SQMUXA_Z297: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "aaab")
+port map (
+combout => VSYNC_STATE_NEXT_2_SQMUXA,
+dataa => UN6_DLY_COUNTER_0_X_56,
+datab => VSYNC_STATE_NEXT_1_SQMUXA_1,
+datac => VSYNC_STATE_NEXT_1_SQMUXA_3,
+datad => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\HSYNC_STATE_3_0_0_0__G0_0_Z298\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "f0f1")
+port map (
+combout => \HSYNC_STATE_3_0_0_0__G0_0\,
+dataa => HSYNC_STATE_NEXT_1_SQMUXA_1,
+datab => HSYNC_STATE_NEXT_1_SQMUXA_2,
+datac => UN6_DLY_COUNTER_0_X_56,
+datad => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+UN1_HSYNC_STATE_NEXT_1_SQMUXA_0_Z299: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0ace")
+port map (
+combout => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
+dataa => HSYNC_STATE_16,
+datab => HSYNC_STATE_21,
+datac => UN13_HSYNC_COUNTER,
+datad => UN12_HSYNC_COUNTER,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+UN1_VSYNC_STATE_NEXT_1_SQMUXA_0_Z300: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff2a")
+port map (
+combout => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
+dataa => VSYNC_STATE_9,
+datab => UN12_VSYNC_COUNTER_6,
+datac => UN15_VSYNC_COUNTER_4,
+datad => VSYNC_STATE_NEXT_1_SQMUXA_2,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\VSYNC_STATE_3_IV_0_0__G0_0_A3_0_Z301\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8080")
+port map (
+combout => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
+dataa => VSYNC_STATE_9,
+datab => UN12_VSYNC_COUNTER_6,
+datac => UN15_VSYNC_COUNTER_4,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO8: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff7f")
+port map (
+combout => UN10_LINE_COUNTER_SIGLTO8,
+dataa => LINE_COUNTER_SIG_6_0,
+datab => LINE_COUNTER_SIG_7_0,
+datac => LINE_COUNTER_SIG_8_0,
+datad => UN10_LINE_COUNTER_SIGLTO5,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+G_2: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0f1f")
+port map (
+combout => G_2_I,
+dataa => HSYNC_STATE_18,
+datab => HSYNC_STATE_22,
+datac => UN9_HSYNC_COUNTERLT9,
+datad => UN6_DLY_COUNTER_0_X_56,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_STATE_NEXT_1_SQMUXA_1_Z304: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "d0f0")
+port map (
+combout => VSYNC_STATE_NEXT_1_SQMUXA_1,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_STATE_10,
+datad => UN14_VSYNC_COUNTER_8,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_STATE_NEXT_1_SQMUXA_2_Z305: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "2a2a")
+port map (
+combout => VSYNC_STATE_NEXT_1_SQMUXA_2,
+dataa => VSYNC_STATE_13,
+datab => UN12_VSYNC_COUNTER_7,
+datac => UN13_VSYNC_COUNTER_4,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_STATE_NEXT_1_SQMUXA_3_Z306: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "70f0")
+port map (
+combout => VSYNC_STATE_NEXT_1_SQMUXA_3,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_STATE_11,
+datad => UN14_VSYNC_COUNTER_8,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+G_16: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0f1f")
+port map (
+combout => G_16_I,
+dataa => VSYNC_STATE_15,
+datab => VSYNC_STATE_12,
+datac => UN9_VSYNC_COUNTERLT9,
+datad => UN6_DLY_COUNTER_0_X_56,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLTO9: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "1f0f")
+port map (
+combout => UN10_COLUMN_COUNTER_SIGLTO9,
+dataa => COLUMN_COUNTER_SIG_30,
+datab => COLUMN_COUNTER_SIG_31,
+datac => COLUMN_COUNTER_SIG_32,
+datad => UN10_COLUMN_COUNTER_SIGLT6,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_STATE_NEXT_1_SQMUXA_2_Z309: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "2aaa")
+port map (
+combout => HSYNC_STATE_NEXT_1_SQMUXA_2,
+dataa => HSYNC_STATE_17,
+datab => UN11_HSYNC_COUNTER_2,
+datac => UN10_HSYNC_COUNTER_1,
+datad => UN11_HSYNC_COUNTER_3,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_STATE_NEXT_1_SQMUXA_1_Z310: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "2aaa")
+port map (
+combout => HSYNC_STATE_NEXT_1_SQMUXA_1,
+dataa => HSYNC_STATE_19,
+datab => UN10_HSYNC_COUNTER_3,
+datac => UN10_HSYNC_COUNTER_1,
+datad => UN10_HSYNC_COUNTER_4,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "1000")
+port map (
+combout => UN13_HSYNC_COUNTER,
+dataa => HSYNC_COUNTER_46,
+datab => HSYNC_COUNTER_45,
+datac => UN13_HSYNC_COUNTER_2,
+datad => UN13_HSYNC_COUNTER_7,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "f7ff")
+port map (
+combout => UN9_HSYNC_COUNTERLT9,
+dataa => HSYNC_COUNTER_44,
+datab => HSYNC_COUNTER_43,
+datac => UN9_HSYNC_COUNTERLT9_3,
+datad => UN13_HSYNC_COUNTER_7,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "fff7")
+port map (
+combout => UN9_VSYNC_COUNTERLT9,
+dataa => VSYNC_COUNTER_38,
+datab => VSYNC_COUNTER_37,
+datac => UN9_VSYNC_COUNTERLT9_5,
+datad => UN9_VSYNC_COUNTERLT9_6,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8000")
+port map (
+combout => UN12_HSYNC_COUNTER,
+dataa => HSYNC_COUNTER_52,
+datab => HSYNC_COUNTER_51,
+datac => UN12_HSYNC_COUNTER_3,
+datad => UN12_HSYNC_COUNTER_4,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO5: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0f07")
+port map (
+combout => UN10_LINE_COUNTER_SIGLTO5,
+dataa => LINE_COUNTER_SIG_1_0,
+datab => LINE_COUNTER_SIG_2_0,
+datac => LINE_COUNTER_SIG_5_0,
+datad => UN10_LINE_COUNTER_SIGLT4_2,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_4: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "1010")
+port map (
+combout => UN15_VSYNC_COUNTER_4,
+dataa => VSYNC_COUNTER_41,
+datab => VSYNC_COUNTER_38,
+datac => UN15_VSYNC_COUNTER_3,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_4: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8080")
+port map (
+combout => UN13_VSYNC_COUNTER_4,
+dataa => VSYNC_COUNTER_42,
+datab => VSYNC_COUNTER_37,
+datac => UN13_VSYNC_COUNTER_3,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ff7f")
+port map (
+combout => UN10_COLUMN_COUNTER_SIGLT6,
+dataa => COLUMN_COUNTER_SIG_27,
+datab => COLUMN_COUNTER_SIG_29,
+datac => COLUMN_COUNTER_SIG_28,
+datad => UN10_COLUMN_COUNTER_SIGLT6_4,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_COUNTER_NEXT_1_SQMUXA_Z319: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0080")
+port map (
+combout => HSYNC_COUNTER_NEXT_1_SQMUXA,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => D_SET_HSYNC_COUNTER_57,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_FSM_NEXT_UN14_VSYNC_COUNTER_8: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8888")
+port map (
+combout => UN14_VSYNC_COUNTER_8,
+dataa => UN12_VSYNC_COUNTER_6,
+datab => UN12_VSYNC_COUNTER_7,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+LINE_COUNTER_NEXT_0_SQMUXA_1_1_Z321: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0080")
+port map (
+combout => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => VSYNC_STATE_14,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+V_SYNC_1_0_0_0_G1_Z322: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ccd8")
+port map (
+combout => V_SYNC_1_0_0_0_G1,
+dataa => VSYNC_STATE_9,
+datab => V_SYNC_54,
+datac => VSYNC_STATE_13,
+datad => UN1_VSYNC_STATE_2_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+H_ENABLE_SIG_1_0_0_0_G0_I_O4_Z323: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "f1f1")
+port map (
+combout => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
+dataa => VSYNC_STATE_13,
+datab => VSYNC_STATE_10,
+datac => UN6_DLY_COUNTER_0_X_56,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_COUNTER_NEXT_1_SQMUXA_Z324: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0080")
+port map (
+combout => VSYNC_COUNTER_NEXT_1_SQMUXA,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => D_SET_VSYNC_COUNTER_53,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+V_ENABLE_SIG_1_0_0_0_G0_I_O4_Z325: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "f1f1")
+port map (
+combout => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
+dataa => HSYNC_STATE_17,
+datab => HSYNC_STATE_19,
+datac => UN6_DLY_COUNTER_0_X_56,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+H_SYNC_1_0_0_0_G1_Z326: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "ccd8")
+port map (
+combout => H_SYNC_1_0_0_0_G1,
+dataa => HSYNC_STATE_16,
+datab => H_SYNC_55,
+datac => HSYNC_STATE_17,
+datad => UN1_HSYNC_STATE_3_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_Z327: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0080")
+port map (
+combout => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
+dataa => reset_pin_c,
+datab => dly_counter_0,
+datac => dly_counter_1,
+datad => HSYNC_STATE_20,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_4: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0010")
+port map (
+combout => UN12_HSYNC_COUNTER_4,
+dataa => HSYNC_COUNTER_46,
+datab => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_43,
+datad => HSYNC_COUNTER_49,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_3: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0008")
+port map (
+combout => UN12_HSYNC_COUNTER_3,
+dataa => HSYNC_COUNTER_50,
+datab => HSYNC_COUNTER_44,
+datac => HSYNC_COUNTER_48,
+datad => HSYNC_COUNTER_47,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_3: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0008")
+port map (
+combout => UN11_HSYNC_COUNTER_3,
+dataa => HSYNC_COUNTER_52,
+datab => HSYNC_COUNTER_51,
+datac => HSYNC_COUNTER_49,
+datad => HSYNC_COUNTER_48,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_2: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0808")
+port map (
+combout => UN11_HSYNC_COUNTER_2,
+dataa => HSYNC_COUNTER_50,
+datab => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_46,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9_3: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7fff")
+port map (
+combout => UN9_HSYNC_COUNTERLT9_3,
+dataa => HSYNC_COUNTER_46,
+datab => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_48,
+datad => HSYNC_COUNTER_47,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_2: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0080")
+port map (
+combout => UN13_HSYNC_COUNTER_2,
+dataa => HSYNC_COUNTER_44,
+datab => HSYNC_COUNTER_43,
+datac => HSYNC_COUNTER_48,
+datad => HSYNC_COUNTER_47,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_6: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7fff")
+port map (
+combout => UN9_VSYNC_COUNTERLT9_6,
+dataa => VSYNC_COUNTER_40,
+datab => VSYNC_COUNTER_39,
+datac => VSYNC_COUNTER_42,
+datad => VSYNC_COUNTER_41,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_5: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7fff")
+port map (
+combout => UN9_VSYNC_COUNTERLT9_5,
+dataa => VSYNC_COUNTER_34,
+datab => VSYNC_COUNTER_33,
+datac => VSYNC_COUNTER_36,
+datad => VSYNC_COUNTER_35,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_4: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8000")
+port map (
+combout => UN10_HSYNC_COUNTER_4,
+dataa => HSYNC_COUNTER_48,
+datab => HSYNC_COUNTER_46,
+datac => HSYNC_COUNTER_51,
+datad => HSYNC_COUNTER_49,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_3: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0101")
+port map (
+combout => UN10_HSYNC_COUNTER_3,
+dataa => HSYNC_COUNTER_52,
+datab => HSYNC_COUNTER_45,
+datac => HSYNC_COUNTER_50,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_3: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0020")
+port map (
+combout => UN15_VSYNC_COUNTER_3,
+dataa => VSYNC_COUNTER_33,
+datab => VSYNC_COUNTER_40,
+datac => VSYNC_COUNTER_39,
+datad => VSYNC_COUNTER_42,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_3: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0001")
+port map (
+combout => UN13_VSYNC_COUNTER_3,
+dataa => VSYNC_COUNTER_36,
+datab => VSYNC_COUNTER_35,
+datac => VSYNC_COUNTER_34,
+datad => VSYNC_COUNTER_33,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6_4: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7fff")
+port map (
+combout => UN10_COLUMN_COUNTER_SIGLT6_4,
+dataa => COLUMN_COUNTER_SIG_25,
+datab => COLUMN_COUNTER_SIG_26,
+datac => COLUMN_COUNTER_SIG_23,
+datad => COLUMN_COUNTER_SIG_24,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLT4_2: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "7f7f")
+port map (
+combout => UN10_LINE_COUNTER_SIGLT4_2,
+dataa => LINE_COUNTER_SIG_3_0,
+datab => LINE_COUNTER_SIG_4_0,
+datac => LINE_COUNTER_SIG_0_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_1: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0101")
+port map (
+combout => UN10_HSYNC_COUNTER_1,
+dataa => HSYNC_COUNTER_47,
+datab => HSYNC_COUNTER_44,
+datac => HSYNC_COUNTER_43,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_6: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0001")
+port map (
+combout => UN12_VSYNC_COUNTER_6,
+dataa => VSYNC_COUNTER_35,
+datab => VSYNC_COUNTER_34,
+datac => VSYNC_COUNTER_37,
+datad => VSYNC_COUNTER_36,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_7: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0001")
+port map (
+combout => UN12_VSYNC_COUNTER_7,
+dataa => VSYNC_COUNTER_39,
+datab => VSYNC_COUNTER_38,
+datac => VSYNC_COUNTER_41,
+datad => VSYNC_COUNTER_40,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_7: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "8000")
+port map (
+combout => UN13_HSYNC_COUNTER_7,
+dataa => HSYNC_COUNTER_50,
+datab => HSYNC_COUNTER_49,
+datac => HSYNC_COUNTER_52,
+datad => HSYNC_COUNTER_51,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+UN1_HSYNC_STATE_3_0_Z346: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "eeee")
+port map (
+combout => UN1_HSYNC_STATE_3_0,
+dataa => HSYNC_STATE_21,
+datab => HSYNC_STATE_20,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+UN1_VSYNC_STATE_2_0_Z347: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "eeee")
+port map (
+combout => UN1_VSYNC_STATE_2_0,
+dataa => VSYNC_STATE_11,
+datab => VSYNC_STATE_14,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+D_SET_HSYNC_COUNTER_Z348: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "eeee")
+port map (
+combout => D_SET_HSYNC_COUNTER_57,
+dataa => HSYNC_STATE_22,
+datab => HSYNC_STATE_18,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+D_SET_VSYNC_COUNTER_Z349: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "eeee")
+port map (
+combout => D_SET_VSYNC_COUNTER_53,
+dataa => VSYNC_STATE_12,
+datab => VSYNC_STATE_15,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_9_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c6c")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(9),
+dataa => LINE_COUNTER_SIG_7_0,
+datab => LINE_COUNTER_SIG_8_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(7),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a5a")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(8),
+dataa => LINE_COUNTER_SIG_7_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(6),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datab => VCC,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(7),
+cout => UN1_LINE_COUNTER_SIG_COUT(7),
+dataa => LINE_COUNTER_SIG_5_0,
+datab => LINE_COUNTER_SIG_6_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(5),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(6),
+cout => UN1_LINE_COUNTER_SIG_COUT(6),
+dataa => LINE_COUNTER_SIG_5_0,
+datab => LINE_COUNTER_SIG_6_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(4),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(5),
+cout => UN1_LINE_COUNTER_SIG_COUT(5),
+dataa => LINE_COUNTER_SIG_3_0,
+datab => LINE_COUNTER_SIG_4_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(3),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(4),
+cout => UN1_LINE_COUNTER_SIG_COUT(4),
+dataa => LINE_COUNTER_SIG_3_0,
+datab => LINE_COUNTER_SIG_4_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(2),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(3),
+cout => UN1_LINE_COUNTER_SIG_COUT(3),
+dataa => LINE_COUNTER_SIG_1_0,
+datab => LINE_COUNTER_SIG_2_0,
+cin => UN1_LINE_COUNTER_SIG_COUT(1),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(2),
+cout => UN1_LINE_COUNTER_SIG_COUT(2),
+dataa => LINE_COUNTER_SIG_1_0,
+datab => LINE_COUNTER_SIG_2_0,
+cin => UN1_LINE_COUNTER_SIG_A_COUT(1),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_A_1_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "0088")
+port map (
+cout => UN1_LINE_COUNTER_SIG_A_COUT(1),
+dataa => D_SET_HSYNC_COUNTER_57,
+datab => LINE_COUNTER_SIG_0_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\UN1_LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "6688")
+port map (
+combout => UN1_LINE_COUNTER_SIG_COMBOUT(1),
+cout => UN1_LINE_COUNTER_SIG_COUT(1),
+dataa => D_SET_HSYNC_COUNTER_57,
+datab => LINE_COUNTER_SIG_0_0,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_9_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c6c")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
+dataa => COLUMN_COUNTER_SIG_31,
+datab => COLUMN_COUNTER_SIG_32,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(7),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_8_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a5a")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
+dataa => COLUMN_COUNTER_SIG_31,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(6),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datab => VCC,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_7_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(7),
+dataa => COLUMN_COUNTER_SIG_29,
+datab => COLUMN_COUNTER_SIG_30,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(5),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_6_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(6),
+dataa => COLUMN_COUNTER_SIG_29,
+datab => COLUMN_COUNTER_SIG_30,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(4),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_5_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(5),
+dataa => COLUMN_COUNTER_SIG_27,
+datab => COLUMN_COUNTER_SIG_28,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(3),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_4_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(4),
+dataa => COLUMN_COUNTER_SIG_27,
+datab => COLUMN_COUNTER_SIG_28,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(2),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_3_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "6c80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(3),
+dataa => COLUMN_COUNTER_SIG_25,
+datab => COLUMN_COUNTER_SIG_26,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(1),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_2_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "cin",
+ cin_used => "true",
+ lut_mask => "5a80")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(2),
+dataa => COLUMN_COUNTER_SIG_25,
+datab => COLUMN_COUNTER_SIG_26,
+cin => UN2_COLUMN_COUNTER_NEXT_COUT(0),
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_1_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "6688")
+port map (
+combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(1),
+dataa => COLUMN_COUNTER_SIG_23,
+datab => COLUMN_COUNTER_SIG_24,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\UN2_COLUMN_COUNTER_NEXT_0_\: stratix_lcell generic map (
+ operation_mode => "arithmetic",
+ output_mode => "comb_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "5588")
+port map (
+cout => UN2_COLUMN_COUNTER_NEXT_COUT(0),
+dataa => COLUMN_COUNTER_SIG_23,
+datab => COLUMN_COUNTER_SIG_24,
+ devpor => devpor,
+ devclrn => devclrn,
+ clk => GND,
+ datac => VCC,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+VCC <= '1';
+GND <= '0';
+LINE_COUNTER_NEXT_0_SQMUXA_1_1_I <= not LINE_COUNTER_NEXT_0_SQMUXA_1_1;
+COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I <= not COLUMN_COUNTER_NEXT_0_SQMUXA_1_1;
+G_16_I_I <= not G_16_I;
+UN9_VSYNC_COUNTERLT9_I <= not UN9_VSYNC_COUNTERLT9;
+G_2_I_I <= not G_2_I;
+UN9_HSYNC_COUNTERLT9_I <= not UN9_HSYNC_COUNTERLT9;
+line_counter_sig_0 <= LINE_COUNTER_SIG_0_0;
+line_counter_sig_1 <= LINE_COUNTER_SIG_1_0;
+line_counter_sig_2 <= LINE_COUNTER_SIG_2_0;
+line_counter_sig_3 <= LINE_COUNTER_SIG_3_0;
+line_counter_sig_4 <= LINE_COUNTER_SIG_4_0;
+line_counter_sig_5 <= LINE_COUNTER_SIG_5_0;
+line_counter_sig_6 <= LINE_COUNTER_SIG_6_0;
+line_counter_sig_7 <= LINE_COUNTER_SIG_7_0;
+line_counter_sig_8 <= LINE_COUNTER_SIG_8_0;
+vsync_state_2 <= VSYNC_STATE_9;
+vsync_state_5 <= VSYNC_STATE_10;
+vsync_state_3 <= VSYNC_STATE_11;
+vsync_state_6 <= VSYNC_STATE_12;
+vsync_state_4 <= VSYNC_STATE_13;
+vsync_state_1 <= VSYNC_STATE_14;
+vsync_state_0 <= VSYNC_STATE_15;
+hsync_state_2 <= HSYNC_STATE_16;
+hsync_state_4 <= HSYNC_STATE_17;
+hsync_state_0 <= HSYNC_STATE_18;
+hsync_state_5 <= HSYNC_STATE_19;
+hsync_state_1 <= HSYNC_STATE_20;
+hsync_state_3 <= HSYNC_STATE_21;
+hsync_state_6 <= HSYNC_STATE_22;
+column_counter_sig_0 <= COLUMN_COUNTER_SIG_23;
+column_counter_sig_1 <= COLUMN_COUNTER_SIG_24;
+column_counter_sig_2 <= COLUMN_COUNTER_SIG_25;
+column_counter_sig_3 <= COLUMN_COUNTER_SIG_26;
+column_counter_sig_4 <= COLUMN_COUNTER_SIG_27;
+column_counter_sig_5 <= COLUMN_COUNTER_SIG_28;
+column_counter_sig_6 <= COLUMN_COUNTER_SIG_29;
+column_counter_sig_7 <= COLUMN_COUNTER_SIG_30;
+column_counter_sig_8 <= COLUMN_COUNTER_SIG_31;
+column_counter_sig_9 <= COLUMN_COUNTER_SIG_32;
+vsync_counter_9 <= VSYNC_COUNTER_33;
+vsync_counter_8 <= VSYNC_COUNTER_34;
+vsync_counter_7 <= VSYNC_COUNTER_35;
+vsync_counter_6 <= VSYNC_COUNTER_36;
+vsync_counter_5 <= VSYNC_COUNTER_37;
+vsync_counter_4 <= VSYNC_COUNTER_38;
+vsync_counter_3 <= VSYNC_COUNTER_39;
+vsync_counter_2 <= VSYNC_COUNTER_40;
+vsync_counter_1 <= VSYNC_COUNTER_41;
+vsync_counter_0 <= VSYNC_COUNTER_42;
+hsync_counter_9 <= HSYNC_COUNTER_43;
+hsync_counter_8 <= HSYNC_COUNTER_44;
+hsync_counter_7 <= HSYNC_COUNTER_45;
+hsync_counter_6 <= HSYNC_COUNTER_46;
+hsync_counter_5 <= HSYNC_COUNTER_47;
+hsync_counter_4 <= HSYNC_COUNTER_48;
+hsync_counter_3 <= HSYNC_COUNTER_49;
+hsync_counter_2 <= HSYNC_COUNTER_50;
+hsync_counter_1 <= HSYNC_COUNTER_51;
+hsync_counter_0 <= HSYNC_COUNTER_52;
+d_set_vsync_counter <= D_SET_VSYNC_COUNTER_53;
+v_sync <= V_SYNC_54;
+h_sync <= H_SYNC_55;
+un6_dly_counter_0_x <= UN6_DLY_COUNTER_0_X_56;
+d_set_hsync_counter <= D_SET_HSYNC_COUNTER_57;
+end beh;
+
+--
+library ieee, stratix;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+use stratix.stratix_components.all;
+
+entity vga is
+port(
+clk_pin : in std_logic;
+reset_pin : in std_logic;
+r0_pin : out std_logic;
+r1_pin : out std_logic;
+r2_pin : out std_logic;
+g0_pin : out std_logic;
+g1_pin : out std_logic;
+g2_pin : out std_logic;
+b0_pin : out std_logic;
+b1_pin : out std_logic;
+hsync_pin : out std_logic;
+vsync_pin : out std_logic;
+seven_seg_pin : out std_logic_vector(13 downto 0);
+d_hsync : out std_logic;
+d_vsync : out std_logic;
+d_column_counter : out std_logic_vector(9 downto 0);
+d_line_counter : out std_logic_vector(8 downto 0);
+d_set_column_counter : out std_logic;
+d_set_line_counter : out std_logic;
+d_hsync_counter : out std_logic_vector(9 downto 0);
+d_vsync_counter : out std_logic_vector(9 downto 0);
+d_set_hsync_counter : out std_logic;
+d_set_vsync_counter : out std_logic;
+d_h_enable : out std_logic;
+d_v_enable : out std_logic;
+d_r : out std_logic;
+d_g : out std_logic;
+d_b : out std_logic;
+d_hsync_state : out std_logic_vector(0 to 6);
+d_vsync_state : out std_logic_vector(0 to 6);
+d_state_clk : out std_logic;
+d_toggle : out std_logic;
+d_toggle_counter : out std_logic_vector(24 downto 0));
+end vga;
+
+architecture beh of vga is
+signal devclrn : std_logic := '1';
+signal devpor : std_logic := '1';
+signal devoe : std_logic := '0';
+signal DLY_COUNTER : std_logic_vector(1 downto 0);
+signal \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\ : std_logic_vector(9 downto 0);
+signal \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\ : std_logic_vector(8 downto 0);
+signal \VGA_DRIVER_UNIT.HSYNC_COUNTER\ : std_logic_vector(9 downto 0);
+signal \VGA_DRIVER_UNIT.VSYNC_COUNTER\ : std_logic_vector(9 downto 0);
+signal \VGA_DRIVER_UNIT.HSYNC_STATE\ : std_logic_vector(6 downto 0);
+signal \VGA_DRIVER_UNIT.VSYNC_STATE\ : std_logic_vector(6 downto 0);
+signal \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\ : std_logic_vector(24 downto 0);
+signal SEVEN_SEG_PINZ : std_logic_vector(13 downto 0);
+signal D_COLUMN_COUNTERZ : std_logic_vector(9 downto 0);
+signal D_LINE_COUNTERZ : std_logic_vector(8 downto 0);
+signal D_HSYNC_COUNTERZ : std_logic_vector(9 downto 0);
+signal D_VSYNC_COUNTERZ : std_logic_vector(9 downto 0);
+signal D_HSYNC_STATEZ : std_logic_vector(6 downto 0);
+signal D_VSYNC_STATEZ : std_logic_vector(6 downto 0);
+signal D_TOGGLE_COUNTERZ : std_logic_vector(24 downto 0);
+signal VCC : std_logic ;
+signal GND : std_logic ;
+signal \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\ : std_logic ;
+signal \VGA_DRIVER_UNIT.H_SYNC\ : std_logic ;
+signal \VGA_DRIVER_UNIT.V_SYNC\ : std_logic ;
+signal \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\ : std_logic ;
+signal \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\ : std_logic ;
+signal \VGA_DRIVER_UNIT.H_ENABLE_SIG\ : std_logic ;
+signal \VGA_DRIVER_UNIT.V_ENABLE_SIG\ : std_logic ;
+signal \VGA_CONTROL_UNIT.R\ : std_logic ;
+signal \VGA_CONTROL_UNIT.G\ : std_logic ;
+signal \VGA_CONTROL_UNIT.B\ : std_logic ;
+signal G_33 : std_logic ;
+signal \VGA_CONTROL_UNIT.TOGGLE_SIG\ : std_logic ;
+signal CLK_PIN_C : std_logic ;
+signal RESET_PIN_C : std_logic ;
+signal CLK_PIN_INTERNAL : std_logic ;
+signal RESET_PIN_INTERNAL : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_84_0 : std_logic ;
+signal N_85_0 : std_logic ;
+signal N_86_0 : std_logic ;
+signal N_87_0 : std_logic ;
+signal N_88_0 : std_logic ;
+signal N_89_0 : std_logic ;
+signal N_90_0 : std_logic ;
+signal N_91_0 : std_logic ;
+signal N_92_0 : std_logic ;
+signal N_93_0 : std_logic ;
+signal N_94_0 : std_logic ;
+signal N_95_0 : std_logic ;
+signal N_96_0 : std_logic ;
+signal N_97_0 : std_logic ;
+signal N_98_0 : std_logic ;
+signal N_99_0 : std_logic ;
+signal N_100_0 : std_logic ;
+signal N_101_0 : std_logic ;
+signal N_102_0 : std_logic ;
+signal N_103_0 : std_logic ;
+signal N_104_0 : std_logic ;
+signal N_105_0 : std_logic ;
+signal N_106_0 : std_logic ;
+signal N_107_0 : std_logic ;
+signal N_108_0 : std_logic ;
+signal N_109_0 : std_logic ;
+signal N_110_0 : std_logic ;
+signal N_111_0 : std_logic ;
+signal N_112_0 : std_logic ;
+signal N_113_0 : std_logic ;
+signal N_114_0 : std_logic ;
+signal N_115_0 : std_logic ;
+signal N_116_0 : std_logic ;
+signal N_117_0 : std_logic ;
+signal N_118 : std_logic ;
+signal N_119 : std_logic ;
+signal N_120 : std_logic ;
+signal N_121 : std_logic ;
+signal N_122 : std_logic ;
+signal N_123 : std_logic ;
+signal N_124 : std_logic ;
+signal N_125 : std_logic ;
+signal N_126 : std_logic ;
+signal N_127 : std_logic ;
+signal N_128 : std_logic ;
+signal N_129 : std_logic ;
+signal N_130 : std_logic ;
+signal N_131 : std_logic ;
+signal N_132 : std_logic ;
+signal N_133 : std_logic ;
+signal N_134 : std_logic ;
+signal N_135 : std_logic ;
+signal N_136 : std_logic ;
+signal N_137 : std_logic ;
+signal N_138 : std_logic ;
+signal N_139 : std_logic ;
+signal N_140 : std_logic ;
+signal N_141 : std_logic ;
+signal N_142 : std_logic ;
+signal N_143 : std_logic ;
+signal N_144 : std_logic ;
+signal N_145 : std_logic ;
+signal N_146 : std_logic ;
+signal N_147 : std_logic ;
+signal N_148 : std_logic ;
+signal N_149 : std_logic ;
+signal N_150 : std_logic ;
+signal N_151 : std_logic ;
+signal N_152 : std_logic ;
+signal N_153 : std_logic ;
+signal N_154 : std_logic ;
+signal N_155 : std_logic ;
+signal N_156 : std_logic ;
+signal N_157 : std_logic ;
+signal N_158 : std_logic ;
+signal N_159 : std_logic ;
+signal N_160 : std_logic ;
+signal N_161 : std_logic ;
+signal N_162 : std_logic ;
+signal N_163 : std_logic ;
+signal N_164 : std_logic ;
+signal N_165 : std_logic ;
+signal N_166 : std_logic ;
+signal N_167 : std_logic ;
+signal N_168 : std_logic ;
+signal N_169 : std_logic ;
+signal N_170 : std_logic ;
+signal N_171 : std_logic ;
+signal N_172 : std_logic ;
+signal N_173 : std_logic ;
+signal N_174 : std_logic ;
+signal N_175 : std_logic ;
+signal N_176 : std_logic ;
+signal N_177 : std_logic ;
+signal N_178 : std_logic ;
+signal N_179 : std_logic ;
+signal N_180 : std_logic ;
+signal N_181 : std_logic ;
+signal N_182 : std_logic ;
+signal N_183 : std_logic ;
+signal N_184 : std_logic ;
+signal N_185 : std_logic ;
+signal N_186 : std_logic ;
+signal N_187 : std_logic ;
+signal N_188 : std_logic ;
+signal N_189 : std_logic ;
+signal N_190 : std_logic ;
+signal N_191 : std_logic ;
+signal N_192 : std_logic ;
+signal N_193 : std_logic ;
+signal N_194 : std_logic ;
+signal N_195 : std_logic ;
+signal N_196 : std_logic ;
+signal N_197 : std_logic ;
+signal N_198 : std_logic ;
+signal R0_PINZ : std_logic ;
+signal R1_PINZ : std_logic ;
+signal R2_PINZ : std_logic ;
+signal G0_PINZ : std_logic ;
+signal G1_PINZ : std_logic ;
+signal G2_PINZ : std_logic ;
+signal B0_PINZ : std_logic ;
+signal B1_PINZ : std_logic ;
+signal HSYNC_PINZ : std_logic ;
+signal VSYNC_PINZ : std_logic ;
+signal D_HSYNCZ : std_logic ;
+signal D_VSYNCZ : std_logic ;
+signal D_SET_COLUMN_COUNTERZ : std_logic ;
+signal D_SET_LINE_COUNTERZ : std_logic ;
+signal D_SET_HSYNC_COUNTERZ : std_logic ;
+signal D_SET_VSYNC_COUNTERZ : std_logic ;
+signal D_H_ENABLEZ : std_logic ;
+signal D_V_ENABLEZ : std_logic ;
+signal D_RZ : std_logic ;
+signal D_GZ : std_logic ;
+signal D_BZ : std_logic ;
+signal D_STATE_CLKZ : std_logic ;
+signal D_TOGGLEZ : std_logic ;
+component vga_driver
+port(
+ line_counter_sig_0 : out std_logic;
+ line_counter_sig_1 : out std_logic;
+ line_counter_sig_2 : out std_logic;
+ line_counter_sig_3 : out std_logic;
+ line_counter_sig_4 : out std_logic;
+ line_counter_sig_5 : out std_logic;
+ line_counter_sig_6 : out std_logic;
+ line_counter_sig_7 : out std_logic;
+ line_counter_sig_8 : out std_logic;
+ dly_counter_1 : in std_logic;
+ dly_counter_0 : in std_logic;
+ vsync_state_2 : out std_logic;
+ vsync_state_5 : out std_logic;
+ vsync_state_3 : out std_logic;
+ vsync_state_6 : out std_logic;
+ vsync_state_4 : out std_logic;
+ vsync_state_1 : out std_logic;
+ vsync_state_0 : out std_logic;
+ hsync_state_2 : out std_logic;
+ hsync_state_4 : out std_logic;
+ hsync_state_0 : out std_logic;
+ hsync_state_5 : out std_logic;
+ hsync_state_1 : out std_logic;
+ hsync_state_3 : out std_logic;
+ hsync_state_6 : out std_logic;
+ column_counter_sig_0 : out std_logic;
+ column_counter_sig_1 : out std_logic;
+ column_counter_sig_2 : out std_logic;
+ column_counter_sig_3 : out std_logic;
+ column_counter_sig_4 : out std_logic;
+ column_counter_sig_5 : out std_logic;
+ column_counter_sig_6 : out std_logic;
+ column_counter_sig_7 : out std_logic;
+ column_counter_sig_8 : out std_logic;
+ column_counter_sig_9 : out std_logic;
+ vsync_counter_9 : out std_logic;
+ vsync_counter_8 : out std_logic;
+ vsync_counter_7 : out std_logic;
+ vsync_counter_6 : out std_logic;
+ vsync_counter_5 : out std_logic;
+ vsync_counter_4 : out std_logic;
+ vsync_counter_3 : out std_logic;
+ vsync_counter_2 : out std_logic;
+ vsync_counter_1 : out std_logic;
+ vsync_counter_0 : out std_logic;
+ hsync_counter_9 : out std_logic;
+ hsync_counter_8 : out std_logic;
+ hsync_counter_7 : out std_logic;
+ hsync_counter_6 : out std_logic;
+ hsync_counter_5 : out std_logic;
+ hsync_counter_4 : out std_logic;
+ hsync_counter_3 : out std_logic;
+ hsync_counter_2 : out std_logic;
+ hsync_counter_1 : out std_logic;
+ hsync_counter_0 : out std_logic;
+ d_set_vsync_counter : out std_logic;
+ v_sync : out std_logic;
+ h_sync : out std_logic;
+ h_enable_sig : out std_logic;
+ v_enable_sig : out std_logic;
+ reset_pin_c : in std_logic;
+ un6_dly_counter_0_x : out std_logic;
+ d_set_hsync_counter : out std_logic;
+ clk_pin_c : in std_logic );
+end component;
+component vga_control
+port(
+ line_counter_sig_0 : in std_logic;
+ line_counter_sig_2 : in std_logic;
+ line_counter_sig_1 : in std_logic;
+ line_counter_sig_3 : in std_logic;
+ line_counter_sig_6 : in std_logic;
+ line_counter_sig_5 : in std_logic;
+ line_counter_sig_4 : in std_logic;
+ line_counter_sig_7 : in std_logic;
+ line_counter_sig_8 : in std_logic;
+ column_counter_sig_0 : in std_logic;
+ column_counter_sig_1 : in std_logic;
+ column_counter_sig_2 : in std_logic;
+ column_counter_sig_8 : in std_logic;
+ column_counter_sig_3 : in std_logic;
+ column_counter_sig_5 : in std_logic;
+ column_counter_sig_4 : in std_logic;
+ column_counter_sig_9 : in std_logic;
+ column_counter_sig_7 : in std_logic;
+ column_counter_sig_6 : in std_logic;
+ toggle_counter_sig_0 : out std_logic;
+ toggle_counter_sig_1 : out std_logic;
+ toggle_counter_sig_2 : out std_logic;
+ toggle_counter_sig_3 : out std_logic;
+ toggle_counter_sig_4 : out std_logic;
+ toggle_counter_sig_5 : out std_logic;
+ toggle_counter_sig_6 : out std_logic;
+ toggle_counter_sig_7 : out std_logic;
+ toggle_counter_sig_8 : out std_logic;
+ toggle_counter_sig_9 : out std_logic;
+ toggle_counter_sig_10 : out std_logic;
+ toggle_counter_sig_11 : out std_logic;
+ toggle_counter_sig_12 : out std_logic;
+ toggle_counter_sig_13 : out std_logic;
+ toggle_counter_sig_14 : out std_logic;
+ toggle_counter_sig_15 : out std_logic;
+ toggle_counter_sig_16 : out std_logic;
+ toggle_counter_sig_17 : out std_logic;
+ toggle_counter_sig_18 : out std_logic;
+ toggle_counter_sig_19 : out std_logic;
+ toggle_counter_sig_20 : out std_logic;
+ toggle_counter_sig_21 : out std_logic;
+ toggle_counter_sig_22 : out std_logic;
+ toggle_counter_sig_23 : out std_logic;
+ toggle_counter_sig_24 : out std_logic;
+ h_enable_sig : in std_logic;
+ g : out std_logic;
+ b : out std_logic;
+ v_enable_sig : in std_logic;
+ r : out std_logic;
+ toggle_sig : out std_logic;
+ un6_dly_counter_0_x : in std_logic;
+ clk_pin_c : in std_logic );
+end component;
+begin
+VCC <= '1';
+GND <= '0';
+\DLY_COUNTER_1_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "a8a8")
+port map (
+regout => DLY_COUNTER(1),
+clk => CLK_PIN_C,
+dataa => RESET_PIN_C,
+datab => DLY_COUNTER(0),
+datac => DLY_COUNTER(1),
+ devpor => devpor,
+ devclrn => devclrn,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+\DLY_COUNTER_0_\: stratix_lcell generic map (
+ operation_mode => "normal",
+ output_mode => "reg_only",
+ synch_mode => "off",
+ sum_lutc_input => "datac",
+ lut_mask => "a2a2")
+port map (
+regout => DLY_COUNTER(0),
+clk => CLK_PIN_C,
+dataa => RESET_PIN_C,
+datab => DLY_COUNTER(0),
+datac => DLY_COUNTER(1),
+ devpor => devpor,
+ devclrn => devclrn,
+ datad => VCC,
+ aclr => GND,
+ sclr => GND,
+ sload => GND,
+ ena => VCC,
+ cin => GND,
+ inverta => GND,
+ aload => GND);
+RESET_PIN_IN: stratix_io generic map (
+ operation_mode => "input"
+ )
+port map (
+padio => N_2,
+combout => RESET_PIN_C,
+oe => GND,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+CLK_PIN_IN: stratix_io generic map (
+ operation_mode => "input"
+ )
+port map (
+padio => N_1,
+combout => CLK_PIN_C,
+oe => GND,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_24_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(24),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_23_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(23),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_22_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(22),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_21_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(21),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_20_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(20),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_19_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(19),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_18_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(18),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_17_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(17),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_16_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(16),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_15_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(15),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_14_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(14),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_13_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(13),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_12_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(12),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_11_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(11),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_10_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(10),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_9_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(9),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_8_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(8),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_7_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(7),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_6_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(6),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_5_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(5),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_4_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(4),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_3_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(3),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_2_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(2),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_1_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(1),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_TOGGLE_COUNTER_OUT_0_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLE_COUNTERZ(0),
+datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_TOGGLE_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_TOGGLEZ,
+datain => \VGA_CONTROL_UNIT.TOGGLE_SIG\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_STATE_CLK_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_STATE_CLKZ,
+datain => G_33,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_STATE_OUT_0_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_STATEZ(0),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_STATE_OUT_1_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_STATEZ(1),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_STATE_OUT_2_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_STATEZ(2),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_STATE_OUT_3_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_STATEZ(3),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_STATE_OUT_4_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_STATEZ(4),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_STATE_OUT_5_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_STATEZ(5),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_STATE_OUT_6_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_STATEZ(6),
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_STATE_OUT_0_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_STATEZ(0),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_STATE_OUT_1_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_STATEZ(1),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_STATE_OUT_2_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_STATEZ(2),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_STATE_OUT_3_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_STATEZ(3),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_STATE_OUT_4_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_STATEZ(4),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_STATE_OUT_5_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_STATEZ(5),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_STATE_OUT_6_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_STATEZ(6),
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_B_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_BZ,
+datain => \VGA_CONTROL_UNIT.B\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_G_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_GZ,
+datain => \VGA_CONTROL_UNIT.G\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_R_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_RZ,
+datain => \VGA_CONTROL_UNIT.R\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_V_ENABLE_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_V_ENABLEZ,
+datain => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_H_ENABLE_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_H_ENABLEZ,
+datain => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_SET_VSYNC_COUNTER_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_SET_VSYNC_COUNTERZ,
+datain => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_SET_HSYNC_COUNTER_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_SET_HSYNC_COUNTERZ,
+datain => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_9_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(9),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_8_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(8),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_7_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(7),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_6_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(6),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_5_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(5),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_4_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(4),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_3_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(3),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_2_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(2),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_1_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(1),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_VSYNC_COUNTER_OUT_0_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNC_COUNTERZ(0),
+datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_9_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(9),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_8_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(8),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_7_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(7),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_6_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(6),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_5_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(5),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_4_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(4),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_3_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(3),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_2_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(2),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_1_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(1),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_HSYNC_COUNTER_OUT_0_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNC_COUNTERZ(0),
+datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_SET_LINE_COUNTER_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_SET_LINE_COUNTERZ,
+datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_SET_COLUMN_COUNTER_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_SET_COLUMN_COUNTERZ,
+datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_8_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(8),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_7_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(7),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_6_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(6),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_5_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(5),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_4_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(4),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_3_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(3),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_2_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(2),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_1_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(1),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_LINE_COUNTER_OUT_0_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_LINE_COUNTERZ(0),
+datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_9_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(9),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_8_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(8),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_7_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(7),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_6_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(6),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_5_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(5),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_4_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(4),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_3_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(3),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_2_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(2),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_1_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(1),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\D_COLUMN_COUNTER_OUT_0_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_COLUMN_COUNTERZ(0),
+datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_VSYNC_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_VSYNCZ,
+datain => \VGA_DRIVER_UNIT.V_SYNC\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+D_HSYNC_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => D_HSYNCZ,
+datain => \VGA_DRIVER_UNIT.H_SYNC\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_TRI_13_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(13),
+datain => VCC,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_OUT_12_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(12),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_OUT_11_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(11),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_OUT_10_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(10),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_OUT_9_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(9),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_OUT_8_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(8),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_OUT_7_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(7),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_TRI_6_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(6),
+datain => VCC,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_TRI_5_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(5),
+datain => VCC,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_TRI_4_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(4),
+datain => VCC,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_TRI_3_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(3),
+datain => VCC,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_OUT_2_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(2),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_OUT_1_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(1),
+datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+\SEVEN_SEG_PIN_TRI_0_\: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => SEVEN_SEG_PINZ(0),
+datain => VCC,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+VSYNC_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => VSYNC_PINZ,
+datain => \VGA_DRIVER_UNIT.V_SYNC\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+HSYNC_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => HSYNC_PINZ,
+datain => \VGA_DRIVER_UNIT.H_SYNC\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+B1_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => B1_PINZ,
+datain => \VGA_CONTROL_UNIT.B\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+B0_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => B0_PINZ,
+datain => \VGA_CONTROL_UNIT.B\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+G2_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => G2_PINZ,
+datain => \VGA_CONTROL_UNIT.G\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+G1_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => G1_PINZ,
+datain => \VGA_CONTROL_UNIT.G\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+G0_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => G0_PINZ,
+datain => \VGA_CONTROL_UNIT.G\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+R2_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => R2_PINZ,
+datain => \VGA_CONTROL_UNIT.R\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+R1_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => R1_PINZ,
+datain => \VGA_CONTROL_UNIT.R\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+R0_PIN_OUT: stratix_io generic map (
+ operation_mode => "output"
+ )
+port map (
+padio => R0_PINZ,
+datain => \VGA_CONTROL_UNIT.R\,
+oe => VCC,
+ devpor => devpor,
+ devclrn => devclrn,
+ devoe => devoe,
+ outclkena => VCC,
+ inclkena => VCC,
+ areset => GND,
+ sreset => GND);
+G_33 <= CLK_PIN_C;
+VGA_DRIVER_UNIT: vga_driver port map (
+line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
+line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
+line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
+line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
+line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
+line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
+line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
+line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
+line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
+dly_counter_1 => DLY_COUNTER(1),
+dly_counter_0 => DLY_COUNTER(0),
+vsync_state_2 => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
+vsync_state_5 => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
+vsync_state_3 => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
+vsync_state_6 => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
+vsync_state_4 => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
+vsync_state_1 => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
+vsync_state_0 => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
+hsync_state_2 => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
+hsync_state_4 => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
+hsync_state_0 => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
+hsync_state_5 => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
+hsync_state_1 => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
+hsync_state_3 => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
+hsync_state_6 => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
+column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
+column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
+column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
+column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
+column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
+column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
+column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
+column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
+column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
+column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
+vsync_counter_9 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
+vsync_counter_8 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
+vsync_counter_7 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
+vsync_counter_6 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
+vsync_counter_5 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
+vsync_counter_4 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
+vsync_counter_3 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
+vsync_counter_2 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
+vsync_counter_1 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
+vsync_counter_0 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
+hsync_counter_9 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
+hsync_counter_8 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
+hsync_counter_7 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
+hsync_counter_6 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
+hsync_counter_5 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
+hsync_counter_4 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
+hsync_counter_3 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
+hsync_counter_2 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
+hsync_counter_1 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
+hsync_counter_0 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
+d_set_vsync_counter => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
+v_sync => \VGA_DRIVER_UNIT.V_SYNC\,
+h_sync => \VGA_DRIVER_UNIT.H_SYNC\,
+h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
+v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
+reset_pin_c => RESET_PIN_C,
+un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+d_set_hsync_counter => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
+clk_pin_c => CLK_PIN_C);
+VGA_CONTROL_UNIT: vga_control port map (
+line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
+line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
+line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
+line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
+line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
+line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
+line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
+line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
+line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
+column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
+column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
+column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
+column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
+column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
+column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
+column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
+column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
+column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
+column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
+toggle_counter_sig_0 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0),
+toggle_counter_sig_1 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1),
+toggle_counter_sig_2 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2),
+toggle_counter_sig_3 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3),
+toggle_counter_sig_4 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4),
+toggle_counter_sig_5 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5),
+toggle_counter_sig_6 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6),
+toggle_counter_sig_7 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7),
+toggle_counter_sig_8 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8),
+toggle_counter_sig_9 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9),
+toggle_counter_sig_10 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10),
+toggle_counter_sig_11 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11),
+toggle_counter_sig_12 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12),
+toggle_counter_sig_13 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13),
+toggle_counter_sig_14 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14),
+toggle_counter_sig_15 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15),
+toggle_counter_sig_16 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16),
+toggle_counter_sig_17 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17),
+toggle_counter_sig_18 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18),
+toggle_counter_sig_19 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19),
+toggle_counter_sig_20 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20),
+toggle_counter_sig_21 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21),
+toggle_counter_sig_22 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22),
+toggle_counter_sig_23 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23),
+toggle_counter_sig_24 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24),
+h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
+g => \VGA_CONTROL_UNIT.G\,
+b => \VGA_CONTROL_UNIT.B\,
+v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
+r => \VGA_CONTROL_UNIT.R\,
+toggle_sig => \VGA_CONTROL_UNIT.TOGGLE_SIG\,
+un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
+clk_pin_c => CLK_PIN_C);
+N_1 <= CLK_PIN_INTERNAL;
+N_2 <= RESET_PIN_INTERNAL;
+N_84_0 <= R0_PINZ;
+N_85_0 <= R1_PINZ;
+N_86_0 <= R2_PINZ;
+N_87_0 <= G0_PINZ;
+N_88_0 <= G1_PINZ;
+N_89_0 <= G2_PINZ;
+N_90_0 <= B0_PINZ;
+N_91_0 <= B1_PINZ;
+N_92_0 <= HSYNC_PINZ;
+N_93_0 <= VSYNC_PINZ;
+N_94_0 <= SEVEN_SEG_PINZ(0);
+N_95_0 <= SEVEN_SEG_PINZ(1);
+N_96_0 <= SEVEN_SEG_PINZ(2);
+N_97_0 <= SEVEN_SEG_PINZ(3);
+N_98_0 <= SEVEN_SEG_PINZ(4);
+N_99_0 <= SEVEN_SEG_PINZ(5);
+N_100_0 <= SEVEN_SEG_PINZ(6);
+N_101_0 <= SEVEN_SEG_PINZ(7);
+N_102_0 <= SEVEN_SEG_PINZ(8);
+N_103_0 <= SEVEN_SEG_PINZ(9);
+N_104_0 <= SEVEN_SEG_PINZ(10);
+N_105_0 <= SEVEN_SEG_PINZ(11);
+N_106_0 <= SEVEN_SEG_PINZ(12);
+N_107_0 <= SEVEN_SEG_PINZ(13);
+N_108_0 <= D_HSYNCZ;
+N_109_0 <= D_VSYNCZ;
+N_110_0 <= D_COLUMN_COUNTERZ(0);
+N_111_0 <= D_COLUMN_COUNTERZ(1);
+N_112_0 <= D_COLUMN_COUNTERZ(2);
+N_113_0 <= D_COLUMN_COUNTERZ(3);
+N_114_0 <= D_COLUMN_COUNTERZ(4);
+N_115_0 <= D_COLUMN_COUNTERZ(5);
+N_116_0 <= D_COLUMN_COUNTERZ(6);
+N_117_0 <= D_COLUMN_COUNTERZ(7);
+N_118 <= D_COLUMN_COUNTERZ(8);
+N_119 <= D_COLUMN_COUNTERZ(9);
+N_120 <= D_LINE_COUNTERZ(0);
+N_121 <= D_LINE_COUNTERZ(1);
+N_122 <= D_LINE_COUNTERZ(2);
+N_123 <= D_LINE_COUNTERZ(3);
+N_124 <= D_LINE_COUNTERZ(4);
+N_125 <= D_LINE_COUNTERZ(5);
+N_126 <= D_LINE_COUNTERZ(6);
+N_127 <= D_LINE_COUNTERZ(7);
+N_128 <= D_LINE_COUNTERZ(8);
+N_129 <= D_SET_COLUMN_COUNTERZ;
+N_130 <= D_SET_LINE_COUNTERZ;
+N_131 <= D_HSYNC_COUNTERZ(0);
+N_132 <= D_HSYNC_COUNTERZ(1);
+N_133 <= D_HSYNC_COUNTERZ(2);
+N_134 <= D_HSYNC_COUNTERZ(3);
+N_135 <= D_HSYNC_COUNTERZ(4);
+N_136 <= D_HSYNC_COUNTERZ(5);
+N_137 <= D_HSYNC_COUNTERZ(6);
+N_138 <= D_HSYNC_COUNTERZ(7);
+N_139 <= D_HSYNC_COUNTERZ(8);
+N_140 <= D_HSYNC_COUNTERZ(9);
+N_141 <= D_VSYNC_COUNTERZ(0);
+N_142 <= D_VSYNC_COUNTERZ(1);
+N_143 <= D_VSYNC_COUNTERZ(2);
+N_144 <= D_VSYNC_COUNTERZ(3);
+N_145 <= D_VSYNC_COUNTERZ(4);
+N_146 <= D_VSYNC_COUNTERZ(5);
+N_147 <= D_VSYNC_COUNTERZ(6);
+N_148 <= D_VSYNC_COUNTERZ(7);
+N_149 <= D_VSYNC_COUNTERZ(8);
+N_150 <= D_VSYNC_COUNTERZ(9);
+N_151 <= D_SET_HSYNC_COUNTERZ;
+N_152 <= D_SET_VSYNC_COUNTERZ;
+N_153 <= D_H_ENABLEZ;
+N_154 <= D_V_ENABLEZ;
+N_155 <= D_RZ;
+N_156 <= D_GZ;
+N_157 <= D_BZ;
+N_158 <= D_HSYNC_STATEZ(6);
+N_159 <= D_HSYNC_STATEZ(5);
+N_160 <= D_HSYNC_STATEZ(4);
+N_161 <= D_HSYNC_STATEZ(3);
+N_162 <= D_HSYNC_STATEZ(2);
+N_163 <= D_HSYNC_STATEZ(1);
+N_164 <= D_HSYNC_STATEZ(0);
+N_165 <= D_VSYNC_STATEZ(6);
+N_166 <= D_VSYNC_STATEZ(5);
+N_167 <= D_VSYNC_STATEZ(4);
+N_168 <= D_VSYNC_STATEZ(3);
+N_169 <= D_VSYNC_STATEZ(2);
+N_170 <= D_VSYNC_STATEZ(1);
+N_171 <= D_VSYNC_STATEZ(0);
+N_172 <= D_STATE_CLKZ;
+N_173 <= D_TOGGLEZ;
+N_174 <= D_TOGGLE_COUNTERZ(0);
+N_175 <= D_TOGGLE_COUNTERZ(1);
+N_176 <= D_TOGGLE_COUNTERZ(2);
+N_177 <= D_TOGGLE_COUNTERZ(3);
+N_178 <= D_TOGGLE_COUNTERZ(4);
+N_179 <= D_TOGGLE_COUNTERZ(5);
+N_180 <= D_TOGGLE_COUNTERZ(6);
+N_181 <= D_TOGGLE_COUNTERZ(7);
+N_182 <= D_TOGGLE_COUNTERZ(8);
+N_183 <= D_TOGGLE_COUNTERZ(9);
+N_184 <= D_TOGGLE_COUNTERZ(10);
+N_185 <= D_TOGGLE_COUNTERZ(11);
+N_186 <= D_TOGGLE_COUNTERZ(12);
+N_187 <= D_TOGGLE_COUNTERZ(13);
+N_188 <= D_TOGGLE_COUNTERZ(14);
+N_189 <= D_TOGGLE_COUNTERZ(15);
+N_190 <= D_TOGGLE_COUNTERZ(16);
+N_191 <= D_TOGGLE_COUNTERZ(17);
+N_192 <= D_TOGGLE_COUNTERZ(18);
+N_193 <= D_TOGGLE_COUNTERZ(19);
+N_194 <= D_TOGGLE_COUNTERZ(20);
+N_195 <= D_TOGGLE_COUNTERZ(21);
+N_196 <= D_TOGGLE_COUNTERZ(22);
+N_197 <= D_TOGGLE_COUNTERZ(23);
+N_198 <= D_TOGGLE_COUNTERZ(24);
+r0_pin <= N_84_0;
+r1_pin <= N_85_0;
+r2_pin <= N_86_0;
+g0_pin <= N_87_0;
+g1_pin <= N_88_0;
+g2_pin <= N_89_0;
+b0_pin <= N_90_0;
+b1_pin <= N_91_0;
+hsync_pin <= N_92_0;
+vsync_pin <= N_93_0;
+seven_seg_pin(0) <= N_94_0;
+seven_seg_pin(1) <= N_95_0;
+seven_seg_pin(2) <= N_96_0;
+seven_seg_pin(3) <= N_97_0;
+seven_seg_pin(4) <= N_98_0;
+seven_seg_pin(5) <= N_99_0;
+seven_seg_pin(6) <= N_100_0;
+seven_seg_pin(7) <= N_101_0;
+seven_seg_pin(8) <= N_102_0;
+seven_seg_pin(9) <= N_103_0;
+seven_seg_pin(10) <= N_104_0;
+seven_seg_pin(11) <= N_105_0;
+seven_seg_pin(12) <= N_106_0;
+seven_seg_pin(13) <= N_107_0;
+d_hsync <= N_108_0;
+d_vsync <= N_109_0;
+d_column_counter(0) <= N_110_0;
+d_column_counter(1) <= N_111_0;
+d_column_counter(2) <= N_112_0;
+d_column_counter(3) <= N_113_0;
+d_column_counter(4) <= N_114_0;
+d_column_counter(5) <= N_115_0;
+d_column_counter(6) <= N_116_0;
+d_column_counter(7) <= N_117_0;
+d_column_counter(8) <= N_118;
+d_column_counter(9) <= N_119;
+d_line_counter(0) <= N_120;
+d_line_counter(1) <= N_121;
+d_line_counter(2) <= N_122;
+d_line_counter(3) <= N_123;
+d_line_counter(4) <= N_124;
+d_line_counter(5) <= N_125;
+d_line_counter(6) <= N_126;
+d_line_counter(7) <= N_127;
+d_line_counter(8) <= N_128;
+d_set_column_counter <= N_129;
+d_set_line_counter <= N_130;
+d_hsync_counter(0) <= N_131;
+d_hsync_counter(1) <= N_132;
+d_hsync_counter(2) <= N_133;
+d_hsync_counter(3) <= N_134;
+d_hsync_counter(4) <= N_135;
+d_hsync_counter(5) <= N_136;
+d_hsync_counter(6) <= N_137;
+d_hsync_counter(7) <= N_138;
+d_hsync_counter(8) <= N_139;
+d_hsync_counter(9) <= N_140;
+d_vsync_counter(0) <= N_141;
+d_vsync_counter(1) <= N_142;
+d_vsync_counter(2) <= N_143;
+d_vsync_counter(3) <= N_144;
+d_vsync_counter(4) <= N_145;
+d_vsync_counter(5) <= N_146;
+d_vsync_counter(6) <= N_147;
+d_vsync_counter(7) <= N_148;
+d_vsync_counter(8) <= N_149;
+d_vsync_counter(9) <= N_150;
+d_set_hsync_counter <= N_151;
+d_set_vsync_counter <= N_152;
+d_h_enable <= N_153;
+d_v_enable <= N_154;
+d_r <= N_155;
+d_g <= N_156;
+d_b <= N_157;
+d_hsync_state(6) <= N_158;
+d_hsync_state(5) <= N_159;
+d_hsync_state(4) <= N_160;
+d_hsync_state(3) <= N_161;
+d_hsync_state(2) <= N_162;
+d_hsync_state(1) <= N_163;
+d_hsync_state(0) <= N_164;
+d_vsync_state(6) <= N_165;
+d_vsync_state(5) <= N_166;
+d_vsync_state(4) <= N_167;
+d_vsync_state(3) <= N_168;
+d_vsync_state(2) <= N_169;
+d_vsync_state(1) <= N_170;
+d_vsync_state(0) <= N_171;
+d_state_clk <= N_172;
+d_toggle <= N_173;
+d_toggle_counter(0) <= N_174;
+d_toggle_counter(1) <= N_175;
+d_toggle_counter(2) <= N_176;
+d_toggle_counter(3) <= N_177;
+d_toggle_counter(4) <= N_178;
+d_toggle_counter(5) <= N_179;
+d_toggle_counter(6) <= N_180;
+d_toggle_counter(7) <= N_181;
+d_toggle_counter(8) <= N_182;
+d_toggle_counter(9) <= N_183;
+d_toggle_counter(10) <= N_184;
+d_toggle_counter(11) <= N_185;
+d_toggle_counter(12) <= N_186;
+d_toggle_counter(13) <= N_187;
+d_toggle_counter(14) <= N_188;
+d_toggle_counter(15) <= N_189;
+d_toggle_counter(16) <= N_190;
+d_toggle_counter(17) <= N_191;
+d_toggle_counter(18) <= N_192;
+d_toggle_counter(19) <= N_193;
+d_toggle_counter(20) <= N_194;
+d_toggle_counter(21) <= N_195;
+d_toggle_counter(22) <= N_196;
+d_toggle_counter(23) <= N_197;
+d_toggle_counter(24) <= N_198;
+CLK_PIN_INTERNAL <= clk_pin;
+RESET_PIN_INTERNAL <= reset_pin;
+end beh;
+
--- /dev/null
+//
+// Written by Synplify
+// Product Version "C-2009.06"
+// Program "Synplify Pro", Mapper "map450rc, Build 029R"
+// Wed Oct 21 17:26:36 2009
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "noname"
+// file 1 "\/opt/synplify/fpga_c200906/lib/vhd/std.vhd "
+// file 2 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd "
+// file 3 "\/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd "
+// file 4 "\/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd "
+// file 5 "\/opt/synplify/fpga_c200906/lib/vhd/arith.vhd "
+// file 6 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd "
+// file 7 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd "
+// file 8 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd "
+// file 9 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd "
+// file 10 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd "
+// file 11 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd "
+// file 12 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd "
+// file 13 "\/homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd "
+
+// VQM4.1+
+module vga_driver (
+ line_counter_sig_0,
+ line_counter_sig_1,
+ line_counter_sig_2,
+ line_counter_sig_3,
+ line_counter_sig_4,
+ line_counter_sig_5,
+ line_counter_sig_6,
+ line_counter_sig_7,
+ line_counter_sig_8,
+ dly_counter_1,
+ dly_counter_0,
+ vsync_state_2,
+ vsync_state_5,
+ vsync_state_3,
+ vsync_state_6,
+ vsync_state_4,
+ vsync_state_1,
+ vsync_state_0,
+ hsync_state_2,
+ hsync_state_4,
+ hsync_state_0,
+ hsync_state_5,
+ hsync_state_1,
+ hsync_state_3,
+ hsync_state_6,
+ column_counter_sig_0,
+ column_counter_sig_1,
+ column_counter_sig_2,
+ column_counter_sig_3,
+ column_counter_sig_4,
+ column_counter_sig_5,
+ column_counter_sig_6,
+ column_counter_sig_7,
+ column_counter_sig_8,
+ column_counter_sig_9,
+ vsync_counter_9,
+ vsync_counter_8,
+ vsync_counter_7,
+ vsync_counter_6,
+ vsync_counter_5,
+ vsync_counter_4,
+ vsync_counter_3,
+ vsync_counter_2,
+ vsync_counter_1,
+ vsync_counter_0,
+ hsync_counter_9,
+ hsync_counter_8,
+ hsync_counter_7,
+ hsync_counter_6,
+ hsync_counter_5,
+ hsync_counter_4,
+ hsync_counter_3,
+ hsync_counter_2,
+ hsync_counter_1,
+ hsync_counter_0,
+ d_set_vsync_counter,
+ v_sync,
+ h_sync,
+ h_enable_sig,
+ v_enable_sig,
+ reset_pin_c,
+ un6_dly_counter_0_x,
+ d_set_hsync_counter,
+ clk_pin_c
+)
+;
+output line_counter_sig_0 ;
+output line_counter_sig_1 ;
+output line_counter_sig_2 ;
+output line_counter_sig_3 ;
+output line_counter_sig_4 ;
+output line_counter_sig_5 ;
+output line_counter_sig_6 ;
+output line_counter_sig_7 ;
+output line_counter_sig_8 ;
+input dly_counter_1 ;
+input dly_counter_0 ;
+output vsync_state_2 ;
+output vsync_state_5 ;
+output vsync_state_3 ;
+output vsync_state_6 ;
+output vsync_state_4 ;
+output vsync_state_1 ;
+output vsync_state_0 ;
+output hsync_state_2 ;
+output hsync_state_4 ;
+output hsync_state_0 ;
+output hsync_state_5 ;
+output hsync_state_1 ;
+output hsync_state_3 ;
+output hsync_state_6 ;
+output column_counter_sig_0 ;
+output column_counter_sig_1 ;
+output column_counter_sig_2 ;
+output column_counter_sig_3 ;
+output column_counter_sig_4 ;
+output column_counter_sig_5 ;
+output column_counter_sig_6 ;
+output column_counter_sig_7 ;
+output column_counter_sig_8 ;
+output column_counter_sig_9 ;
+output vsync_counter_9 ;
+output vsync_counter_8 ;
+output vsync_counter_7 ;
+output vsync_counter_6 ;
+output vsync_counter_5 ;
+output vsync_counter_4 ;
+output vsync_counter_3 ;
+output vsync_counter_2 ;
+output vsync_counter_1 ;
+output vsync_counter_0 ;
+output hsync_counter_9 ;
+output hsync_counter_8 ;
+output hsync_counter_7 ;
+output hsync_counter_6 ;
+output hsync_counter_5 ;
+output hsync_counter_4 ;
+output hsync_counter_3 ;
+output hsync_counter_2 ;
+output hsync_counter_1 ;
+output hsync_counter_0 ;
+output d_set_vsync_counter ;
+output v_sync ;
+output h_sync ;
+output h_enable_sig ;
+output v_enable_sig ;
+input reset_pin_c ;
+output un6_dly_counter_0_x ;
+output d_set_hsync_counter ;
+input clk_pin_c ;
+wire line_counter_sig_0 ;
+wire line_counter_sig_1 ;
+wire line_counter_sig_2 ;
+wire line_counter_sig_3 ;
+wire line_counter_sig_4 ;
+wire line_counter_sig_5 ;
+wire line_counter_sig_6 ;
+wire line_counter_sig_7 ;
+wire line_counter_sig_8 ;
+wire dly_counter_1 ;
+wire dly_counter_0 ;
+wire vsync_state_2 ;
+wire vsync_state_5 ;
+wire vsync_state_3 ;
+wire vsync_state_6 ;
+wire vsync_state_4 ;
+wire vsync_state_1 ;
+wire vsync_state_0 ;
+wire hsync_state_2 ;
+wire hsync_state_4 ;
+wire hsync_state_0 ;
+wire hsync_state_5 ;
+wire hsync_state_1 ;
+wire hsync_state_3 ;
+wire hsync_state_6 ;
+wire column_counter_sig_0 ;
+wire column_counter_sig_1 ;
+wire column_counter_sig_2 ;
+wire column_counter_sig_3 ;
+wire column_counter_sig_4 ;
+wire column_counter_sig_5 ;
+wire column_counter_sig_6 ;
+wire column_counter_sig_7 ;
+wire column_counter_sig_8 ;
+wire column_counter_sig_9 ;
+wire vsync_counter_9 ;
+wire vsync_counter_8 ;
+wire vsync_counter_7 ;
+wire vsync_counter_6 ;
+wire vsync_counter_5 ;
+wire vsync_counter_4 ;
+wire vsync_counter_3 ;
+wire vsync_counter_2 ;
+wire vsync_counter_1 ;
+wire vsync_counter_0 ;
+wire hsync_counter_9 ;
+wire hsync_counter_8 ;
+wire hsync_counter_7 ;
+wire hsync_counter_6 ;
+wire hsync_counter_5 ;
+wire hsync_counter_4 ;
+wire hsync_counter_3 ;
+wire hsync_counter_2 ;
+wire hsync_counter_1 ;
+wire hsync_counter_0 ;
+wire d_set_vsync_counter ;
+wire v_sync ;
+wire h_sync ;
+wire h_enable_sig ;
+wire v_enable_sig ;
+wire reset_pin_c ;
+wire un6_dly_counter_0_x ;
+wire d_set_hsync_counter ;
+wire clk_pin_c ;
+wire [8:0] hsync_counter_cout;
+wire [8:0] vsync_counter_cout;
+wire [9:1] un2_column_counter_next_combout;
+wire [9:1] un1_line_counter_sig_combout;
+wire [7:1] un1_line_counter_sig_cout;
+wire [1:1] un1_line_counter_sig_a_cout;
+wire [7:0] un2_column_counter_next_cout;
+wire hsync_counter_next_1_sqmuxa ;
+wire G_2_i ;
+wire un9_hsync_counterlt9 ;
+wire vsync_counter_next_1_sqmuxa ;
+wire G_16_i ;
+wire un9_vsync_counterlt9 ;
+wire un10_column_counter_siglto9 ;
+wire column_counter_next_0_sqmuxa_1_1 ;
+wire vsync_state_3_iv_0_0__g0_0_a3_0 ;
+wire vsync_state_next_2_sqmuxa ;
+wire un12_vsync_counter_7 ;
+wire un13_vsync_counter_4 ;
+wire un10_line_counter_siglto8 ;
+wire line_counter_next_0_sqmuxa_1_1 ;
+wire v_enable_sig_1_0_0_0_g0_i_o4 ;
+wire h_enable_sig_1_0_0_0_g0_i_o4 ;
+wire h_sync_1_0_0_0_g1 ;
+wire v_sync_1_0_0_0_g1 ;
+wire un14_vsync_counter_8 ;
+wire hsync_state_3_0_0_0__g0_0 ;
+wire un10_hsync_counter_3 ;
+wire un10_hsync_counter_1 ;
+wire un10_hsync_counter_4 ;
+wire un12_hsync_counter ;
+wire un11_hsync_counter_2 ;
+wire un11_hsync_counter_3 ;
+wire un13_hsync_counter ;
+wire vsync_state_next_1_sqmuxa_1 ;
+wire vsync_state_next_1_sqmuxa_3 ;
+wire un1_vsync_state_next_1_sqmuxa_0 ;
+wire hsync_state_next_1_sqmuxa_1 ;
+wire hsync_state_next_1_sqmuxa_2 ;
+wire un1_hsync_state_next_1_sqmuxa_0 ;
+wire un12_vsync_counter_6 ;
+wire un15_vsync_counter_4 ;
+wire vsync_state_next_1_sqmuxa_2 ;
+wire un10_line_counter_siglto5 ;
+wire un10_column_counter_siglt6 ;
+wire un13_hsync_counter_2 ;
+wire un13_hsync_counter_7 ;
+wire un9_hsync_counterlt9_3 ;
+wire un9_vsync_counterlt9_5 ;
+wire un9_vsync_counterlt9_6 ;
+wire un12_hsync_counter_3 ;
+wire un12_hsync_counter_4 ;
+wire un10_line_counter_siglt4_2 ;
+wire un15_vsync_counter_3 ;
+wire un13_vsync_counter_3 ;
+wire un10_column_counter_siglt6_4 ;
+wire un1_vsync_state_2_0 ;
+wire un1_hsync_state_3_0 ;
+wire VCC ;
+wire GND ;
+wire line_counter_next_0_sqmuxa_1_1_i ;
+wire column_counter_next_0_sqmuxa_1_1_i ;
+wire un9_vsync_counterlt9_i ;
+wire G_16_i_i ;
+wire un9_hsync_counterlt9_i ;
+wire G_2_i_i ;
+//@1:1
+ assign VCC = 1'b1;
+ assign GND = 1'b0;
+// @13:158
+ stratix_lcell hsync_counter_0_ (
+ .regout(hsync_counter_0),
+ .cout(hsync_counter_cout[0]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_0),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_0_.operation_mode="arithmetic";
+defparam hsync_counter_0_.output_mode="reg_only";
+defparam hsync_counter_0_.lut_mask="55aa";
+defparam hsync_counter_0_.synch_mode="on";
+defparam hsync_counter_0_.sum_lutc_input="datac";
+// @13:158
+ stratix_lcell hsync_counter_1_ (
+ .regout(hsync_counter_1),
+ .cout(hsync_counter_cout[1]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_1),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[0]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_1_.cin_used="true";
+defparam hsync_counter_1_.operation_mode="arithmetic";
+defparam hsync_counter_1_.output_mode="reg_only";
+defparam hsync_counter_1_.lut_mask="5aa0";
+defparam hsync_counter_1_.synch_mode="on";
+defparam hsync_counter_1_.sum_lutc_input="cin";
+// @13:158
+ stratix_lcell hsync_counter_2_ (
+ .regout(hsync_counter_2),
+ .cout(hsync_counter_cout[2]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_2),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[1]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_2_.cin_used="true";
+defparam hsync_counter_2_.operation_mode="arithmetic";
+defparam hsync_counter_2_.output_mode="reg_only";
+defparam hsync_counter_2_.lut_mask="5aa0";
+defparam hsync_counter_2_.synch_mode="on";
+defparam hsync_counter_2_.sum_lutc_input="cin";
+// @13:158
+ stratix_lcell hsync_counter_3_ (
+ .regout(hsync_counter_3),
+ .cout(hsync_counter_cout[3]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_3),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[2]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_3_.cin_used="true";
+defparam hsync_counter_3_.operation_mode="arithmetic";
+defparam hsync_counter_3_.output_mode="reg_only";
+defparam hsync_counter_3_.lut_mask="5aa0";
+defparam hsync_counter_3_.synch_mode="on";
+defparam hsync_counter_3_.sum_lutc_input="cin";
+// @13:158
+ stratix_lcell hsync_counter_4_ (
+ .regout(hsync_counter_4),
+ .cout(hsync_counter_cout[4]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_4),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[3]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_4_.cin_used="true";
+defparam hsync_counter_4_.operation_mode="arithmetic";
+defparam hsync_counter_4_.output_mode="reg_only";
+defparam hsync_counter_4_.lut_mask="5aa0";
+defparam hsync_counter_4_.synch_mode="on";
+defparam hsync_counter_4_.sum_lutc_input="cin";
+// @13:158
+ stratix_lcell hsync_counter_5_ (
+ .regout(hsync_counter_5),
+ .cout(hsync_counter_cout[5]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_5),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[4]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_5_.cin_used="true";
+defparam hsync_counter_5_.operation_mode="arithmetic";
+defparam hsync_counter_5_.output_mode="reg_only";
+defparam hsync_counter_5_.lut_mask="5aa0";
+defparam hsync_counter_5_.synch_mode="on";
+defparam hsync_counter_5_.sum_lutc_input="cin";
+// @13:158
+ stratix_lcell hsync_counter_6_ (
+ .regout(hsync_counter_6),
+ .cout(hsync_counter_cout[6]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_6),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[5]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_6_.cin_used="true";
+defparam hsync_counter_6_.operation_mode="arithmetic";
+defparam hsync_counter_6_.output_mode="reg_only";
+defparam hsync_counter_6_.lut_mask="5aa0";
+defparam hsync_counter_6_.synch_mode="on";
+defparam hsync_counter_6_.sum_lutc_input="cin";
+// @13:158
+ stratix_lcell hsync_counter_7_ (
+ .regout(hsync_counter_7),
+ .cout(hsync_counter_cout[7]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_7),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[6]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_7_.cin_used="true";
+defparam hsync_counter_7_.operation_mode="arithmetic";
+defparam hsync_counter_7_.output_mode="reg_only";
+defparam hsync_counter_7_.lut_mask="5aa0";
+defparam hsync_counter_7_.synch_mode="on";
+defparam hsync_counter_7_.sum_lutc_input="cin";
+// @13:158
+ stratix_lcell hsync_counter_8_ (
+ .regout(hsync_counter_8),
+ .cout(hsync_counter_cout[8]),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_8),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[7]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_8_.cin_used="true";
+defparam hsync_counter_8_.operation_mode="arithmetic";
+defparam hsync_counter_8_.output_mode="reg_only";
+defparam hsync_counter_8_.lut_mask="5aa0";
+defparam hsync_counter_8_.synch_mode="on";
+defparam hsync_counter_8_.sum_lutc_input="cin";
+// @13:158
+ stratix_lcell hsync_counter_9_ (
+ .regout(hsync_counter_9),
+ .clk(clk_pin_c),
+ .dataa(hsync_counter_9),
+ .datab(VCC),
+ .datac(hsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_2_i_i),
+ .sload(un9_hsync_counterlt9_i),
+ .ena(VCC),
+ .cin(hsync_counter_cout[8]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_9_.cin_used="true";
+defparam hsync_counter_9_.operation_mode="normal";
+defparam hsync_counter_9_.output_mode="reg_only";
+defparam hsync_counter_9_.lut_mask="5a5a";
+defparam hsync_counter_9_.synch_mode="on";
+defparam hsync_counter_9_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_0_ (
+ .regout(vsync_counter_0),
+ .cout(vsync_counter_cout[0]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_0),
+ .datab(d_set_hsync_counter),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_0_.operation_mode="arithmetic";
+defparam vsync_counter_0_.output_mode="reg_only";
+defparam vsync_counter_0_.lut_mask="6688";
+defparam vsync_counter_0_.synch_mode="on";
+defparam vsync_counter_0_.sum_lutc_input="datac";
+// @13:267
+ stratix_lcell vsync_counter_1_ (
+ .regout(vsync_counter_1),
+ .cout(vsync_counter_cout[1]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_1),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[0]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_1_.cin_used="true";
+defparam vsync_counter_1_.operation_mode="arithmetic";
+defparam vsync_counter_1_.output_mode="reg_only";
+defparam vsync_counter_1_.lut_mask="5aa0";
+defparam vsync_counter_1_.synch_mode="on";
+defparam vsync_counter_1_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_2_ (
+ .regout(vsync_counter_2),
+ .cout(vsync_counter_cout[2]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_2),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[1]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_2_.cin_used="true";
+defparam vsync_counter_2_.operation_mode="arithmetic";
+defparam vsync_counter_2_.output_mode="reg_only";
+defparam vsync_counter_2_.lut_mask="5aa0";
+defparam vsync_counter_2_.synch_mode="on";
+defparam vsync_counter_2_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_3_ (
+ .regout(vsync_counter_3),
+ .cout(vsync_counter_cout[3]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_3),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[2]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_3_.cin_used="true";
+defparam vsync_counter_3_.operation_mode="arithmetic";
+defparam vsync_counter_3_.output_mode="reg_only";
+defparam vsync_counter_3_.lut_mask="5aa0";
+defparam vsync_counter_3_.synch_mode="on";
+defparam vsync_counter_3_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_4_ (
+ .regout(vsync_counter_4),
+ .cout(vsync_counter_cout[4]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_4),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[3]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_4_.cin_used="true";
+defparam vsync_counter_4_.operation_mode="arithmetic";
+defparam vsync_counter_4_.output_mode="reg_only";
+defparam vsync_counter_4_.lut_mask="5aa0";
+defparam vsync_counter_4_.synch_mode="on";
+defparam vsync_counter_4_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_5_ (
+ .regout(vsync_counter_5),
+ .cout(vsync_counter_cout[5]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_5),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[4]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_5_.cin_used="true";
+defparam vsync_counter_5_.operation_mode="arithmetic";
+defparam vsync_counter_5_.output_mode="reg_only";
+defparam vsync_counter_5_.lut_mask="5aa0";
+defparam vsync_counter_5_.synch_mode="on";
+defparam vsync_counter_5_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_6_ (
+ .regout(vsync_counter_6),
+ .cout(vsync_counter_cout[6]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_6),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[5]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_6_.cin_used="true";
+defparam vsync_counter_6_.operation_mode="arithmetic";
+defparam vsync_counter_6_.output_mode="reg_only";
+defparam vsync_counter_6_.lut_mask="5aa0";
+defparam vsync_counter_6_.synch_mode="on";
+defparam vsync_counter_6_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_7_ (
+ .regout(vsync_counter_7),
+ .cout(vsync_counter_cout[7]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_7),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[6]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_7_.cin_used="true";
+defparam vsync_counter_7_.operation_mode="arithmetic";
+defparam vsync_counter_7_.output_mode="reg_only";
+defparam vsync_counter_7_.lut_mask="5aa0";
+defparam vsync_counter_7_.synch_mode="on";
+defparam vsync_counter_7_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_8_ (
+ .regout(vsync_counter_8),
+ .cout(vsync_counter_cout[8]),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_8),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[7]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_8_.cin_used="true";
+defparam vsync_counter_8_.operation_mode="arithmetic";
+defparam vsync_counter_8_.output_mode="reg_only";
+defparam vsync_counter_8_.lut_mask="5aa0";
+defparam vsync_counter_8_.synch_mode="on";
+defparam vsync_counter_8_.sum_lutc_input="cin";
+// @13:267
+ stratix_lcell vsync_counter_9_ (
+ .regout(vsync_counter_9),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_9),
+ .datab(VCC),
+ .datac(vsync_counter_next_1_sqmuxa),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(G_16_i_i),
+ .sload(un9_vsync_counterlt9_i),
+ .ena(VCC),
+ .cin(vsync_counter_cout[8]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_9_.cin_used="true";
+defparam vsync_counter_9_.operation_mode="normal";
+defparam vsync_counter_9_.output_mode="reg_only";
+defparam vsync_counter_9_.lut_mask="5a5a";
+defparam vsync_counter_9_.synch_mode="on";
+defparam vsync_counter_9_.sum_lutc_input="cin";
+// @13:97
+ stratix_lcell column_counter_sig_9_ (
+ .regout(column_counter_sig_9),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[9]),
+ .datab(un10_column_counter_siglto9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(column_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_9_.operation_mode="normal";
+defparam column_counter_sig_9_.output_mode="reg_only";
+defparam column_counter_sig_9_.lut_mask="bbbb";
+defparam column_counter_sig_9_.synch_mode="on";
+defparam column_counter_sig_9_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_8_ (
+ .regout(column_counter_sig_8),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[8]),
+ .datab(un10_column_counter_siglto9),
+ .datac(column_counter_next_0_sqmuxa_1_1),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_8_.operation_mode="normal";
+defparam column_counter_sig_8_.output_mode="reg_only";
+defparam column_counter_sig_8_.lut_mask="8080";
+defparam column_counter_sig_8_.synch_mode="off";
+defparam column_counter_sig_8_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_7_ (
+ .regout(column_counter_sig_7),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[7]),
+ .datab(un10_column_counter_siglto9),
+ .datac(column_counter_next_0_sqmuxa_1_1),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_7_.operation_mode="normal";
+defparam column_counter_sig_7_.output_mode="reg_only";
+defparam column_counter_sig_7_.lut_mask="8080";
+defparam column_counter_sig_7_.synch_mode="off";
+defparam column_counter_sig_7_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_6_ (
+ .regout(column_counter_sig_6),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[6]),
+ .datab(un10_column_counter_siglto9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(column_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_6_.operation_mode="normal";
+defparam column_counter_sig_6_.output_mode="reg_only";
+defparam column_counter_sig_6_.lut_mask="bbbb";
+defparam column_counter_sig_6_.synch_mode="on";
+defparam column_counter_sig_6_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_5_ (
+ .regout(column_counter_sig_5),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[5]),
+ .datab(un10_column_counter_siglto9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(column_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_5_.operation_mode="normal";
+defparam column_counter_sig_5_.output_mode="reg_only";
+defparam column_counter_sig_5_.lut_mask="bbbb";
+defparam column_counter_sig_5_.synch_mode="on";
+defparam column_counter_sig_5_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_4_ (
+ .regout(column_counter_sig_4),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[4]),
+ .datab(un10_column_counter_siglto9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(column_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_4_.operation_mode="normal";
+defparam column_counter_sig_4_.output_mode="reg_only";
+defparam column_counter_sig_4_.lut_mask="bbbb";
+defparam column_counter_sig_4_.synch_mode="on";
+defparam column_counter_sig_4_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_3_ (
+ .regout(column_counter_sig_3),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[3]),
+ .datab(un10_column_counter_siglto9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(column_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_3_.operation_mode="normal";
+defparam column_counter_sig_3_.output_mode="reg_only";
+defparam column_counter_sig_3_.lut_mask="bbbb";
+defparam column_counter_sig_3_.synch_mode="on";
+defparam column_counter_sig_3_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_2_ (
+ .regout(column_counter_sig_2),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[2]),
+ .datab(un10_column_counter_siglto9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(column_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_2_.operation_mode="normal";
+defparam column_counter_sig_2_.output_mode="reg_only";
+defparam column_counter_sig_2_.lut_mask="bbbb";
+defparam column_counter_sig_2_.synch_mode="on";
+defparam column_counter_sig_2_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_1_ (
+ .regout(column_counter_sig_1),
+ .clk(clk_pin_c),
+ .dataa(un2_column_counter_next_combout[1]),
+ .datab(un10_column_counter_siglto9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(column_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_1_.operation_mode="normal";
+defparam column_counter_sig_1_.output_mode="reg_only";
+defparam column_counter_sig_1_.lut_mask="bbbb";
+defparam column_counter_sig_1_.synch_mode="on";
+defparam column_counter_sig_1_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell column_counter_sig_0_ (
+ .regout(column_counter_sig_0),
+ .clk(clk_pin_c),
+ .dataa(column_counter_sig_0),
+ .datab(un10_column_counter_siglto9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(column_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_sig_0_.operation_mode="normal";
+defparam column_counter_sig_0_.output_mode="reg_only";
+defparam column_counter_sig_0_.lut_mask="7777";
+defparam column_counter_sig_0_.synch_mode="on";
+defparam column_counter_sig_0_.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell hsync_state_6_ (
+ .regout(hsync_state_6),
+ .clk(clk_pin_c),
+ .dataa(VCC),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(un6_dly_counter_0_x),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_6_.operation_mode="normal";
+defparam hsync_state_6_.output_mode="reg_only";
+defparam hsync_state_6_.lut_mask="ff00";
+defparam hsync_state_6_.synch_mode="off";
+defparam hsync_state_6_.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell vsync_state_0_ (
+ .regout(vsync_state_0),
+ .clk(clk_pin_c),
+ .dataa(vsync_state_0),
+ .datab(vsync_state_3_iv_0_0__g0_0_a3_0),
+ .datac(un6_dly_counter_0_x),
+ .datad(vsync_state_next_2_sqmuxa),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_0_.operation_mode="normal";
+defparam vsync_state_0_.output_mode="reg_only";
+defparam vsync_state_0_.lut_mask="0cae";
+defparam vsync_state_0_.synch_mode="off";
+defparam vsync_state_0_.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell vsync_state_1_ (
+ .regout(vsync_state_1),
+ .clk(clk_pin_c),
+ .dataa(vsync_state_4),
+ .datab(un12_vsync_counter_7),
+ .datac(un13_vsync_counter_4),
+ .datad(un6_dly_counter_0_x),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_1_.operation_mode="normal";
+defparam vsync_state_1_.output_mode="reg_only";
+defparam vsync_state_1_.lut_mask="0080";
+defparam vsync_state_1_.synch_mode="off";
+defparam vsync_state_1_.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell vsync_state_6_ (
+ .combout(un6_dly_counter_0_x),
+ .regout(vsync_state_6),
+ .clk(clk_pin_c),
+ .dataa(reset_pin_c),
+ .datab(dly_counter_0),
+ .datac(dly_counter_1),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_6_.operation_mode="normal";
+defparam vsync_state_6_.output_mode="reg_and_comb";
+defparam vsync_state_6_.lut_mask="7f7f";
+defparam vsync_state_6_.synch_mode="off";
+defparam vsync_state_6_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_8_ (
+ .regout(line_counter_sig_8),
+ .clk(clk_pin_c),
+ .dataa(un10_line_counter_siglto8),
+ .datab(un1_line_counter_sig_combout[9]),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(line_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_8_.operation_mode="normal";
+defparam line_counter_sig_8_.output_mode="reg_only";
+defparam line_counter_sig_8_.lut_mask="dddd";
+defparam line_counter_sig_8_.synch_mode="on";
+defparam line_counter_sig_8_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_7_ (
+ .regout(line_counter_sig_7),
+ .clk(clk_pin_c),
+ .dataa(un10_line_counter_siglto8),
+ .datab(un1_line_counter_sig_combout[8]),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(line_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_7_.operation_mode="normal";
+defparam line_counter_sig_7_.output_mode="reg_only";
+defparam line_counter_sig_7_.lut_mask="dddd";
+defparam line_counter_sig_7_.synch_mode="on";
+defparam line_counter_sig_7_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_6_ (
+ .regout(line_counter_sig_6),
+ .clk(clk_pin_c),
+ .dataa(un10_line_counter_siglto8),
+ .datab(un1_line_counter_sig_combout[7]),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(line_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_6_.operation_mode="normal";
+defparam line_counter_sig_6_.output_mode="reg_only";
+defparam line_counter_sig_6_.lut_mask="dddd";
+defparam line_counter_sig_6_.synch_mode="on";
+defparam line_counter_sig_6_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_5_ (
+ .regout(line_counter_sig_5),
+ .clk(clk_pin_c),
+ .dataa(un10_line_counter_siglto8),
+ .datab(un1_line_counter_sig_combout[6]),
+ .datac(line_counter_next_0_sqmuxa_1_1),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_5_.operation_mode="normal";
+defparam line_counter_sig_5_.output_mode="reg_only";
+defparam line_counter_sig_5_.lut_mask="8080";
+defparam line_counter_sig_5_.synch_mode="off";
+defparam line_counter_sig_5_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_4_ (
+ .regout(line_counter_sig_4),
+ .clk(clk_pin_c),
+ .dataa(un10_line_counter_siglto8),
+ .datab(un1_line_counter_sig_combout[5]),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(line_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_4_.operation_mode="normal";
+defparam line_counter_sig_4_.output_mode="reg_only";
+defparam line_counter_sig_4_.lut_mask="dddd";
+defparam line_counter_sig_4_.synch_mode="on";
+defparam line_counter_sig_4_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_3_ (
+ .regout(line_counter_sig_3),
+ .clk(clk_pin_c),
+ .dataa(un10_line_counter_siglto8),
+ .datab(un1_line_counter_sig_combout[4]),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(line_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_3_.operation_mode="normal";
+defparam line_counter_sig_3_.output_mode="reg_only";
+defparam line_counter_sig_3_.lut_mask="dddd";
+defparam line_counter_sig_3_.synch_mode="on";
+defparam line_counter_sig_3_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_2_ (
+ .regout(line_counter_sig_2),
+ .clk(clk_pin_c),
+ .dataa(un10_line_counter_siglto8),
+ .datab(un1_line_counter_sig_combout[3]),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(line_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_2_.operation_mode="normal";
+defparam line_counter_sig_2_.output_mode="reg_only";
+defparam line_counter_sig_2_.lut_mask="dddd";
+defparam line_counter_sig_2_.synch_mode="on";
+defparam line_counter_sig_2_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_1_ (
+ .regout(line_counter_sig_1),
+ .clk(clk_pin_c),
+ .dataa(un10_line_counter_siglto8),
+ .datab(un1_line_counter_sig_combout[2]),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(line_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_1_.operation_mode="normal";
+defparam line_counter_sig_1_.output_mode="reg_only";
+defparam line_counter_sig_1_.lut_mask="dddd";
+defparam line_counter_sig_1_.synch_mode="on";
+defparam line_counter_sig_1_.sum_lutc_input="datac";
+// @13:125
+ stratix_lcell line_counter_sig_0_ (
+ .regout(line_counter_sig_0),
+ .clk(clk_pin_c),
+ .dataa(un1_line_counter_sig_combout[1]),
+ .datab(un10_line_counter_siglto8),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(line_counter_next_0_sqmuxa_1_1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_sig_0_.operation_mode="normal";
+defparam line_counter_sig_0_.output_mode="reg_only";
+defparam line_counter_sig_0_.lut_mask="bbbb";
+defparam line_counter_sig_0_.synch_mode="on";
+defparam line_counter_sig_0_.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell v_enable_sig_Z (
+ .regout(v_enable_sig),
+ .clk(clk_pin_c),
+ .dataa(hsync_state_3),
+ .datab(hsync_state_1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(v_enable_sig_1_0_0_0_g0_i_o4),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam v_enable_sig_Z.operation_mode="normal";
+defparam v_enable_sig_Z.output_mode="reg_only";
+defparam v_enable_sig_Z.lut_mask="eeee";
+defparam v_enable_sig_Z.synch_mode="on";
+defparam v_enable_sig_Z.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell h_enable_sig_Z (
+ .regout(h_enable_sig),
+ .clk(clk_pin_c),
+ .dataa(vsync_state_3),
+ .datab(vsync_state_1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(h_enable_sig_1_0_0_0_g0_i_o4),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam h_enable_sig_Z.operation_mode="normal";
+defparam h_enable_sig_Z.output_mode="reg_only";
+defparam h_enable_sig_Z.lut_mask="eeee";
+defparam h_enable_sig_Z.synch_mode="on";
+defparam h_enable_sig_Z.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell h_sync_Z (
+ .regout(h_sync),
+ .clk(clk_pin_c),
+ .dataa(reset_pin_c),
+ .datab(dly_counter_0),
+ .datac(dly_counter_1),
+ .datad(h_sync_1_0_0_0_g1),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam h_sync_Z.operation_mode="normal";
+defparam h_sync_Z.output_mode="reg_only";
+defparam h_sync_Z.lut_mask="ff7f";
+defparam h_sync_Z.synch_mode="off";
+defparam h_sync_Z.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell v_sync_Z (
+ .regout(v_sync),
+ .clk(clk_pin_c),
+ .dataa(reset_pin_c),
+ .datab(dly_counter_0),
+ .datac(dly_counter_1),
+ .datad(v_sync_1_0_0_0_g1),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam v_sync_Z.operation_mode="normal";
+defparam v_sync_Z.output_mode="reg_only";
+defparam v_sync_Z.lut_mask="ff7f";
+defparam v_sync_Z.synch_mode="off";
+defparam v_sync_Z.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell vsync_state_5_ (
+ .regout(vsync_state_5),
+ .clk(clk_pin_c),
+ .dataa(vsync_state_6),
+ .datab(vsync_state_0),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(vsync_state_next_2_sqmuxa),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_5_.operation_mode="normal";
+defparam vsync_state_5_.output_mode="reg_only";
+defparam vsync_state_5_.lut_mask="eeee";
+defparam vsync_state_5_.synch_mode="on";
+defparam vsync_state_5_.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell vsync_state_4_ (
+ .regout(vsync_state_4),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_0),
+ .datab(vsync_counter_9),
+ .datac(vsync_state_5),
+ .datad(un14_vsync_counter_8),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(vsync_state_next_2_sqmuxa),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_4_.operation_mode="normal";
+defparam vsync_state_4_.output_mode="reg_only";
+defparam vsync_state_4_.lut_mask="2000";
+defparam vsync_state_4_.synch_mode="on";
+defparam vsync_state_4_.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell vsync_state_3_ (
+ .regout(vsync_state_3),
+ .clk(clk_pin_c),
+ .dataa(vsync_state_1),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(vsync_state_next_2_sqmuxa),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_3_.operation_mode="normal";
+defparam vsync_state_3_.output_mode="reg_only";
+defparam vsync_state_3_.lut_mask="aaaa";
+defparam vsync_state_3_.synch_mode="on";
+defparam vsync_state_3_.sum_lutc_input="datac";
+// @13:300
+ stratix_lcell vsync_state_2_ (
+ .regout(vsync_state_2),
+ .clk(clk_pin_c),
+ .dataa(vsync_counter_0),
+ .datab(vsync_counter_9),
+ .datac(vsync_state_3),
+ .datad(un14_vsync_counter_8),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(vsync_state_next_2_sqmuxa),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_2_.operation_mode="normal";
+defparam vsync_state_2_.output_mode="reg_only";
+defparam vsync_state_2_.lut_mask="8000";
+defparam vsync_state_2_.synch_mode="on";
+defparam vsync_state_2_.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell hsync_state_5_ (
+ .regout(hsync_state_5),
+ .clk(clk_pin_c),
+ .dataa(hsync_state_6),
+ .datab(hsync_state_0),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(hsync_state_3_0_0_0__g0_0),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_5_.operation_mode="normal";
+defparam hsync_state_5_.output_mode="reg_only";
+defparam hsync_state_5_.lut_mask="eeee";
+defparam hsync_state_5_.synch_mode="on";
+defparam hsync_state_5_.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell hsync_state_4_ (
+ .regout(hsync_state_4),
+ .clk(clk_pin_c),
+ .dataa(hsync_state_5),
+ .datab(un10_hsync_counter_3),
+ .datac(un10_hsync_counter_1),
+ .datad(un10_hsync_counter_4),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(hsync_state_3_0_0_0__g0_0),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_4_.operation_mode="normal";
+defparam hsync_state_4_.output_mode="reg_only";
+defparam hsync_state_4_.lut_mask="8000";
+defparam hsync_state_4_.synch_mode="on";
+defparam hsync_state_4_.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell hsync_state_3_ (
+ .regout(hsync_state_3),
+ .clk(clk_pin_c),
+ .dataa(hsync_state_1),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(hsync_state_3_0_0_0__g0_0),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_3_.operation_mode="normal";
+defparam hsync_state_3_.output_mode="reg_only";
+defparam hsync_state_3_.lut_mask="aaaa";
+defparam hsync_state_3_.synch_mode="on";
+defparam hsync_state_3_.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell hsync_state_2_ (
+ .regout(hsync_state_2),
+ .clk(clk_pin_c),
+ .dataa(hsync_state_3),
+ .datab(un12_hsync_counter),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(hsync_state_3_0_0_0__g0_0),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_2_.operation_mode="normal";
+defparam hsync_state_2_.output_mode="reg_only";
+defparam hsync_state_2_.lut_mask="8888";
+defparam hsync_state_2_.synch_mode="on";
+defparam hsync_state_2_.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell hsync_state_1_ (
+ .regout(hsync_state_1),
+ .clk(clk_pin_c),
+ .dataa(hsync_state_4),
+ .datab(un11_hsync_counter_2),
+ .datac(un10_hsync_counter_1),
+ .datad(un11_hsync_counter_3),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(hsync_state_3_0_0_0__g0_0),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_1_.operation_mode="normal";
+defparam hsync_state_1_.output_mode="reg_only";
+defparam hsync_state_1_.lut_mask="8000";
+defparam hsync_state_1_.synch_mode="on";
+defparam hsync_state_1_.sum_lutc_input="datac";
+// @13:187
+ stratix_lcell hsync_state_0_ (
+ .regout(hsync_state_0),
+ .clk(clk_pin_c),
+ .dataa(hsync_state_2),
+ .datab(un13_hsync_counter),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(un6_dly_counter_0_x),
+ .sload(GND),
+ .ena(hsync_state_3_0_0_0__g0_0),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_0_.operation_mode="normal";
+defparam hsync_state_0_.output_mode="reg_only";
+defparam hsync_state_0_.lut_mask="8888";
+defparam hsync_state_0_.synch_mode="on";
+defparam hsync_state_0_.sum_lutc_input="datac";
+// @13:97
+ stratix_lcell vsync_state_next_2_sqmuxa_cZ (
+ .combout(vsync_state_next_2_sqmuxa),
+ .clk(GND),
+ .dataa(un6_dly_counter_0_x),
+ .datab(vsync_state_next_1_sqmuxa_1),
+ .datac(vsync_state_next_1_sqmuxa_3),
+ .datad(un1_vsync_state_next_1_sqmuxa_0),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_next_2_sqmuxa_cZ.operation_mode="normal";
+defparam vsync_state_next_2_sqmuxa_cZ.output_mode="comb_only";
+defparam vsync_state_next_2_sqmuxa_cZ.lut_mask="aaab";
+defparam vsync_state_next_2_sqmuxa_cZ.synch_mode="off";
+defparam vsync_state_next_2_sqmuxa_cZ.sum_lutc_input="datac";
+ stratix_lcell hsync_state_3_0_0_0__g0_0_cZ (
+ .combout(hsync_state_3_0_0_0__g0_0),
+ .clk(GND),
+ .dataa(hsync_state_next_1_sqmuxa_1),
+ .datab(hsync_state_next_1_sqmuxa_2),
+ .datac(un6_dly_counter_0_x),
+ .datad(un1_hsync_state_next_1_sqmuxa_0),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_3_0_0_0__g0_0_cZ.operation_mode="normal";
+defparam hsync_state_3_0_0_0__g0_0_cZ.output_mode="comb_only";
+defparam hsync_state_3_0_0_0__g0_0_cZ.lut_mask="f0f1";
+defparam hsync_state_3_0_0_0__g0_0_cZ.synch_mode="off";
+defparam hsync_state_3_0_0_0__g0_0_cZ.sum_lutc_input="datac";
+// @13:206
+ stratix_lcell un1_hsync_state_next_1_sqmuxa_0_cZ (
+ .combout(un1_hsync_state_next_1_sqmuxa_0),
+ .clk(GND),
+ .dataa(hsync_state_2),
+ .datab(hsync_state_3),
+ .datac(un13_hsync_counter),
+ .datad(un12_hsync_counter),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.lut_mask="0ace";
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
+defparam un1_hsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
+// @13:319
+ stratix_lcell un1_vsync_state_next_1_sqmuxa_0_cZ (
+ .combout(un1_vsync_state_next_1_sqmuxa_0),
+ .clk(GND),
+ .dataa(vsync_state_2),
+ .datab(un12_vsync_counter_6),
+ .datac(un15_vsync_counter_4),
+ .datad(vsync_state_next_1_sqmuxa_2),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.lut_mask="ff2a";
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
+defparam un1_vsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
+ stratix_lcell vsync_state_3_iv_0_0__g0_0_a3_0_cZ (
+ .combout(vsync_state_3_iv_0_0__g0_0_a3_0),
+ .clk(GND),
+ .dataa(vsync_state_2),
+ .datab(un12_vsync_counter_6),
+ .datac(un15_vsync_counter_4),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.operation_mode="normal";
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.output_mode="comb_only";
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lut_mask="8080";
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.synch_mode="off";
+defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.sum_lutc_input="datac";
+// @13:139
+ stratix_lcell LINE_COUNT_next_un10_line_counter_siglto8 (
+ .combout(un10_line_counter_siglto8),
+ .clk(GND),
+ .dataa(line_counter_sig_6),
+ .datab(line_counter_sig_7),
+ .datac(line_counter_sig_8),
+ .datad(un10_line_counter_siglto5),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam LINE_COUNT_next_un10_line_counter_siglto8.operation_mode="normal";
+defparam LINE_COUNT_next_un10_line_counter_siglto8.output_mode="comb_only";
+defparam LINE_COUNT_next_un10_line_counter_siglto8.lut_mask="ff7f";
+defparam LINE_COUNT_next_un10_line_counter_siglto8.synch_mode="off";
+defparam LINE_COUNT_next_un10_line_counter_siglto8.sum_lutc_input="datac";
+// @10:161
+ stratix_lcell G_2 (
+ .combout(G_2_i),
+ .clk(GND),
+ .dataa(hsync_state_0),
+ .datab(hsync_state_6),
+ .datac(un9_hsync_counterlt9),
+ .datad(un6_dly_counter_0_x),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam G_2.operation_mode="normal";
+defparam G_2.output_mode="comb_only";
+defparam G_2.lut_mask="0f1f";
+defparam G_2.synch_mode="off";
+defparam G_2.sum_lutc_input="datac";
+// @13:326
+ stratix_lcell vsync_state_next_1_sqmuxa_1_cZ (
+ .combout(vsync_state_next_1_sqmuxa_1),
+ .clk(GND),
+ .dataa(vsync_counter_0),
+ .datab(vsync_counter_9),
+ .datac(vsync_state_5),
+ .datad(un14_vsync_counter_8),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
+defparam vsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
+defparam vsync_state_next_1_sqmuxa_1_cZ.lut_mask="d0f0";
+defparam vsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
+defparam vsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
+// @13:331
+ stratix_lcell vsync_state_next_1_sqmuxa_2_cZ (
+ .combout(vsync_state_next_1_sqmuxa_2),
+ .clk(GND),
+ .dataa(vsync_state_4),
+ .datab(un12_vsync_counter_7),
+ .datac(un13_vsync_counter_4),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
+defparam vsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
+defparam vsync_state_next_1_sqmuxa_2_cZ.lut_mask="2a2a";
+defparam vsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
+defparam vsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
+// @13:339
+ stratix_lcell vsync_state_next_1_sqmuxa_3_cZ (
+ .combout(vsync_state_next_1_sqmuxa_3),
+ .clk(GND),
+ .dataa(vsync_counter_0),
+ .datab(vsync_counter_9),
+ .datac(vsync_state_3),
+ .datad(un14_vsync_counter_8),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_state_next_1_sqmuxa_3_cZ.operation_mode="normal";
+defparam vsync_state_next_1_sqmuxa_3_cZ.output_mode="comb_only";
+defparam vsync_state_next_1_sqmuxa_3_cZ.lut_mask="70f0";
+defparam vsync_state_next_1_sqmuxa_3_cZ.synch_mode="off";
+defparam vsync_state_next_1_sqmuxa_3_cZ.sum_lutc_input="datac";
+// @10:161
+ stratix_lcell G_16 (
+ .combout(G_16_i),
+ .clk(GND),
+ .dataa(vsync_state_0),
+ .datab(vsync_state_6),
+ .datac(un9_vsync_counterlt9),
+ .datad(un6_dly_counter_0_x),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam G_16.operation_mode="normal";
+defparam G_16.output_mode="comb_only";
+defparam G_16.lut_mask="0f1f";
+defparam G_16.synch_mode="off";
+defparam G_16.sum_lutc_input="datac";
+// @13:111
+ stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglto9 (
+ .combout(un10_column_counter_siglto9),
+ .clk(GND),
+ .dataa(column_counter_sig_7),
+ .datab(column_counter_sig_8),
+ .datac(column_counter_sig_9),
+ .datad(un10_column_counter_siglt6),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.operation_mode="normal";
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.output_mode="comb_only";
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.lut_mask="1f0f";
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.synch_mode="off";
+defparam COLUMN_COUNT_next_un10_column_counter_siglto9.sum_lutc_input="datac";
+// @13:218
+ stratix_lcell hsync_state_next_1_sqmuxa_2_cZ (
+ .combout(hsync_state_next_1_sqmuxa_2),
+ .clk(GND),
+ .dataa(hsync_state_4),
+ .datab(un11_hsync_counter_2),
+ .datac(un10_hsync_counter_1),
+ .datad(un11_hsync_counter_3),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
+defparam hsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
+defparam hsync_state_next_1_sqmuxa_2_cZ.lut_mask="2aaa";
+defparam hsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
+defparam hsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
+// @13:213
+ stratix_lcell hsync_state_next_1_sqmuxa_1_cZ (
+ .combout(hsync_state_next_1_sqmuxa_1),
+ .clk(GND),
+ .dataa(hsync_state_5),
+ .datab(un10_hsync_counter_3),
+ .datac(un10_hsync_counter_1),
+ .datad(un10_hsync_counter_4),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
+defparam hsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
+defparam hsync_state_next_1_sqmuxa_1_cZ.lut_mask="2aaa";
+defparam hsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
+defparam hsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
+// @13:231
+ stratix_lcell HSYNC_FSM_next_un13_hsync_counter (
+ .combout(un13_hsync_counter),
+ .clk(GND),
+ .dataa(hsync_counter_6),
+ .datab(hsync_counter_7),
+ .datac(un13_hsync_counter_2),
+ .datad(un13_hsync_counter_7),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un13_hsync_counter.operation_mode="normal";
+defparam HSYNC_FSM_next_un13_hsync_counter.output_mode="comb_only";
+defparam HSYNC_FSM_next_un13_hsync_counter.lut_mask="1000";
+defparam HSYNC_FSM_next_un13_hsync_counter.synch_mode="off";
+defparam HSYNC_FSM_next_un13_hsync_counter.sum_lutc_input="datac";
+// @13:172
+ stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9 (
+ .combout(un9_hsync_counterlt9),
+ .clk(GND),
+ .dataa(hsync_counter_8),
+ .datab(hsync_counter_9),
+ .datac(un9_hsync_counterlt9_3),
+ .datad(un13_hsync_counter_7),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.operation_mode="normal";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.output_mode="comb_only";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.lut_mask="f7ff";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.synch_mode="off";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9.sum_lutc_input="datac";
+// @13:281
+ stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9 (
+ .combout(un9_vsync_counterlt9),
+ .clk(GND),
+ .dataa(vsync_counter_4),
+ .datab(vsync_counter_5),
+ .datac(un9_vsync_counterlt9_5),
+ .datad(un9_vsync_counterlt9_6),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.operation_mode="normal";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.output_mode="comb_only";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.lut_mask="fff7";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.synch_mode="off";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9.sum_lutc_input="datac";
+// @13:226
+ stratix_lcell HSYNC_FSM_next_un12_hsync_counter (
+ .combout(un12_hsync_counter),
+ .clk(GND),
+ .dataa(hsync_counter_0),
+ .datab(hsync_counter_1),
+ .datac(un12_hsync_counter_3),
+ .datad(un12_hsync_counter_4),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un12_hsync_counter.operation_mode="normal";
+defparam HSYNC_FSM_next_un12_hsync_counter.output_mode="comb_only";
+defparam HSYNC_FSM_next_un12_hsync_counter.lut_mask="8000";
+defparam HSYNC_FSM_next_un12_hsync_counter.synch_mode="off";
+defparam HSYNC_FSM_next_un12_hsync_counter.sum_lutc_input="datac";
+// @13:139
+ stratix_lcell LINE_COUNT_next_un10_line_counter_siglto5 (
+ .combout(un10_line_counter_siglto5),
+ .clk(GND),
+ .dataa(line_counter_sig_1),
+ .datab(line_counter_sig_2),
+ .datac(line_counter_sig_5),
+ .datad(un10_line_counter_siglt4_2),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam LINE_COUNT_next_un10_line_counter_siglto5.operation_mode="normal";
+defparam LINE_COUNT_next_un10_line_counter_siglto5.output_mode="comb_only";
+defparam LINE_COUNT_next_un10_line_counter_siglto5.lut_mask="0f07";
+defparam LINE_COUNT_next_un10_line_counter_siglto5.synch_mode="off";
+defparam LINE_COUNT_next_un10_line_counter_siglto5.sum_lutc_input="datac";
+// @13:344
+ stratix_lcell VSYNC_FSM_next_un15_vsync_counter_4 (
+ .combout(un15_vsync_counter_4),
+ .clk(GND),
+ .dataa(vsync_counter_1),
+ .datab(vsync_counter_4),
+ .datac(un15_vsync_counter_3),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_FSM_next_un15_vsync_counter_4.operation_mode="normal";
+defparam VSYNC_FSM_next_un15_vsync_counter_4.output_mode="comb_only";
+defparam VSYNC_FSM_next_un15_vsync_counter_4.lut_mask="1010";
+defparam VSYNC_FSM_next_un15_vsync_counter_4.synch_mode="off";
+defparam VSYNC_FSM_next_un15_vsync_counter_4.sum_lutc_input="datac";
+// @13:331
+ stratix_lcell VSYNC_FSM_next_un13_vsync_counter_4 (
+ .combout(un13_vsync_counter_4),
+ .clk(GND),
+ .dataa(vsync_counter_0),
+ .datab(vsync_counter_5),
+ .datac(un13_vsync_counter_3),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_FSM_next_un13_vsync_counter_4.operation_mode="normal";
+defparam VSYNC_FSM_next_un13_vsync_counter_4.output_mode="comb_only";
+defparam VSYNC_FSM_next_un13_vsync_counter_4.lut_mask="8080";
+defparam VSYNC_FSM_next_un13_vsync_counter_4.synch_mode="off";
+defparam VSYNC_FSM_next_un13_vsync_counter_4.sum_lutc_input="datac";
+// @13:111
+ stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6 (
+ .combout(un10_column_counter_siglt6),
+ .clk(GND),
+ .dataa(column_counter_sig_4),
+ .datab(column_counter_sig_6),
+ .datac(column_counter_sig_5),
+ .datad(un10_column_counter_siglt6_4),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.operation_mode="normal";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.output_mode="comb_only";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.lut_mask="ff7f";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.synch_mode="off";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6.sum_lutc_input="datac";
+// @13:169
+ stratix_lcell hsync_counter_next_1_sqmuxa_cZ (
+ .combout(hsync_counter_next_1_sqmuxa),
+ .clk(GND),
+ .dataa(reset_pin_c),
+ .datab(dly_counter_0),
+ .datac(dly_counter_1),
+ .datad(d_set_hsync_counter),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam hsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
+defparam hsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
+defparam hsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
+defparam hsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
+defparam hsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
+// @13:339
+ stratix_lcell VSYNC_FSM_next_un14_vsync_counter_8 (
+ .combout(un14_vsync_counter_8),
+ .clk(GND),
+ .dataa(un12_vsync_counter_6),
+ .datab(un12_vsync_counter_7),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_FSM_next_un14_vsync_counter_8.operation_mode="normal";
+defparam VSYNC_FSM_next_un14_vsync_counter_8.output_mode="comb_only";
+defparam VSYNC_FSM_next_un14_vsync_counter_8.lut_mask="8888";
+defparam VSYNC_FSM_next_un14_vsync_counter_8.synch_mode="off";
+defparam VSYNC_FSM_next_un14_vsync_counter_8.sum_lutc_input="datac";
+// @13:139
+ stratix_lcell line_counter_next_0_sqmuxa_1_1_cZ (
+ .combout(line_counter_next_0_sqmuxa_1_1),
+ .clk(GND),
+ .dataa(reset_pin_c),
+ .datab(dly_counter_0),
+ .datac(dly_counter_1),
+ .datad(vsync_state_1),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam line_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
+defparam line_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
+defparam line_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
+defparam line_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
+defparam line_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
+ stratix_lcell v_sync_1_0_0_0_g1_cZ (
+ .combout(v_sync_1_0_0_0_g1),
+ .clk(GND),
+ .dataa(vsync_state_2),
+ .datab(v_sync),
+ .datac(vsync_state_4),
+ .datad(un1_vsync_state_2_0),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam v_sync_1_0_0_0_g1_cZ.operation_mode="normal";
+defparam v_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
+defparam v_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
+defparam v_sync_1_0_0_0_g1_cZ.synch_mode="off";
+defparam v_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
+ stratix_lcell h_enable_sig_1_0_0_0_g0_i_o4_cZ (
+ .combout(h_enable_sig_1_0_0_0_g0_i_o4),
+ .clk(GND),
+ .dataa(vsync_state_4),
+ .datab(vsync_state_5),
+ .datac(un6_dly_counter_0_x),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
+defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
+// @13:278
+ stratix_lcell vsync_counter_next_1_sqmuxa_cZ (
+ .combout(vsync_counter_next_1_sqmuxa),
+ .clk(GND),
+ .dataa(reset_pin_c),
+ .datab(dly_counter_0),
+ .datac(dly_counter_1),
+ .datad(d_set_vsync_counter),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam vsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
+defparam vsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
+defparam vsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
+defparam vsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
+defparam vsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
+ stratix_lcell v_enable_sig_1_0_0_0_g0_i_o4_cZ (
+ .combout(v_enable_sig_1_0_0_0_g0_i_o4),
+ .clk(GND),
+ .dataa(hsync_state_4),
+ .datab(hsync_state_5),
+ .datac(un6_dly_counter_0_x),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
+defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
+ stratix_lcell h_sync_1_0_0_0_g1_cZ (
+ .combout(h_sync_1_0_0_0_g1),
+ .clk(GND),
+ .dataa(hsync_state_2),
+ .datab(h_sync),
+ .datac(hsync_state_4),
+ .datad(un1_hsync_state_3_0),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam h_sync_1_0_0_0_g1_cZ.operation_mode="normal";
+defparam h_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
+defparam h_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
+defparam h_sync_1_0_0_0_g1_cZ.synch_mode="off";
+defparam h_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
+// @13:111
+ stratix_lcell column_counter_next_0_sqmuxa_1_1_cZ (
+ .combout(column_counter_next_0_sqmuxa_1_1),
+ .clk(GND),
+ .dataa(reset_pin_c),
+ .datab(dly_counter_0),
+ .datac(dly_counter_1),
+ .datad(hsync_state_1),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam column_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
+defparam column_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
+defparam column_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
+defparam column_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
+defparam column_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
+// @13:226
+ stratix_lcell HSYNC_FSM_next_un12_hsync_counter_4 (
+ .combout(un12_hsync_counter_4),
+ .clk(GND),
+ .dataa(hsync_counter_6),
+ .datab(hsync_counter_7),
+ .datac(hsync_counter_9),
+ .datad(hsync_counter_3),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un12_hsync_counter_4.operation_mode="normal";
+defparam HSYNC_FSM_next_un12_hsync_counter_4.output_mode="comb_only";
+defparam HSYNC_FSM_next_un12_hsync_counter_4.lut_mask="0010";
+defparam HSYNC_FSM_next_un12_hsync_counter_4.synch_mode="off";
+defparam HSYNC_FSM_next_un12_hsync_counter_4.sum_lutc_input="datac";
+// @13:226
+ stratix_lcell HSYNC_FSM_next_un12_hsync_counter_3 (
+ .combout(un12_hsync_counter_3),
+ .clk(GND),
+ .dataa(hsync_counter_2),
+ .datab(hsync_counter_8),
+ .datac(hsync_counter_4),
+ .datad(hsync_counter_5),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un12_hsync_counter_3.operation_mode="normal";
+defparam HSYNC_FSM_next_un12_hsync_counter_3.output_mode="comb_only";
+defparam HSYNC_FSM_next_un12_hsync_counter_3.lut_mask="0008";
+defparam HSYNC_FSM_next_un12_hsync_counter_3.synch_mode="off";
+defparam HSYNC_FSM_next_un12_hsync_counter_3.sum_lutc_input="datac";
+// @13:218
+ stratix_lcell HSYNC_FSM_next_un11_hsync_counter_3 (
+ .combout(un11_hsync_counter_3),
+ .clk(GND),
+ .dataa(hsync_counter_0),
+ .datab(hsync_counter_1),
+ .datac(hsync_counter_3),
+ .datad(hsync_counter_4),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un11_hsync_counter_3.operation_mode="normal";
+defparam HSYNC_FSM_next_un11_hsync_counter_3.output_mode="comb_only";
+defparam HSYNC_FSM_next_un11_hsync_counter_3.lut_mask="0008";
+defparam HSYNC_FSM_next_un11_hsync_counter_3.synch_mode="off";
+defparam HSYNC_FSM_next_un11_hsync_counter_3.sum_lutc_input="datac";
+// @13:218
+ stratix_lcell HSYNC_FSM_next_un11_hsync_counter_2 (
+ .combout(un11_hsync_counter_2),
+ .clk(GND),
+ .dataa(hsync_counter_2),
+ .datab(hsync_counter_7),
+ .datac(hsync_counter_6),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un11_hsync_counter_2.operation_mode="normal";
+defparam HSYNC_FSM_next_un11_hsync_counter_2.output_mode="comb_only";
+defparam HSYNC_FSM_next_un11_hsync_counter_2.lut_mask="0808";
+defparam HSYNC_FSM_next_un11_hsync_counter_2.synch_mode="off";
+defparam HSYNC_FSM_next_un11_hsync_counter_2.sum_lutc_input="datac";
+// @13:172
+ stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9_3 (
+ .combout(un9_hsync_counterlt9_3),
+ .clk(GND),
+ .dataa(hsync_counter_6),
+ .datab(hsync_counter_7),
+ .datac(hsync_counter_4),
+ .datad(hsync_counter_5),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.operation_mode="normal";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.output_mode="comb_only";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.lut_mask="7fff";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.synch_mode="off";
+defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.sum_lutc_input="datac";
+// @13:231
+ stratix_lcell HSYNC_FSM_next_un13_hsync_counter_2 (
+ .combout(un13_hsync_counter_2),
+ .clk(GND),
+ .dataa(hsync_counter_8),
+ .datab(hsync_counter_9),
+ .datac(hsync_counter_4),
+ .datad(hsync_counter_5),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un13_hsync_counter_2.operation_mode="normal";
+defparam HSYNC_FSM_next_un13_hsync_counter_2.output_mode="comb_only";
+defparam HSYNC_FSM_next_un13_hsync_counter_2.lut_mask="0080";
+defparam HSYNC_FSM_next_un13_hsync_counter_2.synch_mode="off";
+defparam HSYNC_FSM_next_un13_hsync_counter_2.sum_lutc_input="datac";
+// @13:281
+ stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_6 (
+ .combout(un9_vsync_counterlt9_6),
+ .clk(GND),
+ .dataa(vsync_counter_2),
+ .datab(vsync_counter_3),
+ .datac(vsync_counter_0),
+ .datad(vsync_counter_1),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.operation_mode="normal";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.output_mode="comb_only";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.lut_mask="7fff";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.synch_mode="off";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.sum_lutc_input="datac";
+// @13:281
+ stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_5 (
+ .combout(un9_vsync_counterlt9_5),
+ .clk(GND),
+ .dataa(vsync_counter_8),
+ .datab(vsync_counter_9),
+ .datac(vsync_counter_6),
+ .datad(vsync_counter_7),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.operation_mode="normal";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.output_mode="comb_only";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.lut_mask="7fff";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.synch_mode="off";
+defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.sum_lutc_input="datac";
+// @13:213
+ stratix_lcell HSYNC_FSM_next_un10_hsync_counter_4 (
+ .combout(un10_hsync_counter_4),
+ .clk(GND),
+ .dataa(hsync_counter_4),
+ .datab(hsync_counter_6),
+ .datac(hsync_counter_1),
+ .datad(hsync_counter_3),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un10_hsync_counter_4.operation_mode="normal";
+defparam HSYNC_FSM_next_un10_hsync_counter_4.output_mode="comb_only";
+defparam HSYNC_FSM_next_un10_hsync_counter_4.lut_mask="8000";
+defparam HSYNC_FSM_next_un10_hsync_counter_4.synch_mode="off";
+defparam HSYNC_FSM_next_un10_hsync_counter_4.sum_lutc_input="datac";
+// @13:213
+ stratix_lcell HSYNC_FSM_next_un10_hsync_counter_3 (
+ .combout(un10_hsync_counter_3),
+ .clk(GND),
+ .dataa(hsync_counter_0),
+ .datab(hsync_counter_7),
+ .datac(hsync_counter_2),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un10_hsync_counter_3.operation_mode="normal";
+defparam HSYNC_FSM_next_un10_hsync_counter_3.output_mode="comb_only";
+defparam HSYNC_FSM_next_un10_hsync_counter_3.lut_mask="0101";
+defparam HSYNC_FSM_next_un10_hsync_counter_3.synch_mode="off";
+defparam HSYNC_FSM_next_un10_hsync_counter_3.sum_lutc_input="datac";
+// @13:344
+ stratix_lcell VSYNC_FSM_next_un15_vsync_counter_3 (
+ .combout(un15_vsync_counter_3),
+ .clk(GND),
+ .dataa(vsync_counter_9),
+ .datab(vsync_counter_2),
+ .datac(vsync_counter_3),
+ .datad(vsync_counter_0),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_FSM_next_un15_vsync_counter_3.operation_mode="normal";
+defparam VSYNC_FSM_next_un15_vsync_counter_3.output_mode="comb_only";
+defparam VSYNC_FSM_next_un15_vsync_counter_3.lut_mask="0020";
+defparam VSYNC_FSM_next_un15_vsync_counter_3.synch_mode="off";
+defparam VSYNC_FSM_next_un15_vsync_counter_3.sum_lutc_input="datac";
+// @13:331
+ stratix_lcell VSYNC_FSM_next_un13_vsync_counter_3 (
+ .combout(un13_vsync_counter_3),
+ .clk(GND),
+ .dataa(vsync_counter_6),
+ .datab(vsync_counter_7),
+ .datac(vsync_counter_8),
+ .datad(vsync_counter_9),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_FSM_next_un13_vsync_counter_3.operation_mode="normal";
+defparam VSYNC_FSM_next_un13_vsync_counter_3.output_mode="comb_only";
+defparam VSYNC_FSM_next_un13_vsync_counter_3.lut_mask="0001";
+defparam VSYNC_FSM_next_un13_vsync_counter_3.synch_mode="off";
+defparam VSYNC_FSM_next_un13_vsync_counter_3.sum_lutc_input="datac";
+// @13:111
+ stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_4 (
+ .combout(un10_column_counter_siglt6_4),
+ .clk(GND),
+ .dataa(column_counter_sig_2),
+ .datab(column_counter_sig_3),
+ .datac(column_counter_sig_0),
+ .datad(column_counter_sig_1),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.operation_mode="normal";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.output_mode="comb_only";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.lut_mask="7fff";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.synch_mode="off";
+defparam COLUMN_COUNT_next_un10_column_counter_siglt6_4.sum_lutc_input="datac";
+// @13:139
+ stratix_lcell LINE_COUNT_next_un10_line_counter_siglt4_2 (
+ .combout(un10_line_counter_siglt4_2),
+ .clk(GND),
+ .dataa(line_counter_sig_3),
+ .datab(line_counter_sig_4),
+ .datac(line_counter_sig_0),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.operation_mode="normal";
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.output_mode="comb_only";
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.lut_mask="7f7f";
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.synch_mode="off";
+defparam LINE_COUNT_next_un10_line_counter_siglt4_2.sum_lutc_input="datac";
+// @13:213
+ stratix_lcell HSYNC_FSM_next_un10_hsync_counter_1 (
+ .combout(un10_hsync_counter_1),
+ .clk(GND),
+ .dataa(hsync_counter_5),
+ .datab(hsync_counter_8),
+ .datac(hsync_counter_9),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un10_hsync_counter_1.operation_mode="normal";
+defparam HSYNC_FSM_next_un10_hsync_counter_1.output_mode="comb_only";
+defparam HSYNC_FSM_next_un10_hsync_counter_1.lut_mask="0101";
+defparam HSYNC_FSM_next_un10_hsync_counter_1.synch_mode="off";
+defparam HSYNC_FSM_next_un10_hsync_counter_1.sum_lutc_input="datac";
+// @13:326
+ stratix_lcell VSYNC_FSM_next_un12_vsync_counter_6 (
+ .combout(un12_vsync_counter_6),
+ .clk(GND),
+ .dataa(vsync_counter_7),
+ .datab(vsync_counter_8),
+ .datac(vsync_counter_5),
+ .datad(vsync_counter_6),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_FSM_next_un12_vsync_counter_6.operation_mode="normal";
+defparam VSYNC_FSM_next_un12_vsync_counter_6.output_mode="comb_only";
+defparam VSYNC_FSM_next_un12_vsync_counter_6.lut_mask="0001";
+defparam VSYNC_FSM_next_un12_vsync_counter_6.synch_mode="off";
+defparam VSYNC_FSM_next_un12_vsync_counter_6.sum_lutc_input="datac";
+// @13:326
+ stratix_lcell VSYNC_FSM_next_un12_vsync_counter_7 (
+ .combout(un12_vsync_counter_7),
+ .clk(GND),
+ .dataa(vsync_counter_3),
+ .datab(vsync_counter_4),
+ .datac(vsync_counter_1),
+ .datad(vsync_counter_2),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam VSYNC_FSM_next_un12_vsync_counter_7.operation_mode="normal";
+defparam VSYNC_FSM_next_un12_vsync_counter_7.output_mode="comb_only";
+defparam VSYNC_FSM_next_un12_vsync_counter_7.lut_mask="0001";
+defparam VSYNC_FSM_next_un12_vsync_counter_7.synch_mode="off";
+defparam VSYNC_FSM_next_un12_vsync_counter_7.sum_lutc_input="datac";
+// @13:231
+ stratix_lcell HSYNC_FSM_next_un13_hsync_counter_7 (
+ .combout(un13_hsync_counter_7),
+ .clk(GND),
+ .dataa(hsync_counter_2),
+ .datab(hsync_counter_3),
+ .datac(hsync_counter_0),
+ .datad(hsync_counter_1),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam HSYNC_FSM_next_un13_hsync_counter_7.operation_mode="normal";
+defparam HSYNC_FSM_next_un13_hsync_counter_7.output_mode="comb_only";
+defparam HSYNC_FSM_next_un13_hsync_counter_7.lut_mask="8000";
+defparam HSYNC_FSM_next_un13_hsync_counter_7.synch_mode="off";
+defparam HSYNC_FSM_next_un13_hsync_counter_7.sum_lutc_input="datac";
+// @13:206
+ stratix_lcell un1_hsync_state_3_0_cZ (
+ .combout(un1_hsync_state_3_0),
+ .clk(GND),
+ .dataa(hsync_state_3),
+ .datab(hsync_state_1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_hsync_state_3_0_cZ.operation_mode="normal";
+defparam un1_hsync_state_3_0_cZ.output_mode="comb_only";
+defparam un1_hsync_state_3_0_cZ.lut_mask="eeee";
+defparam un1_hsync_state_3_0_cZ.synch_mode="off";
+defparam un1_hsync_state_3_0_cZ.sum_lutc_input="datac";
+// @13:319
+ stratix_lcell un1_vsync_state_2_0_cZ (
+ .combout(un1_vsync_state_2_0),
+ .clk(GND),
+ .dataa(vsync_state_3),
+ .datab(vsync_state_1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_vsync_state_2_0_cZ.operation_mode="normal";
+defparam un1_vsync_state_2_0_cZ.output_mode="comb_only";
+defparam un1_vsync_state_2_0_cZ.lut_mask="eeee";
+defparam un1_vsync_state_2_0_cZ.synch_mode="off";
+defparam un1_vsync_state_2_0_cZ.sum_lutc_input="datac";
+// @13:248
+ stratix_lcell d_set_hsync_counter_cZ (
+ .combout(d_set_hsync_counter),
+ .clk(GND),
+ .dataa(hsync_state_6),
+ .datab(hsync_state_0),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam d_set_hsync_counter_cZ.operation_mode="normal";
+defparam d_set_hsync_counter_cZ.output_mode="comb_only";
+defparam d_set_hsync_counter_cZ.lut_mask="eeee";
+defparam d_set_hsync_counter_cZ.synch_mode="off";
+defparam d_set_hsync_counter_cZ.sum_lutc_input="datac";
+// @13:361
+ stratix_lcell d_set_vsync_counter_cZ (
+ .combout(d_set_vsync_counter),
+ .clk(GND),
+ .dataa(vsync_state_6),
+ .datab(vsync_state_0),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam d_set_vsync_counter_cZ.operation_mode="normal";
+defparam d_set_vsync_counter_cZ.output_mode="comb_only";
+defparam d_set_vsync_counter_cZ.lut_mask="eeee";
+defparam d_set_vsync_counter_cZ.synch_mode="off";
+defparam d_set_vsync_counter_cZ.sum_lutc_input="datac";
+// @13:141
+ stratix_lcell un1_line_counter_sig_9_ (
+ .combout(un1_line_counter_sig_combout[9]),
+ .clk(GND),
+ .dataa(line_counter_sig_7),
+ .datab(line_counter_sig_8),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un1_line_counter_sig_cout[7]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_9_.cin_used="true";
+defparam un1_line_counter_sig_9_.operation_mode="normal";
+defparam un1_line_counter_sig_9_.output_mode="comb_only";
+defparam un1_line_counter_sig_9_.lut_mask="6c6c";
+defparam un1_line_counter_sig_9_.synch_mode="off";
+defparam un1_line_counter_sig_9_.sum_lutc_input="cin";
+// @13:141
+ stratix_lcell un1_line_counter_sig_8_ (
+ .combout(un1_line_counter_sig_combout[8]),
+ .clk(GND),
+ .dataa(line_counter_sig_7),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un1_line_counter_sig_cout[6]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_8_.cin_used="true";
+defparam un1_line_counter_sig_8_.operation_mode="normal";
+defparam un1_line_counter_sig_8_.output_mode="comb_only";
+defparam un1_line_counter_sig_8_.lut_mask="5a5a";
+defparam un1_line_counter_sig_8_.synch_mode="off";
+defparam un1_line_counter_sig_8_.sum_lutc_input="cin";
+// @13:141
+ stratix_lcell un1_line_counter_sig_7_ (
+ .combout(un1_line_counter_sig_combout[7]),
+ .cout(un1_line_counter_sig_cout[7]),
+ .clk(GND),
+ .dataa(line_counter_sig_5),
+ .datab(line_counter_sig_6),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un1_line_counter_sig_cout[5]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_7_.cin_used="true";
+defparam un1_line_counter_sig_7_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_7_.output_mode="comb_only";
+defparam un1_line_counter_sig_7_.lut_mask="6c80";
+defparam un1_line_counter_sig_7_.synch_mode="off";
+defparam un1_line_counter_sig_7_.sum_lutc_input="cin";
+// @13:141
+ stratix_lcell un1_line_counter_sig_6_ (
+ .combout(un1_line_counter_sig_combout[6]),
+ .cout(un1_line_counter_sig_cout[6]),
+ .clk(GND),
+ .dataa(line_counter_sig_5),
+ .datab(line_counter_sig_6),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un1_line_counter_sig_cout[4]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_6_.cin_used="true";
+defparam un1_line_counter_sig_6_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_6_.output_mode="comb_only";
+defparam un1_line_counter_sig_6_.lut_mask="5a80";
+defparam un1_line_counter_sig_6_.synch_mode="off";
+defparam un1_line_counter_sig_6_.sum_lutc_input="cin";
+// @13:141
+ stratix_lcell un1_line_counter_sig_5_ (
+ .combout(un1_line_counter_sig_combout[5]),
+ .cout(un1_line_counter_sig_cout[5]),
+ .clk(GND),
+ .dataa(line_counter_sig_3),
+ .datab(line_counter_sig_4),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un1_line_counter_sig_cout[3]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_5_.cin_used="true";
+defparam un1_line_counter_sig_5_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_5_.output_mode="comb_only";
+defparam un1_line_counter_sig_5_.lut_mask="6c80";
+defparam un1_line_counter_sig_5_.synch_mode="off";
+defparam un1_line_counter_sig_5_.sum_lutc_input="cin";
+// @13:141
+ stratix_lcell un1_line_counter_sig_4_ (
+ .combout(un1_line_counter_sig_combout[4]),
+ .cout(un1_line_counter_sig_cout[4]),
+ .clk(GND),
+ .dataa(line_counter_sig_3),
+ .datab(line_counter_sig_4),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un1_line_counter_sig_cout[2]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_4_.cin_used="true";
+defparam un1_line_counter_sig_4_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_4_.output_mode="comb_only";
+defparam un1_line_counter_sig_4_.lut_mask="5a80";
+defparam un1_line_counter_sig_4_.synch_mode="off";
+defparam un1_line_counter_sig_4_.sum_lutc_input="cin";
+// @13:141
+ stratix_lcell un1_line_counter_sig_3_ (
+ .combout(un1_line_counter_sig_combout[3]),
+ .cout(un1_line_counter_sig_cout[3]),
+ .clk(GND),
+ .dataa(line_counter_sig_1),
+ .datab(line_counter_sig_2),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un1_line_counter_sig_cout[1]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_3_.cin_used="true";
+defparam un1_line_counter_sig_3_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_3_.output_mode="comb_only";
+defparam un1_line_counter_sig_3_.lut_mask="6c80";
+defparam un1_line_counter_sig_3_.synch_mode="off";
+defparam un1_line_counter_sig_3_.sum_lutc_input="cin";
+// @13:141
+ stratix_lcell un1_line_counter_sig_2_ (
+ .combout(un1_line_counter_sig_combout[2]),
+ .cout(un1_line_counter_sig_cout[2]),
+ .clk(GND),
+ .dataa(line_counter_sig_1),
+ .datab(line_counter_sig_2),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un1_line_counter_sig_a_cout[1]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_2_.cin_used="true";
+defparam un1_line_counter_sig_2_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_2_.output_mode="comb_only";
+defparam un1_line_counter_sig_2_.lut_mask="5a80";
+defparam un1_line_counter_sig_2_.synch_mode="off";
+defparam un1_line_counter_sig_2_.sum_lutc_input="cin";
+// @13:141
+ stratix_lcell un1_line_counter_sig_a_1_ (
+ .cout(un1_line_counter_sig_a_cout[1]),
+ .clk(GND),
+ .dataa(d_set_hsync_counter),
+ .datab(line_counter_sig_0),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_a_1_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_a_1_.output_mode="comb_only";
+defparam un1_line_counter_sig_a_1_.lut_mask="0088";
+defparam un1_line_counter_sig_a_1_.synch_mode="off";
+defparam un1_line_counter_sig_a_1_.sum_lutc_input="datac";
+// @13:141
+ stratix_lcell un1_line_counter_sig_1_ (
+ .combout(un1_line_counter_sig_combout[1]),
+ .cout(un1_line_counter_sig_cout[1]),
+ .clk(GND),
+ .dataa(d_set_hsync_counter),
+ .datab(line_counter_sig_0),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un1_line_counter_sig_1_.operation_mode="arithmetic";
+defparam un1_line_counter_sig_1_.output_mode="comb_only";
+defparam un1_line_counter_sig_1_.lut_mask="6688";
+defparam un1_line_counter_sig_1_.synch_mode="off";
+defparam un1_line_counter_sig_1_.sum_lutc_input="datac";
+// @13:112
+ stratix_lcell un2_column_counter_next_9_ (
+ .combout(un2_column_counter_next_combout[9]),
+ .clk(GND),
+ .dataa(column_counter_sig_8),
+ .datab(column_counter_sig_9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_column_counter_next_cout[7]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_9_.cin_used="true";
+defparam un2_column_counter_next_9_.operation_mode="normal";
+defparam un2_column_counter_next_9_.output_mode="comb_only";
+defparam un2_column_counter_next_9_.lut_mask="6c6c";
+defparam un2_column_counter_next_9_.synch_mode="off";
+defparam un2_column_counter_next_9_.sum_lutc_input="cin";
+// @13:112
+ stratix_lcell un2_column_counter_next_8_ (
+ .combout(un2_column_counter_next_combout[8]),
+ .clk(GND),
+ .dataa(column_counter_sig_8),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_column_counter_next_cout[6]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_8_.cin_used="true";
+defparam un2_column_counter_next_8_.operation_mode="normal";
+defparam un2_column_counter_next_8_.output_mode="comb_only";
+defparam un2_column_counter_next_8_.lut_mask="5a5a";
+defparam un2_column_counter_next_8_.synch_mode="off";
+defparam un2_column_counter_next_8_.sum_lutc_input="cin";
+// @13:112
+ stratix_lcell un2_column_counter_next_7_ (
+ .combout(un2_column_counter_next_combout[7]),
+ .cout(un2_column_counter_next_cout[7]),
+ .clk(GND),
+ .dataa(column_counter_sig_6),
+ .datab(column_counter_sig_7),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_column_counter_next_cout[5]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_7_.cin_used="true";
+defparam un2_column_counter_next_7_.operation_mode="arithmetic";
+defparam un2_column_counter_next_7_.output_mode="comb_only";
+defparam un2_column_counter_next_7_.lut_mask="6c80";
+defparam un2_column_counter_next_7_.synch_mode="off";
+defparam un2_column_counter_next_7_.sum_lutc_input="cin";
+// @13:112
+ stratix_lcell un2_column_counter_next_6_ (
+ .combout(un2_column_counter_next_combout[6]),
+ .cout(un2_column_counter_next_cout[6]),
+ .clk(GND),
+ .dataa(column_counter_sig_6),
+ .datab(column_counter_sig_7),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_column_counter_next_cout[4]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_6_.cin_used="true";
+defparam un2_column_counter_next_6_.operation_mode="arithmetic";
+defparam un2_column_counter_next_6_.output_mode="comb_only";
+defparam un2_column_counter_next_6_.lut_mask="5a80";
+defparam un2_column_counter_next_6_.synch_mode="off";
+defparam un2_column_counter_next_6_.sum_lutc_input="cin";
+// @13:112
+ stratix_lcell un2_column_counter_next_5_ (
+ .combout(un2_column_counter_next_combout[5]),
+ .cout(un2_column_counter_next_cout[5]),
+ .clk(GND),
+ .dataa(column_counter_sig_4),
+ .datab(column_counter_sig_5),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_column_counter_next_cout[3]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_5_.cin_used="true";
+defparam un2_column_counter_next_5_.operation_mode="arithmetic";
+defparam un2_column_counter_next_5_.output_mode="comb_only";
+defparam un2_column_counter_next_5_.lut_mask="6c80";
+defparam un2_column_counter_next_5_.synch_mode="off";
+defparam un2_column_counter_next_5_.sum_lutc_input="cin";
+// @13:112
+ stratix_lcell un2_column_counter_next_4_ (
+ .combout(un2_column_counter_next_combout[4]),
+ .cout(un2_column_counter_next_cout[4]),
+ .clk(GND),
+ .dataa(column_counter_sig_4),
+ .datab(column_counter_sig_5),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_column_counter_next_cout[2]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_4_.cin_used="true";
+defparam un2_column_counter_next_4_.operation_mode="arithmetic";
+defparam un2_column_counter_next_4_.output_mode="comb_only";
+defparam un2_column_counter_next_4_.lut_mask="5a80";
+defparam un2_column_counter_next_4_.synch_mode="off";
+defparam un2_column_counter_next_4_.sum_lutc_input="cin";
+// @13:112
+ stratix_lcell un2_column_counter_next_3_ (
+ .combout(un2_column_counter_next_combout[3]),
+ .cout(un2_column_counter_next_cout[3]),
+ .clk(GND),
+ .dataa(column_counter_sig_2),
+ .datab(column_counter_sig_3),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_column_counter_next_cout[1]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_3_.cin_used="true";
+defparam un2_column_counter_next_3_.operation_mode="arithmetic";
+defparam un2_column_counter_next_3_.output_mode="comb_only";
+defparam un2_column_counter_next_3_.lut_mask="6c80";
+defparam un2_column_counter_next_3_.synch_mode="off";
+defparam un2_column_counter_next_3_.sum_lutc_input="cin";
+// @13:112
+ stratix_lcell un2_column_counter_next_2_ (
+ .combout(un2_column_counter_next_combout[2]),
+ .cout(un2_column_counter_next_cout[2]),
+ .clk(GND),
+ .dataa(column_counter_sig_2),
+ .datab(column_counter_sig_3),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_column_counter_next_cout[0]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_2_.cin_used="true";
+defparam un2_column_counter_next_2_.operation_mode="arithmetic";
+defparam un2_column_counter_next_2_.output_mode="comb_only";
+defparam un2_column_counter_next_2_.lut_mask="5a80";
+defparam un2_column_counter_next_2_.synch_mode="off";
+defparam un2_column_counter_next_2_.sum_lutc_input="cin";
+// @13:112
+ stratix_lcell un2_column_counter_next_1_ (
+ .combout(un2_column_counter_next_combout[1]),
+ .cout(un2_column_counter_next_cout[1]),
+ .clk(GND),
+ .dataa(column_counter_sig_0),
+ .datab(column_counter_sig_1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_1_.operation_mode="arithmetic";
+defparam un2_column_counter_next_1_.output_mode="comb_only";
+defparam un2_column_counter_next_1_.lut_mask="6688";
+defparam un2_column_counter_next_1_.synch_mode="off";
+defparam un2_column_counter_next_1_.sum_lutc_input="datac";
+// @13:112
+ stratix_lcell un2_column_counter_next_0_ (
+ .cout(un2_column_counter_next_cout[0]),
+ .clk(GND),
+ .dataa(column_counter_sig_0),
+ .datab(column_counter_sig_1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_column_counter_next_0_.operation_mode="arithmetic";
+defparam un2_column_counter_next_0_.output_mode="comb_only";
+defparam un2_column_counter_next_0_.lut_mask="5588";
+defparam un2_column_counter_next_0_.synch_mode="off";
+defparam un2_column_counter_next_0_.sum_lutc_input="datac";
+ assign line_counter_next_0_sqmuxa_1_1_i = ~ line_counter_next_0_sqmuxa_1_1;
+ assign column_counter_next_0_sqmuxa_1_1_i = ~ column_counter_next_0_sqmuxa_1_1;
+ assign un9_vsync_counterlt9_i = ~ un9_vsync_counterlt9;
+ assign G_16_i_i = ~ G_16_i;
+ assign un9_hsync_counterlt9_i = ~ un9_hsync_counterlt9;
+ assign G_2_i_i = ~ G_2_i;
+endmodule /* vga_driver */
+
+// VQM4.1+
+module vga_control (
+ line_counter_sig_0,
+ line_counter_sig_2,
+ line_counter_sig_1,
+ line_counter_sig_3,
+ line_counter_sig_6,
+ line_counter_sig_5,
+ line_counter_sig_4,
+ line_counter_sig_7,
+ line_counter_sig_8,
+ column_counter_sig_0,
+ column_counter_sig_1,
+ column_counter_sig_2,
+ column_counter_sig_8,
+ column_counter_sig_3,
+ column_counter_sig_5,
+ column_counter_sig_4,
+ column_counter_sig_9,
+ column_counter_sig_7,
+ column_counter_sig_6,
+ toggle_counter_sig_0,
+ toggle_counter_sig_1,
+ toggle_counter_sig_2,
+ toggle_counter_sig_3,
+ toggle_counter_sig_4,
+ toggle_counter_sig_5,
+ toggle_counter_sig_6,
+ toggle_counter_sig_7,
+ toggle_counter_sig_8,
+ toggle_counter_sig_9,
+ toggle_counter_sig_10,
+ toggle_counter_sig_11,
+ toggle_counter_sig_12,
+ toggle_counter_sig_13,
+ toggle_counter_sig_14,
+ toggle_counter_sig_15,
+ toggle_counter_sig_16,
+ toggle_counter_sig_17,
+ toggle_counter_sig_18,
+ toggle_counter_sig_19,
+ toggle_counter_sig_20,
+ toggle_counter_sig_21,
+ toggle_counter_sig_22,
+ toggle_counter_sig_23,
+ toggle_counter_sig_24,
+ h_enable_sig,
+ g,
+ b,
+ v_enable_sig,
+ r,
+ toggle_sig,
+ un6_dly_counter_0_x,
+ clk_pin_c
+)
+;
+input line_counter_sig_0 ;
+input line_counter_sig_2 ;
+input line_counter_sig_1 ;
+input line_counter_sig_3 ;
+input line_counter_sig_6 ;
+input line_counter_sig_5 ;
+input line_counter_sig_4 ;
+input line_counter_sig_7 ;
+input line_counter_sig_8 ;
+input column_counter_sig_0 ;
+input column_counter_sig_1 ;
+input column_counter_sig_2 ;
+input column_counter_sig_8 ;
+input column_counter_sig_3 ;
+input column_counter_sig_5 ;
+input column_counter_sig_4 ;
+input column_counter_sig_9 ;
+input column_counter_sig_7 ;
+input column_counter_sig_6 ;
+output toggle_counter_sig_0 ;
+output toggle_counter_sig_1 ;
+output toggle_counter_sig_2 ;
+output toggle_counter_sig_3 ;
+output toggle_counter_sig_4 ;
+output toggle_counter_sig_5 ;
+output toggle_counter_sig_6 ;
+output toggle_counter_sig_7 ;
+output toggle_counter_sig_8 ;
+output toggle_counter_sig_9 ;
+output toggle_counter_sig_10 ;
+output toggle_counter_sig_11 ;
+output toggle_counter_sig_12 ;
+output toggle_counter_sig_13 ;
+output toggle_counter_sig_14 ;
+output toggle_counter_sig_15 ;
+output toggle_counter_sig_16 ;
+output toggle_counter_sig_17 ;
+output toggle_counter_sig_18 ;
+output toggle_counter_sig_19 ;
+output toggle_counter_sig_20 ;
+output toggle_counter_sig_21 ;
+output toggle_counter_sig_22 ;
+output toggle_counter_sig_23 ;
+output toggle_counter_sig_24 ;
+input h_enable_sig ;
+output g ;
+output b ;
+input v_enable_sig ;
+output r ;
+output toggle_sig ;
+input un6_dly_counter_0_x ;
+input clk_pin_c ;
+wire line_counter_sig_0 ;
+wire line_counter_sig_2 ;
+wire line_counter_sig_1 ;
+wire line_counter_sig_3 ;
+wire line_counter_sig_6 ;
+wire line_counter_sig_5 ;
+wire line_counter_sig_4 ;
+wire line_counter_sig_7 ;
+wire line_counter_sig_8 ;
+wire column_counter_sig_0 ;
+wire column_counter_sig_1 ;
+wire column_counter_sig_2 ;
+wire column_counter_sig_8 ;
+wire column_counter_sig_3 ;
+wire column_counter_sig_5 ;
+wire column_counter_sig_4 ;
+wire column_counter_sig_9 ;
+wire column_counter_sig_7 ;
+wire column_counter_sig_6 ;
+wire toggle_counter_sig_0 ;
+wire toggle_counter_sig_1 ;
+wire toggle_counter_sig_2 ;
+wire toggle_counter_sig_3 ;
+wire toggle_counter_sig_4 ;
+wire toggle_counter_sig_5 ;
+wire toggle_counter_sig_6 ;
+wire toggle_counter_sig_7 ;
+wire toggle_counter_sig_8 ;
+wire toggle_counter_sig_9 ;
+wire toggle_counter_sig_10 ;
+wire toggle_counter_sig_11 ;
+wire toggle_counter_sig_12 ;
+wire toggle_counter_sig_13 ;
+wire toggle_counter_sig_14 ;
+wire toggle_counter_sig_15 ;
+wire toggle_counter_sig_16 ;
+wire toggle_counter_sig_17 ;
+wire toggle_counter_sig_18 ;
+wire toggle_counter_sig_19 ;
+wire toggle_counter_sig_20 ;
+wire toggle_counter_sig_21 ;
+wire toggle_counter_sig_22 ;
+wire toggle_counter_sig_23 ;
+wire toggle_counter_sig_24 ;
+wire h_enable_sig ;
+wire g ;
+wire b ;
+wire v_enable_sig ;
+wire r ;
+wire toggle_sig ;
+wire un6_dly_counter_0_x ;
+wire clk_pin_c ;
+wire [18:1] toggle_counter_sig_cout;
+wire [0:0] un2_toggle_counter_next_cout;
+wire GND ;
+wire toggle_sig_0_0_0_g1 ;
+wire b_next_0_sqmuxa_7_4 ;
+wire b_next_0_sqmuxa_7_5 ;
+wire toggle_sig_0_0_0_g1_2 ;
+wire un1_toggle_counter_siglto18 ;
+wire un1_toggle_counter_siglto15 ;
+wire un5_v_enablelto5 ;
+wire b_next_0_sqmuxa_7_3 ;
+wire un13_v_enablelto6 ;
+wire b_next_0_sqmuxa_7_4_a ;
+wire un17_v_enablelto3 ;
+wire b_next_0_sqmuxa_7_2 ;
+wire un9_v_enablelto6 ;
+wire un1_toggle_counter_siglto12 ;
+wire un5_v_enablelt2 ;
+wire un1_toggle_counter_siglto9 ;
+wire un13_v_enablelto4_0 ;
+wire un9_v_enablelto4 ;
+wire un1_toggle_counter_siglt6 ;
+wire VCC ;
+wire toggle_sig_0_0_0_g1_i ;
+ assign VCC = 1'b1;
+//@1:1
+ assign GND = 1'b0;
+// @12:99
+ stratix_lcell toggle_counter_sig_24_ (
+ .regout(toggle_counter_sig_24),
+ .clk(clk_pin_c),
+ .dataa(VCC),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(GND),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_24_.operation_mode="normal";
+defparam toggle_counter_sig_24_.output_mode="reg_only";
+defparam toggle_counter_sig_24_.lut_mask="ff00";
+defparam toggle_counter_sig_24_.synch_mode="off";
+defparam toggle_counter_sig_24_.sum_lutc_input="datac";
+// @12:99
+ stratix_lcell toggle_counter_sig_23_ (
+ .regout(toggle_counter_sig_23),
+ .clk(clk_pin_c),
+ .dataa(VCC),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(GND),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_23_.operation_mode="normal";
+defparam toggle_counter_sig_23_.output_mode="reg_only";
+defparam toggle_counter_sig_23_.lut_mask="ff00";
+defparam toggle_counter_sig_23_.synch_mode="off";
+defparam toggle_counter_sig_23_.sum_lutc_input="datac";
+// @12:99
+ stratix_lcell toggle_counter_sig_22_ (
+ .regout(toggle_counter_sig_22),
+ .clk(clk_pin_c),
+ .dataa(VCC),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(GND),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_22_.operation_mode="normal";
+defparam toggle_counter_sig_22_.output_mode="reg_only";
+defparam toggle_counter_sig_22_.lut_mask="ff00";
+defparam toggle_counter_sig_22_.synch_mode="off";
+defparam toggle_counter_sig_22_.sum_lutc_input="datac";
+// @12:99
+ stratix_lcell toggle_counter_sig_21_ (
+ .regout(toggle_counter_sig_21),
+ .clk(clk_pin_c),
+ .dataa(VCC),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(GND),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_21_.operation_mode="normal";
+defparam toggle_counter_sig_21_.output_mode="reg_only";
+defparam toggle_counter_sig_21_.lut_mask="ff00";
+defparam toggle_counter_sig_21_.synch_mode="off";
+defparam toggle_counter_sig_21_.sum_lutc_input="datac";
+// @12:99
+ stratix_lcell toggle_counter_sig_20_ (
+ .regout(toggle_counter_sig_20),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_20),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[18]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_20_.cin_used="true";
+defparam toggle_counter_sig_20_.operation_mode="normal";
+defparam toggle_counter_sig_20_.output_mode="reg_only";
+defparam toggle_counter_sig_20_.lut_mask="5a5a";
+defparam toggle_counter_sig_20_.synch_mode="on";
+defparam toggle_counter_sig_20_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_19_ (
+ .regout(toggle_counter_sig_19),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_18),
+ .datab(toggle_counter_sig_19),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[17]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_19_.cin_used="true";
+defparam toggle_counter_sig_19_.operation_mode="normal";
+defparam toggle_counter_sig_19_.output_mode="reg_only";
+defparam toggle_counter_sig_19_.lut_mask="6c6c";
+defparam toggle_counter_sig_19_.synch_mode="on";
+defparam toggle_counter_sig_19_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_18_ (
+ .regout(toggle_counter_sig_18),
+ .cout(toggle_counter_sig_cout[18]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_18),
+ .datab(toggle_counter_sig_19),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[16]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_18_.cin_used="true";
+defparam toggle_counter_sig_18_.operation_mode="arithmetic";
+defparam toggle_counter_sig_18_.output_mode="reg_only";
+defparam toggle_counter_sig_18_.lut_mask="5a80";
+defparam toggle_counter_sig_18_.synch_mode="on";
+defparam toggle_counter_sig_18_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_17_ (
+ .regout(toggle_counter_sig_17),
+ .cout(toggle_counter_sig_cout[17]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_16),
+ .datab(toggle_counter_sig_17),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[15]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_17_.cin_used="true";
+defparam toggle_counter_sig_17_.operation_mode="arithmetic";
+defparam toggle_counter_sig_17_.output_mode="reg_only";
+defparam toggle_counter_sig_17_.lut_mask="6c80";
+defparam toggle_counter_sig_17_.synch_mode="on";
+defparam toggle_counter_sig_17_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_16_ (
+ .regout(toggle_counter_sig_16),
+ .cout(toggle_counter_sig_cout[16]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_16),
+ .datab(toggle_counter_sig_17),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[14]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_16_.cin_used="true";
+defparam toggle_counter_sig_16_.operation_mode="arithmetic";
+defparam toggle_counter_sig_16_.output_mode="reg_only";
+defparam toggle_counter_sig_16_.lut_mask="5a80";
+defparam toggle_counter_sig_16_.synch_mode="on";
+defparam toggle_counter_sig_16_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_15_ (
+ .regout(toggle_counter_sig_15),
+ .cout(toggle_counter_sig_cout[15]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_14),
+ .datab(toggle_counter_sig_15),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[13]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_15_.cin_used="true";
+defparam toggle_counter_sig_15_.operation_mode="arithmetic";
+defparam toggle_counter_sig_15_.output_mode="reg_only";
+defparam toggle_counter_sig_15_.lut_mask="6c80";
+defparam toggle_counter_sig_15_.synch_mode="on";
+defparam toggle_counter_sig_15_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_14_ (
+ .regout(toggle_counter_sig_14),
+ .cout(toggle_counter_sig_cout[14]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_14),
+ .datab(toggle_counter_sig_15),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[12]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_14_.cin_used="true";
+defparam toggle_counter_sig_14_.operation_mode="arithmetic";
+defparam toggle_counter_sig_14_.output_mode="reg_only";
+defparam toggle_counter_sig_14_.lut_mask="5a80";
+defparam toggle_counter_sig_14_.synch_mode="on";
+defparam toggle_counter_sig_14_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_13_ (
+ .regout(toggle_counter_sig_13),
+ .cout(toggle_counter_sig_cout[13]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_12),
+ .datab(toggle_counter_sig_13),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[11]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_13_.cin_used="true";
+defparam toggle_counter_sig_13_.operation_mode="arithmetic";
+defparam toggle_counter_sig_13_.output_mode="reg_only";
+defparam toggle_counter_sig_13_.lut_mask="6c80";
+defparam toggle_counter_sig_13_.synch_mode="on";
+defparam toggle_counter_sig_13_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_12_ (
+ .regout(toggle_counter_sig_12),
+ .cout(toggle_counter_sig_cout[12]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_12),
+ .datab(toggle_counter_sig_13),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[10]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_12_.cin_used="true";
+defparam toggle_counter_sig_12_.operation_mode="arithmetic";
+defparam toggle_counter_sig_12_.output_mode="reg_only";
+defparam toggle_counter_sig_12_.lut_mask="5a80";
+defparam toggle_counter_sig_12_.synch_mode="on";
+defparam toggle_counter_sig_12_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_11_ (
+ .regout(toggle_counter_sig_11),
+ .cout(toggle_counter_sig_cout[11]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_10),
+ .datab(toggle_counter_sig_11),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[9]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_11_.cin_used="true";
+defparam toggle_counter_sig_11_.operation_mode="arithmetic";
+defparam toggle_counter_sig_11_.output_mode="reg_only";
+defparam toggle_counter_sig_11_.lut_mask="6c80";
+defparam toggle_counter_sig_11_.synch_mode="on";
+defparam toggle_counter_sig_11_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_10_ (
+ .regout(toggle_counter_sig_10),
+ .cout(toggle_counter_sig_cout[10]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_10),
+ .datab(toggle_counter_sig_11),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[8]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_10_.cin_used="true";
+defparam toggle_counter_sig_10_.operation_mode="arithmetic";
+defparam toggle_counter_sig_10_.output_mode="reg_only";
+defparam toggle_counter_sig_10_.lut_mask="5a80";
+defparam toggle_counter_sig_10_.synch_mode="on";
+defparam toggle_counter_sig_10_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_9_ (
+ .regout(toggle_counter_sig_9),
+ .cout(toggle_counter_sig_cout[9]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_8),
+ .datab(toggle_counter_sig_9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[7]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_9_.cin_used="true";
+defparam toggle_counter_sig_9_.operation_mode="arithmetic";
+defparam toggle_counter_sig_9_.output_mode="reg_only";
+defparam toggle_counter_sig_9_.lut_mask="6c80";
+defparam toggle_counter_sig_9_.synch_mode="on";
+defparam toggle_counter_sig_9_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_8_ (
+ .regout(toggle_counter_sig_8),
+ .cout(toggle_counter_sig_cout[8]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_8),
+ .datab(toggle_counter_sig_9),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[6]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_8_.cin_used="true";
+defparam toggle_counter_sig_8_.operation_mode="arithmetic";
+defparam toggle_counter_sig_8_.output_mode="reg_only";
+defparam toggle_counter_sig_8_.lut_mask="5a80";
+defparam toggle_counter_sig_8_.synch_mode="on";
+defparam toggle_counter_sig_8_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_7_ (
+ .regout(toggle_counter_sig_7),
+ .cout(toggle_counter_sig_cout[7]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_6),
+ .datab(toggle_counter_sig_7),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[5]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_7_.cin_used="true";
+defparam toggle_counter_sig_7_.operation_mode="arithmetic";
+defparam toggle_counter_sig_7_.output_mode="reg_only";
+defparam toggle_counter_sig_7_.lut_mask="6c80";
+defparam toggle_counter_sig_7_.synch_mode="on";
+defparam toggle_counter_sig_7_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_6_ (
+ .regout(toggle_counter_sig_6),
+ .cout(toggle_counter_sig_cout[6]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_6),
+ .datab(toggle_counter_sig_7),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[4]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_6_.cin_used="true";
+defparam toggle_counter_sig_6_.operation_mode="arithmetic";
+defparam toggle_counter_sig_6_.output_mode="reg_only";
+defparam toggle_counter_sig_6_.lut_mask="5a80";
+defparam toggle_counter_sig_6_.synch_mode="on";
+defparam toggle_counter_sig_6_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_5_ (
+ .regout(toggle_counter_sig_5),
+ .cout(toggle_counter_sig_cout[5]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_4),
+ .datab(toggle_counter_sig_5),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[3]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_5_.cin_used="true";
+defparam toggle_counter_sig_5_.operation_mode="arithmetic";
+defparam toggle_counter_sig_5_.output_mode="reg_only";
+defparam toggle_counter_sig_5_.lut_mask="6c80";
+defparam toggle_counter_sig_5_.synch_mode="on";
+defparam toggle_counter_sig_5_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_4_ (
+ .regout(toggle_counter_sig_4),
+ .cout(toggle_counter_sig_cout[4]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_4),
+ .datab(toggle_counter_sig_5),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[2]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_4_.cin_used="true";
+defparam toggle_counter_sig_4_.operation_mode="arithmetic";
+defparam toggle_counter_sig_4_.output_mode="reg_only";
+defparam toggle_counter_sig_4_.lut_mask="5a80";
+defparam toggle_counter_sig_4_.synch_mode="on";
+defparam toggle_counter_sig_4_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_3_ (
+ .regout(toggle_counter_sig_3),
+ .cout(toggle_counter_sig_cout[3]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_2),
+ .datab(toggle_counter_sig_3),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(toggle_counter_sig_cout[1]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_3_.cin_used="true";
+defparam toggle_counter_sig_3_.operation_mode="arithmetic";
+defparam toggle_counter_sig_3_.output_mode="reg_only";
+defparam toggle_counter_sig_3_.lut_mask="6c80";
+defparam toggle_counter_sig_3_.synch_mode="on";
+defparam toggle_counter_sig_3_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_2_ (
+ .regout(toggle_counter_sig_2),
+ .cout(toggle_counter_sig_cout[2]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_2),
+ .datab(toggle_counter_sig_3),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .cin(un2_toggle_counter_next_cout[0]),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_2_.cin_used="true";
+defparam toggle_counter_sig_2_.operation_mode="arithmetic";
+defparam toggle_counter_sig_2_.output_mode="reg_only";
+defparam toggle_counter_sig_2_.lut_mask="5a80";
+defparam toggle_counter_sig_2_.synch_mode="on";
+defparam toggle_counter_sig_2_.sum_lutc_input="cin";
+// @12:99
+ stratix_lcell toggle_counter_sig_1_ (
+ .regout(toggle_counter_sig_1),
+ .cout(toggle_counter_sig_cout[1]),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_0),
+ .datab(toggle_counter_sig_1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_1_.operation_mode="arithmetic";
+defparam toggle_counter_sig_1_.output_mode="reg_only";
+defparam toggle_counter_sig_1_.lut_mask="6688";
+defparam toggle_counter_sig_1_.synch_mode="on";
+defparam toggle_counter_sig_1_.sum_lutc_input="datac";
+// @12:99
+ stratix_lcell toggle_counter_sig_0_ (
+ .regout(toggle_counter_sig_0),
+ .clk(clk_pin_c),
+ .dataa(toggle_counter_sig_0),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(toggle_sig_0_0_0_g1_i),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_counter_sig_0_.operation_mode="normal";
+defparam toggle_counter_sig_0_.output_mode="reg_only";
+defparam toggle_counter_sig_0_.lut_mask="5555";
+defparam toggle_counter_sig_0_.synch_mode="on";
+defparam toggle_counter_sig_0_.sum_lutc_input="datac";
+// @12:99
+ stratix_lcell toggle_sig_Z (
+ .regout(toggle_sig),
+ .clk(clk_pin_c),
+ .dataa(toggle_sig),
+ .datab(toggle_sig_0_0_0_g1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_sig_Z.operation_mode="normal";
+defparam toggle_sig_Z.output_mode="reg_only";
+defparam toggle_sig_Z.lut_mask="9999";
+defparam toggle_sig_Z.synch_mode="off";
+defparam toggle_sig_Z.sum_lutc_input="datac";
+// @12:60
+ stratix_lcell r_Z (
+ .regout(r),
+ .clk(clk_pin_c),
+ .dataa(toggle_sig),
+ .datab(v_enable_sig),
+ .datac(b_next_0_sqmuxa_7_4),
+ .datad(b_next_0_sqmuxa_7_5),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam r_Z.operation_mode="normal";
+defparam r_Z.output_mode="reg_only";
+defparam r_Z.lut_mask="8000";
+defparam r_Z.synch_mode="off";
+defparam r_Z.sum_lutc_input="datac";
+// @12:60
+ stratix_lcell b_Z (
+ .regout(b),
+ .clk(clk_pin_c),
+ .dataa(toggle_sig),
+ .datab(v_enable_sig),
+ .datac(b_next_0_sqmuxa_7_4),
+ .datad(b_next_0_sqmuxa_7_5),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam b_Z.operation_mode="normal";
+defparam b_Z.output_mode="reg_only";
+defparam b_Z.lut_mask="4000";
+defparam b_Z.synch_mode="off";
+defparam b_Z.sum_lutc_input="datac";
+// @12:60
+ stratix_lcell g_Z (
+ .regout(g),
+ .clk(clk_pin_c),
+ .dataa(VCC),
+ .datab(VCC),
+ .datac(VCC),
+ .datad(GND),
+ .aclr(un6_dly_counter_0_x),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam g_Z.operation_mode="normal";
+defparam g_Z.output_mode="reg_only";
+defparam g_Z.lut_mask="ff00";
+defparam g_Z.synch_mode="off";
+defparam g_Z.sum_lutc_input="datac";
+ stratix_lcell toggle_sig_0_0_0_g1_cZ (
+ .combout(toggle_sig_0_0_0_g1),
+ .clk(GND),
+ .dataa(toggle_counter_sig_19),
+ .datab(toggle_counter_sig_20),
+ .datac(toggle_sig_0_0_0_g1_2),
+ .datad(un1_toggle_counter_siglto18),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_sig_0_0_0_g1_cZ.operation_mode="normal";
+defparam toggle_sig_0_0_0_g1_cZ.output_mode="comb_only";
+defparam toggle_sig_0_0_0_g1_cZ.lut_mask="0703";
+defparam toggle_sig_0_0_0_g1_cZ.synch_mode="off";
+defparam toggle_sig_0_0_0_g1_cZ.sum_lutc_input="datac";
+// @12:111
+ stratix_lcell BLINKER_next_un1_toggle_counter_siglto18 (
+ .combout(un1_toggle_counter_siglto18),
+ .clk(GND),
+ .dataa(toggle_counter_sig_17),
+ .datab(toggle_counter_sig_18),
+ .datac(toggle_counter_sig_16),
+ .datad(un1_toggle_counter_siglto15),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglto18.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglto18.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglto18.lut_mask="7f77";
+defparam BLINKER_next_un1_toggle_counter_siglto18.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglto18.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell b_next_0_sqmuxa_7_5_cZ (
+ .combout(b_next_0_sqmuxa_7_5),
+ .clk(GND),
+ .dataa(column_counter_sig_6),
+ .datab(column_counter_sig_7),
+ .datac(un5_v_enablelto5),
+ .datad(b_next_0_sqmuxa_7_3),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_5_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_5_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_5_cZ.lut_mask="7f00";
+defparam b_next_0_sqmuxa_7_5_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_5_cZ.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell b_next_0_sqmuxa_7_4_cZ (
+ .combout(b_next_0_sqmuxa_7_4),
+ .clk(GND),
+ .dataa(line_counter_sig_8),
+ .datab(line_counter_sig_7),
+ .datac(un13_v_enablelto6),
+ .datad(b_next_0_sqmuxa_7_4_a),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_4_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_4_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_4_cZ.lut_mask="ef23";
+defparam b_next_0_sqmuxa_7_4_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_4_cZ.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell b_next_0_sqmuxa_7_4_a_cZ (
+ .combout(b_next_0_sqmuxa_7_4_a),
+ .clk(GND),
+ .dataa(line_counter_sig_4),
+ .datab(line_counter_sig_5),
+ .datac(line_counter_sig_6),
+ .datad(un17_v_enablelto3),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_4_a_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_4_a_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_4_a_cZ.lut_mask="0f1f";
+defparam b_next_0_sqmuxa_7_4_a_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_4_a_cZ.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell b_next_0_sqmuxa_7_3_cZ (
+ .combout(b_next_0_sqmuxa_7_3),
+ .clk(GND),
+ .dataa(column_counter_sig_7),
+ .datab(column_counter_sig_9),
+ .datac(b_next_0_sqmuxa_7_2),
+ .datad(un9_v_enablelto6),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_3_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_3_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_3_cZ.lut_mask="e0f0";
+defparam b_next_0_sqmuxa_7_3_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_3_cZ.sum_lutc_input="datac";
+// @12:111
+ stratix_lcell BLINKER_next_un1_toggle_counter_siglto15 (
+ .combout(un1_toggle_counter_siglto15),
+ .clk(GND),
+ .dataa(toggle_counter_sig_13),
+ .datab(toggle_counter_sig_14),
+ .datac(toggle_counter_sig_15),
+ .datad(un1_toggle_counter_siglto12),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglto15.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglto15.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglto15.lut_mask="ff7f";
+defparam BLINKER_next_un1_toggle_counter_siglto15.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglto15.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell DRAW_SQUARE_next_un5_v_enablelto5 (
+ .combout(un5_v_enablelto5),
+ .clk(GND),
+ .dataa(column_counter_sig_4),
+ .datab(column_counter_sig_5),
+ .datac(column_counter_sig_3),
+ .datad(un5_v_enablelt2),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un5_v_enablelto5.operation_mode="normal";
+defparam DRAW_SQUARE_next_un5_v_enablelto5.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un5_v_enablelto5.lut_mask="feee";
+defparam DRAW_SQUARE_next_un5_v_enablelto5.synch_mode="off";
+defparam DRAW_SQUARE_next_un5_v_enablelto5.sum_lutc_input="datac";
+// @12:111
+ stratix_lcell BLINKER_next_un1_toggle_counter_siglto12 (
+ .combout(un1_toggle_counter_siglto12),
+ .clk(GND),
+ .dataa(toggle_counter_sig_10),
+ .datab(toggle_counter_sig_11),
+ .datac(toggle_counter_sig_12),
+ .datad(un1_toggle_counter_siglto9),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglto12.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglto12.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglto12.lut_mask="0100";
+defparam BLINKER_next_un1_toggle_counter_siglto12.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglto12.sum_lutc_input="datac";
+// @12:76
+ stratix_lcell DRAW_SQUARE_next_un13_v_enablelto6 (
+ .combout(un13_v_enablelto6),
+ .clk(GND),
+ .dataa(line_counter_sig_5),
+ .datab(line_counter_sig_6),
+ .datac(line_counter_sig_3),
+ .datad(un13_v_enablelto4_0),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un13_v_enablelto6.operation_mode="normal";
+defparam DRAW_SQUARE_next_un13_v_enablelto6.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un13_v_enablelto6.lut_mask="7f77";
+defparam DRAW_SQUARE_next_un13_v_enablelto6.synch_mode="off";
+defparam DRAW_SQUARE_next_un13_v_enablelto6.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell DRAW_SQUARE_next_un9_v_enablelto6 (
+ .combout(un9_v_enablelto6),
+ .clk(GND),
+ .dataa(column_counter_sig_5),
+ .datab(column_counter_sig_6),
+ .datac(un9_v_enablelto4),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un9_v_enablelto6.operation_mode="normal";
+defparam DRAW_SQUARE_next_un9_v_enablelto6.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un9_v_enablelto6.lut_mask="f7f7";
+defparam DRAW_SQUARE_next_un9_v_enablelto6.synch_mode="off";
+defparam DRAW_SQUARE_next_un9_v_enablelto6.sum_lutc_input="datac";
+// @12:111
+ stratix_lcell BLINKER_next_un1_toggle_counter_siglto9 (
+ .combout(un1_toggle_counter_siglto9),
+ .clk(GND),
+ .dataa(toggle_counter_sig_8),
+ .datab(toggle_counter_sig_9),
+ .datac(toggle_counter_sig_7),
+ .datad(un1_toggle_counter_siglt6),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglto9.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglto9.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglto9.lut_mask="7f77";
+defparam BLINKER_next_un1_toggle_counter_siglto9.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglto9.sum_lutc_input="datac";
+// @12:76
+ stratix_lcell DRAW_SQUARE_next_un17_v_enablelto3 (
+ .combout(un17_v_enablelto3),
+ .clk(GND),
+ .dataa(line_counter_sig_1),
+ .datab(line_counter_sig_2),
+ .datac(line_counter_sig_0),
+ .datad(line_counter_sig_3),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un17_v_enablelto3.operation_mode="normal";
+defparam DRAW_SQUARE_next_un17_v_enablelto3.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un17_v_enablelto3.lut_mask="fe00";
+defparam DRAW_SQUARE_next_un17_v_enablelto3.synch_mode="off";
+defparam DRAW_SQUARE_next_un17_v_enablelto3.sum_lutc_input="datac";
+ stratix_lcell toggle_sig_0_0_0_g1_2_cZ (
+ .combout(toggle_sig_0_0_0_g1_2),
+ .clk(GND),
+ .dataa(toggle_counter_sig_23),
+ .datab(toggle_counter_sig_24),
+ .datac(toggle_counter_sig_21),
+ .datad(toggle_counter_sig_22),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam toggle_sig_0_0_0_g1_2_cZ.operation_mode="normal";
+defparam toggle_sig_0_0_0_g1_2_cZ.output_mode="comb_only";
+defparam toggle_sig_0_0_0_g1_2_cZ.lut_mask="fffe";
+defparam toggle_sig_0_0_0_g1_2_cZ.synch_mode="off";
+defparam toggle_sig_0_0_0_g1_2_cZ.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell b_next_0_sqmuxa_7_2_cZ (
+ .combout(b_next_0_sqmuxa_7_2),
+ .clk(GND),
+ .dataa(column_counter_sig_8),
+ .datab(h_enable_sig),
+ .datac(column_counter_sig_9),
+ .datad(line_counter_sig_8),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam b_next_0_sqmuxa_7_2_cZ.operation_mode="normal";
+defparam b_next_0_sqmuxa_7_2_cZ.output_mode="comb_only";
+defparam b_next_0_sqmuxa_7_2_cZ.lut_mask="0004";
+defparam b_next_0_sqmuxa_7_2_cZ.synch_mode="off";
+defparam b_next_0_sqmuxa_7_2_cZ.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell DRAW_SQUARE_next_un9_v_enablelto4 (
+ .combout(un9_v_enablelto4),
+ .clk(GND),
+ .dataa(column_counter_sig_3),
+ .datab(column_counter_sig_4),
+ .datac(column_counter_sig_2),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un9_v_enablelto4.operation_mode="normal";
+defparam DRAW_SQUARE_next_un9_v_enablelto4.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un9_v_enablelto4.lut_mask="0101";
+defparam DRAW_SQUARE_next_un9_v_enablelto4.synch_mode="off";
+defparam DRAW_SQUARE_next_un9_v_enablelto4.sum_lutc_input="datac";
+// @12:75
+ stratix_lcell DRAW_SQUARE_next_un5_v_enablelt2 (
+ .combout(un5_v_enablelt2),
+ .clk(GND),
+ .dataa(column_counter_sig_1),
+ .datab(column_counter_sig_2),
+ .datac(column_counter_sig_0),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un5_v_enablelt2.operation_mode="normal";
+defparam DRAW_SQUARE_next_un5_v_enablelt2.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un5_v_enablelt2.lut_mask="fefe";
+defparam DRAW_SQUARE_next_un5_v_enablelt2.synch_mode="off";
+defparam DRAW_SQUARE_next_un5_v_enablelt2.sum_lutc_input="datac";
+// @12:76
+ stratix_lcell DRAW_SQUARE_next_un13_v_enablelto4_0 (
+ .combout(un13_v_enablelto4_0),
+ .clk(GND),
+ .dataa(line_counter_sig_4),
+ .datab(line_counter_sig_2),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.operation_mode="normal";
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.output_mode="comb_only";
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.lut_mask="1111";
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.synch_mode="off";
+defparam DRAW_SQUARE_next_un13_v_enablelto4_0.sum_lutc_input="datac";
+// @12:111
+ stratix_lcell BLINKER_next_un1_toggle_counter_siglt6 (
+ .combout(un1_toggle_counter_siglt6),
+ .clk(GND),
+ .dataa(toggle_counter_sig_6),
+ .datab(toggle_counter_sig_5),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam BLINKER_next_un1_toggle_counter_siglt6.operation_mode="normal";
+defparam BLINKER_next_un1_toggle_counter_siglt6.output_mode="comb_only";
+defparam BLINKER_next_un1_toggle_counter_siglt6.lut_mask="7777";
+defparam BLINKER_next_un1_toggle_counter_siglt6.synch_mode="off";
+defparam BLINKER_next_un1_toggle_counter_siglt6.sum_lutc_input="datac";
+// @12:115
+ stratix_lcell un2_toggle_counter_next_0_ (
+ .cout(un2_toggle_counter_next_cout[0]),
+ .clk(GND),
+ .dataa(toggle_counter_sig_0),
+ .datab(toggle_counter_sig_1),
+ .datac(VCC),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam un2_toggle_counter_next_0_.operation_mode="arithmetic";
+defparam un2_toggle_counter_next_0_.output_mode="comb_only";
+defparam un2_toggle_counter_next_0_.lut_mask="5588";
+defparam un2_toggle_counter_next_0_.synch_mode="off";
+defparam un2_toggle_counter_next_0_.sum_lutc_input="datac";
+ assign toggle_sig_0_0_0_g1_i = ~ toggle_sig_0_0_0_g1;
+endmodule /* vga_control */
+
+// VQM4.1+
+module vga (
+ clk_pin,
+ reset_pin,
+ r0_pin,
+ r1_pin,
+ r2_pin,
+ g0_pin,
+ g1_pin,
+ g2_pin,
+ b0_pin,
+ b1_pin,
+ hsync_pin,
+ vsync_pin,
+ seven_seg_pin,
+ d_hsync,
+ d_vsync,
+ d_column_counter,
+ d_line_counter,
+ d_set_column_counter,
+ d_set_line_counter,
+ d_hsync_counter,
+ d_vsync_counter,
+ d_set_hsync_counter,
+ d_set_vsync_counter,
+ d_h_enable,
+ d_v_enable,
+ d_r,
+ d_g,
+ d_b,
+ d_hsync_state,
+ d_vsync_state,
+ d_state_clk,
+ d_toggle,
+ d_toggle_counter
+)
+;
+input clk_pin ;
+input reset_pin ;
+output r0_pin ;
+output r1_pin ;
+output r2_pin ;
+output g0_pin ;
+output g1_pin ;
+output g2_pin ;
+output b0_pin ;
+output b1_pin ;
+output hsync_pin ;
+output vsync_pin ;
+output [13:0] seven_seg_pin ;
+output d_hsync ;
+output d_vsync ;
+output [9:0] d_column_counter ;
+output [8:0] d_line_counter ;
+output d_set_column_counter ;
+output d_set_line_counter ;
+output [9:0] d_hsync_counter ;
+output [9:0] d_vsync_counter ;
+output d_set_hsync_counter ;
+output d_set_vsync_counter ;
+output d_h_enable ;
+output d_v_enable ;
+output d_r ;
+output d_g ;
+output d_b ;
+output [0:6] d_hsync_state ;
+output [0:6] d_vsync_state ;
+output d_state_clk ;
+output d_toggle ;
+output [24:0] d_toggle_counter ;
+wire clk_pin ;
+wire reset_pin ;
+wire r0_pin ;
+wire r1_pin ;
+wire r2_pin ;
+wire g0_pin ;
+wire g1_pin ;
+wire g2_pin ;
+wire b0_pin ;
+wire b1_pin ;
+wire hsync_pin ;
+wire vsync_pin ;
+wire d_hsync ;
+wire d_vsync ;
+wire d_set_column_counter ;
+wire d_set_line_counter ;
+wire d_set_hsync_counter ;
+wire d_set_vsync_counter ;
+wire d_h_enable ;
+wire d_v_enable ;
+wire d_r ;
+wire d_g ;
+wire d_b ;
+wire d_state_clk ;
+wire d_toggle ;
+wire [1:0] dly_counter;
+wire [9:0] vga_driver_unit_column_counter_sig;
+wire [8:0] vga_driver_unit_line_counter_sig;
+wire [9:0] vga_driver_unit_hsync_counter;
+wire [9:0] vga_driver_unit_vsync_counter;
+wire [6:0] vga_driver_unit_hsync_state;
+wire [6:0] vga_driver_unit_vsync_state;
+wire [24:0] vga_control_unit_toggle_counter_sig;
+wire VCC ;
+wire GND ;
+wire DELAY_RESET_next_un6_dly_counter_0_x ;
+wire vga_driver_unit_h_sync ;
+wire vga_driver_unit_v_sync ;
+wire vga_driver_unit_d_set_hsync_counter ;
+wire vga_driver_unit_d_set_vsync_counter ;
+wire vga_driver_unit_h_enable_sig ;
+wire vga_driver_unit_v_enable_sig ;
+wire vga_control_unit_r ;
+wire vga_control_unit_g ;
+wire vga_control_unit_b ;
+wire G_33 ;
+wire vga_control_unit_toggle_sig ;
+wire reset_pin_c ;
+//@1:1
+ assign VCC = 1'b1;
+//@1:1
+ assign GND = 1'b0;
+// @10:113
+ stratix_lcell dly_counter_1_ (
+ .regout(dly_counter[1]),
+ .clk(G_33),
+ .dataa(reset_pin_c),
+ .datab(dly_counter[0]),
+ .datac(dly_counter[1]),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam dly_counter_1_.operation_mode="normal";
+defparam dly_counter_1_.output_mode="reg_only";
+defparam dly_counter_1_.lut_mask="a8a8";
+defparam dly_counter_1_.synch_mode="off";
+defparam dly_counter_1_.sum_lutc_input="datac";
+// @10:113
+ stratix_lcell dly_counter_0_ (
+ .regout(dly_counter[0]),
+ .clk(G_33),
+ .dataa(reset_pin_c),
+ .datab(dly_counter[0]),
+ .datac(dly_counter[1]),
+ .datad(VCC),
+ .aclr(GND),
+ .sclr(GND),
+ .sload(GND),
+ .ena(VCC),
+ .inverta(GND),
+ .aload(GND),
+ .regcascin(GND)
+);
+defparam dly_counter_0_.operation_mode="normal";
+defparam dly_counter_0_.output_mode="reg_only";
+defparam dly_counter_0_.lut_mask="a2a2";
+defparam dly_counter_0_.synch_mode="off";
+defparam dly_counter_0_.sum_lutc_input="datac";
+// @6:42
+ stratix_io reset_pin_in (
+ .padio(reset_pin),
+ .combout(reset_pin_c),
+ .datain(GND),
+ .oe(GND),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam reset_pin_in.operation_mode = "input";
+// @6:41
+ stratix_io clk_pin_in (
+ .padio(clk_pin),
+ .combout(G_33),
+ .datain(GND),
+ .oe(GND),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam clk_pin_in.operation_mode = "input";
+// @6:66
+ stratix_io d_toggle_counter_out_24_ (
+ .padio(d_toggle_counter[24]),
+ .datain(vga_control_unit_toggle_counter_sig[24]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_24_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_23_ (
+ .padio(d_toggle_counter[23]),
+ .datain(vga_control_unit_toggle_counter_sig[23]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_23_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_22_ (
+ .padio(d_toggle_counter[22]),
+ .datain(vga_control_unit_toggle_counter_sig[22]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_22_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_21_ (
+ .padio(d_toggle_counter[21]),
+ .datain(vga_control_unit_toggle_counter_sig[21]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_21_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_20_ (
+ .padio(d_toggle_counter[20]),
+ .datain(vga_control_unit_toggle_counter_sig[20]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_20_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_19_ (
+ .padio(d_toggle_counter[19]),
+ .datain(vga_control_unit_toggle_counter_sig[19]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_19_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_18_ (
+ .padio(d_toggle_counter[18]),
+ .datain(vga_control_unit_toggle_counter_sig[18]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_18_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_17_ (
+ .padio(d_toggle_counter[17]),
+ .datain(vga_control_unit_toggle_counter_sig[17]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_17_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_16_ (
+ .padio(d_toggle_counter[16]),
+ .datain(vga_control_unit_toggle_counter_sig[16]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_16_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_15_ (
+ .padio(d_toggle_counter[15]),
+ .datain(vga_control_unit_toggle_counter_sig[15]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_15_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_14_ (
+ .padio(d_toggle_counter[14]),
+ .datain(vga_control_unit_toggle_counter_sig[14]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_14_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_13_ (
+ .padio(d_toggle_counter[13]),
+ .datain(vga_control_unit_toggle_counter_sig[13]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_13_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_12_ (
+ .padio(d_toggle_counter[12]),
+ .datain(vga_control_unit_toggle_counter_sig[12]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_12_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_11_ (
+ .padio(d_toggle_counter[11]),
+ .datain(vga_control_unit_toggle_counter_sig[11]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_11_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_10_ (
+ .padio(d_toggle_counter[10]),
+ .datain(vga_control_unit_toggle_counter_sig[10]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_10_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_9_ (
+ .padio(d_toggle_counter[9]),
+ .datain(vga_control_unit_toggle_counter_sig[9]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_9_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_8_ (
+ .padio(d_toggle_counter[8]),
+ .datain(vga_control_unit_toggle_counter_sig[8]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_8_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_7_ (
+ .padio(d_toggle_counter[7]),
+ .datain(vga_control_unit_toggle_counter_sig[7]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_7_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_6_ (
+ .padio(d_toggle_counter[6]),
+ .datain(vga_control_unit_toggle_counter_sig[6]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_6_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_5_ (
+ .padio(d_toggle_counter[5]),
+ .datain(vga_control_unit_toggle_counter_sig[5]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_5_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_4_ (
+ .padio(d_toggle_counter[4]),
+ .datain(vga_control_unit_toggle_counter_sig[4]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_4_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_3_ (
+ .padio(d_toggle_counter[3]),
+ .datain(vga_control_unit_toggle_counter_sig[3]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_3_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_2_ (
+ .padio(d_toggle_counter[2]),
+ .datain(vga_control_unit_toggle_counter_sig[2]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_2_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_1_ (
+ .padio(d_toggle_counter[1]),
+ .datain(vga_control_unit_toggle_counter_sig[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_1_.operation_mode = "output";
+// @6:66
+ stratix_io d_toggle_counter_out_0_ (
+ .padio(d_toggle_counter[0]),
+ .datain(vga_control_unit_toggle_counter_sig[0]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_counter_out_0_.operation_mode = "output";
+// @6:65
+ stratix_io d_toggle_out (
+ .padio(d_toggle),
+ .datain(vga_control_unit_toggle_sig),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_toggle_out.operation_mode = "output";
+// @6:64
+ stratix_io d_state_clk_out (
+ .padio(d_state_clk),
+ .datain(G_33),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_state_clk_out.operation_mode = "output";
+// @6:63
+ stratix_io d_vsync_state_out_0_ (
+ .padio(d_vsync_state[0]),
+ .datain(vga_driver_unit_vsync_state[0]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_state_out_0_.operation_mode = "output";
+// @6:63
+ stratix_io d_vsync_state_out_1_ (
+ .padio(d_vsync_state[1]),
+ .datain(vga_driver_unit_vsync_state[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_state_out_1_.operation_mode = "output";
+// @6:63
+ stratix_io d_vsync_state_out_2_ (
+ .padio(d_vsync_state[2]),
+ .datain(vga_driver_unit_vsync_state[2]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_state_out_2_.operation_mode = "output";
+// @6:63
+ stratix_io d_vsync_state_out_3_ (
+ .padio(d_vsync_state[3]),
+ .datain(vga_driver_unit_vsync_state[3]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_state_out_3_.operation_mode = "output";
+// @6:63
+ stratix_io d_vsync_state_out_4_ (
+ .padio(d_vsync_state[4]),
+ .datain(vga_driver_unit_vsync_state[4]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_state_out_4_.operation_mode = "output";
+// @6:63
+ stratix_io d_vsync_state_out_5_ (
+ .padio(d_vsync_state[5]),
+ .datain(vga_driver_unit_vsync_state[5]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_state_out_5_.operation_mode = "output";
+// @6:63
+ stratix_io d_vsync_state_out_6_ (
+ .padio(d_vsync_state[6]),
+ .datain(vga_driver_unit_vsync_state[6]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_state_out_6_.operation_mode = "output";
+// @6:62
+ stratix_io d_hsync_state_out_0_ (
+ .padio(d_hsync_state[0]),
+ .datain(vga_driver_unit_hsync_state[0]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_state_out_0_.operation_mode = "output";
+// @6:62
+ stratix_io d_hsync_state_out_1_ (
+ .padio(d_hsync_state[1]),
+ .datain(vga_driver_unit_hsync_state[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_state_out_1_.operation_mode = "output";
+// @6:62
+ stratix_io d_hsync_state_out_2_ (
+ .padio(d_hsync_state[2]),
+ .datain(vga_driver_unit_hsync_state[2]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_state_out_2_.operation_mode = "output";
+// @6:62
+ stratix_io d_hsync_state_out_3_ (
+ .padio(d_hsync_state[3]),
+ .datain(vga_driver_unit_hsync_state[3]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_state_out_3_.operation_mode = "output";
+// @6:62
+ stratix_io d_hsync_state_out_4_ (
+ .padio(d_hsync_state[4]),
+ .datain(vga_driver_unit_hsync_state[4]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_state_out_4_.operation_mode = "output";
+// @6:62
+ stratix_io d_hsync_state_out_5_ (
+ .padio(d_hsync_state[5]),
+ .datain(vga_driver_unit_hsync_state[5]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_state_out_5_.operation_mode = "output";
+// @6:62
+ stratix_io d_hsync_state_out_6_ (
+ .padio(d_hsync_state[6]),
+ .datain(vga_driver_unit_hsync_state[6]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_state_out_6_.operation_mode = "output";
+// @6:61
+ stratix_io d_b_out (
+ .padio(d_b),
+ .datain(vga_control_unit_b),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_b_out.operation_mode = "output";
+// @6:61
+ stratix_io d_g_out (
+ .padio(d_g),
+ .datain(vga_control_unit_g),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_g_out.operation_mode = "output";
+// @6:61
+ stratix_io d_r_out (
+ .padio(d_r),
+ .datain(vga_control_unit_r),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_r_out.operation_mode = "output";
+// @6:60
+ stratix_io d_v_enable_out (
+ .padio(d_v_enable),
+ .datain(vga_driver_unit_v_enable_sig),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_v_enable_out.operation_mode = "output";
+// @6:59
+ stratix_io d_h_enable_out (
+ .padio(d_h_enable),
+ .datain(vga_driver_unit_h_enable_sig),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_h_enable_out.operation_mode = "output";
+// @6:58
+ stratix_io d_set_vsync_counter_out (
+ .padio(d_set_vsync_counter),
+ .datain(vga_driver_unit_d_set_vsync_counter),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_set_vsync_counter_out.operation_mode = "output";
+// @6:58
+ stratix_io d_set_hsync_counter_out (
+ .padio(d_set_hsync_counter),
+ .datain(vga_driver_unit_d_set_hsync_counter),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_set_hsync_counter_out.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_9_ (
+ .padio(d_vsync_counter[9]),
+ .datain(vga_driver_unit_vsync_counter[9]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_9_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_8_ (
+ .padio(d_vsync_counter[8]),
+ .datain(vga_driver_unit_vsync_counter[8]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_8_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_7_ (
+ .padio(d_vsync_counter[7]),
+ .datain(vga_driver_unit_vsync_counter[7]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_7_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_6_ (
+ .padio(d_vsync_counter[6]),
+ .datain(vga_driver_unit_vsync_counter[6]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_6_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_5_ (
+ .padio(d_vsync_counter[5]),
+ .datain(vga_driver_unit_vsync_counter[5]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_5_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_4_ (
+ .padio(d_vsync_counter[4]),
+ .datain(vga_driver_unit_vsync_counter[4]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_4_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_3_ (
+ .padio(d_vsync_counter[3]),
+ .datain(vga_driver_unit_vsync_counter[3]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_3_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_2_ (
+ .padio(d_vsync_counter[2]),
+ .datain(vga_driver_unit_vsync_counter[2]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_2_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_1_ (
+ .padio(d_vsync_counter[1]),
+ .datain(vga_driver_unit_vsync_counter[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_1_.operation_mode = "output";
+// @6:57
+ stratix_io d_vsync_counter_out_0_ (
+ .padio(d_vsync_counter[0]),
+ .datain(vga_driver_unit_vsync_counter[0]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_counter_out_0_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_9_ (
+ .padio(d_hsync_counter[9]),
+ .datain(vga_driver_unit_hsync_counter[9]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_9_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_8_ (
+ .padio(d_hsync_counter[8]),
+ .datain(vga_driver_unit_hsync_counter[8]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_8_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_7_ (
+ .padio(d_hsync_counter[7]),
+ .datain(vga_driver_unit_hsync_counter[7]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_7_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_6_ (
+ .padio(d_hsync_counter[6]),
+ .datain(vga_driver_unit_hsync_counter[6]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_6_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_5_ (
+ .padio(d_hsync_counter[5]),
+ .datain(vga_driver_unit_hsync_counter[5]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_5_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_4_ (
+ .padio(d_hsync_counter[4]),
+ .datain(vga_driver_unit_hsync_counter[4]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_4_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_3_ (
+ .padio(d_hsync_counter[3]),
+ .datain(vga_driver_unit_hsync_counter[3]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_3_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_2_ (
+ .padio(d_hsync_counter[2]),
+ .datain(vga_driver_unit_hsync_counter[2]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_2_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_1_ (
+ .padio(d_hsync_counter[1]),
+ .datain(vga_driver_unit_hsync_counter[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_1_.operation_mode = "output";
+// @6:56
+ stratix_io d_hsync_counter_out_0_ (
+ .padio(d_hsync_counter[0]),
+ .datain(vga_driver_unit_hsync_counter[0]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_counter_out_0_.operation_mode = "output";
+// @6:55
+ stratix_io d_set_line_counter_out (
+ .padio(d_set_line_counter),
+ .datain(vga_driver_unit_vsync_state[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_set_line_counter_out.operation_mode = "output";
+// @6:55
+ stratix_io d_set_column_counter_out (
+ .padio(d_set_column_counter),
+ .datain(vga_driver_unit_hsync_state[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_set_column_counter_out.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_8_ (
+ .padio(d_line_counter[8]),
+ .datain(vga_driver_unit_line_counter_sig[8]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_8_.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_7_ (
+ .padio(d_line_counter[7]),
+ .datain(vga_driver_unit_line_counter_sig[7]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_7_.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_6_ (
+ .padio(d_line_counter[6]),
+ .datain(vga_driver_unit_line_counter_sig[6]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_6_.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_5_ (
+ .padio(d_line_counter[5]),
+ .datain(vga_driver_unit_line_counter_sig[5]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_5_.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_4_ (
+ .padio(d_line_counter[4]),
+ .datain(vga_driver_unit_line_counter_sig[4]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_4_.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_3_ (
+ .padio(d_line_counter[3]),
+ .datain(vga_driver_unit_line_counter_sig[3]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_3_.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_2_ (
+ .padio(d_line_counter[2]),
+ .datain(vga_driver_unit_line_counter_sig[2]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_2_.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_1_ (
+ .padio(d_line_counter[1]),
+ .datain(vga_driver_unit_line_counter_sig[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_1_.operation_mode = "output";
+// @6:54
+ stratix_io d_line_counter_out_0_ (
+ .padio(d_line_counter[0]),
+ .datain(vga_driver_unit_line_counter_sig[0]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_line_counter_out_0_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_9_ (
+ .padio(d_column_counter[9]),
+ .datain(vga_driver_unit_column_counter_sig[9]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_9_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_8_ (
+ .padio(d_column_counter[8]),
+ .datain(vga_driver_unit_column_counter_sig[8]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_8_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_7_ (
+ .padio(d_column_counter[7]),
+ .datain(vga_driver_unit_column_counter_sig[7]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_7_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_6_ (
+ .padio(d_column_counter[6]),
+ .datain(vga_driver_unit_column_counter_sig[6]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_6_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_5_ (
+ .padio(d_column_counter[5]),
+ .datain(vga_driver_unit_column_counter_sig[5]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_5_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_4_ (
+ .padio(d_column_counter[4]),
+ .datain(vga_driver_unit_column_counter_sig[4]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_4_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_3_ (
+ .padio(d_column_counter[3]),
+ .datain(vga_driver_unit_column_counter_sig[3]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_3_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_2_ (
+ .padio(d_column_counter[2]),
+ .datain(vga_driver_unit_column_counter_sig[2]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_2_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_1_ (
+ .padio(d_column_counter[1]),
+ .datain(vga_driver_unit_column_counter_sig[1]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_1_.operation_mode = "output";
+// @6:53
+ stratix_io d_column_counter_out_0_ (
+ .padio(d_column_counter[0]),
+ .datain(vga_driver_unit_column_counter_sig[0]),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_column_counter_out_0_.operation_mode = "output";
+// @6:52
+ stratix_io d_vsync_out (
+ .padio(d_vsync),
+ .datain(vga_driver_unit_v_sync),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_vsync_out.operation_mode = "output";
+// @6:52
+ stratix_io d_hsync_out (
+ .padio(d_hsync),
+ .datain(vga_driver_unit_h_sync),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam d_hsync_out.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_tri_13_ (
+ .padio(seven_seg_pin[13]),
+ .datain(VCC),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_tri_13_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_out_12_ (
+ .padio(seven_seg_pin[12]),
+ .datain(DELAY_RESET_next_un6_dly_counter_0_x),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_out_12_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_out_11_ (
+ .padio(seven_seg_pin[11]),
+ .datain(DELAY_RESET_next_un6_dly_counter_0_x),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_out_11_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_out_10_ (
+ .padio(seven_seg_pin[10]),
+ .datain(DELAY_RESET_next_un6_dly_counter_0_x),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_out_10_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_out_9_ (
+ .padio(seven_seg_pin[9]),
+ .datain(DELAY_RESET_next_un6_dly_counter_0_x),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_out_9_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_out_8_ (
+ .padio(seven_seg_pin[8]),
+ .datain(DELAY_RESET_next_un6_dly_counter_0_x),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_out_8_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_out_7_ (
+ .padio(seven_seg_pin[7]),
+ .datain(DELAY_RESET_next_un6_dly_counter_0_x),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_out_7_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_tri_6_ (
+ .padio(seven_seg_pin[6]),
+ .datain(VCC),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_tri_6_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_tri_5_ (
+ .padio(seven_seg_pin[5]),
+ .datain(VCC),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_tri_5_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_tri_4_ (
+ .padio(seven_seg_pin[4]),
+ .datain(VCC),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_tri_4_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_tri_3_ (
+ .padio(seven_seg_pin[3]),
+ .datain(VCC),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_tri_3_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_out_2_ (
+ .padio(seven_seg_pin[2]),
+ .datain(DELAY_RESET_next_un6_dly_counter_0_x),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_out_2_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_out_1_ (
+ .padio(seven_seg_pin[1]),
+ .datain(DELAY_RESET_next_un6_dly_counter_0_x),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_out_1_.operation_mode = "output";
+// @6:50
+ stratix_io seven_seg_pin_tri_0_ (
+ .padio(seven_seg_pin[0]),
+ .datain(VCC),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam seven_seg_pin_tri_0_.operation_mode = "output";
+// @6:48
+ stratix_io vsync_pin_out (
+ .padio(vsync_pin),
+ .datain(vga_driver_unit_v_sync),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam vsync_pin_out.operation_mode = "output";
+// @6:47
+ stratix_io hsync_pin_out (
+ .padio(hsync_pin),
+ .datain(vga_driver_unit_h_sync),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam hsync_pin_out.operation_mode = "output";
+// @6:46
+ stratix_io b1_pin_out (
+ .padio(b1_pin),
+ .datain(vga_control_unit_b),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam b1_pin_out.operation_mode = "output";
+// @6:46
+ stratix_io b0_pin_out (
+ .padio(b0_pin),
+ .datain(vga_control_unit_b),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam b0_pin_out.operation_mode = "output";
+// @6:45
+ stratix_io g2_pin_out (
+ .padio(g2_pin),
+ .datain(vga_control_unit_g),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam g2_pin_out.operation_mode = "output";
+// @6:45
+ stratix_io g1_pin_out (
+ .padio(g1_pin),
+ .datain(vga_control_unit_g),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam g1_pin_out.operation_mode = "output";
+// @6:45
+ stratix_io g0_pin_out (
+ .padio(g0_pin),
+ .datain(vga_control_unit_g),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam g0_pin_out.operation_mode = "output";
+// @6:44
+ stratix_io r2_pin_out (
+ .padio(r2_pin),
+ .datain(vga_control_unit_r),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam r2_pin_out.operation_mode = "output";
+// @6:44
+ stratix_io r1_pin_out (
+ .padio(r1_pin),
+ .datain(vga_control_unit_r),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam r1_pin_out.operation_mode = "output";
+// @6:44
+ stratix_io r0_pin_out (
+ .padio(r0_pin),
+ .datain(vga_control_unit_r),
+ .oe(VCC),
+ .outclk(GND),
+ .outclkena(VCC),
+ .inclk(GND),
+ .inclkena(VCC),
+ .areset(GND),
+ .sreset(GND)
+);
+defparam r0_pin_out.operation_mode = "output";
+//@6:41
+// @10:161
+ vga_driver vga_driver_unit (
+ .line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
+ .line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
+ .line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
+ .line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
+ .line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
+ .line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
+ .line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
+ .line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
+ .line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
+ .dly_counter_1(dly_counter[1]),
+ .dly_counter_0(dly_counter[0]),
+ .vsync_state_2(vga_driver_unit_vsync_state[2]),
+ .vsync_state_5(vga_driver_unit_vsync_state[5]),
+ .vsync_state_3(vga_driver_unit_vsync_state[3]),
+ .vsync_state_6(vga_driver_unit_vsync_state[6]),
+ .vsync_state_4(vga_driver_unit_vsync_state[4]),
+ .vsync_state_1(vga_driver_unit_vsync_state[1]),
+ .vsync_state_0(vga_driver_unit_vsync_state[0]),
+ .hsync_state_2(vga_driver_unit_hsync_state[2]),
+ .hsync_state_4(vga_driver_unit_hsync_state[4]),
+ .hsync_state_0(vga_driver_unit_hsync_state[0]),
+ .hsync_state_5(vga_driver_unit_hsync_state[5]),
+ .hsync_state_1(vga_driver_unit_hsync_state[1]),
+ .hsync_state_3(vga_driver_unit_hsync_state[3]),
+ .hsync_state_6(vga_driver_unit_hsync_state[6]),
+ .column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
+ .column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
+ .column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
+ .column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
+ .column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
+ .column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
+ .column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
+ .column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
+ .column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
+ .column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
+ .vsync_counter_9(vga_driver_unit_vsync_counter[9]),
+ .vsync_counter_8(vga_driver_unit_vsync_counter[8]),
+ .vsync_counter_7(vga_driver_unit_vsync_counter[7]),
+ .vsync_counter_6(vga_driver_unit_vsync_counter[6]),
+ .vsync_counter_5(vga_driver_unit_vsync_counter[5]),
+ .vsync_counter_4(vga_driver_unit_vsync_counter[4]),
+ .vsync_counter_3(vga_driver_unit_vsync_counter[3]),
+ .vsync_counter_2(vga_driver_unit_vsync_counter[2]),
+ .vsync_counter_1(vga_driver_unit_vsync_counter[1]),
+ .vsync_counter_0(vga_driver_unit_vsync_counter[0]),
+ .hsync_counter_9(vga_driver_unit_hsync_counter[9]),
+ .hsync_counter_8(vga_driver_unit_hsync_counter[8]),
+ .hsync_counter_7(vga_driver_unit_hsync_counter[7]),
+ .hsync_counter_6(vga_driver_unit_hsync_counter[6]),
+ .hsync_counter_5(vga_driver_unit_hsync_counter[5]),
+ .hsync_counter_4(vga_driver_unit_hsync_counter[4]),
+ .hsync_counter_3(vga_driver_unit_hsync_counter[3]),
+ .hsync_counter_2(vga_driver_unit_hsync_counter[2]),
+ .hsync_counter_1(vga_driver_unit_hsync_counter[1]),
+ .hsync_counter_0(vga_driver_unit_hsync_counter[0]),
+ .d_set_vsync_counter(vga_driver_unit_d_set_vsync_counter),
+ .v_sync(vga_driver_unit_v_sync),
+ .h_sync(vga_driver_unit_h_sync),
+ .h_enable_sig(vga_driver_unit_h_enable_sig),
+ .v_enable_sig(vga_driver_unit_v_enable_sig),
+ .reset_pin_c(reset_pin_c),
+ .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
+ .d_set_hsync_counter(vga_driver_unit_d_set_hsync_counter),
+ .clk_pin_c(G_33)
+);
+// @10:186
+ vga_control vga_control_unit (
+ .line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
+ .line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
+ .line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
+ .line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
+ .line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
+ .line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
+ .line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
+ .line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
+ .line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
+ .column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
+ .column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
+ .column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
+ .column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
+ .column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
+ .column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
+ .column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
+ .column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
+ .column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
+ .column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
+ .toggle_counter_sig_0(vga_control_unit_toggle_counter_sig[0]),
+ .toggle_counter_sig_1(vga_control_unit_toggle_counter_sig[1]),
+ .toggle_counter_sig_2(vga_control_unit_toggle_counter_sig[2]),
+ .toggle_counter_sig_3(vga_control_unit_toggle_counter_sig[3]),
+ .toggle_counter_sig_4(vga_control_unit_toggle_counter_sig[4]),
+ .toggle_counter_sig_5(vga_control_unit_toggle_counter_sig[5]),
+ .toggle_counter_sig_6(vga_control_unit_toggle_counter_sig[6]),
+ .toggle_counter_sig_7(vga_control_unit_toggle_counter_sig[7]),
+ .toggle_counter_sig_8(vga_control_unit_toggle_counter_sig[8]),
+ .toggle_counter_sig_9(vga_control_unit_toggle_counter_sig[9]),
+ .toggle_counter_sig_10(vga_control_unit_toggle_counter_sig[10]),
+ .toggle_counter_sig_11(vga_control_unit_toggle_counter_sig[11]),
+ .toggle_counter_sig_12(vga_control_unit_toggle_counter_sig[12]),
+ .toggle_counter_sig_13(vga_control_unit_toggle_counter_sig[13]),
+ .toggle_counter_sig_14(vga_control_unit_toggle_counter_sig[14]),
+ .toggle_counter_sig_15(vga_control_unit_toggle_counter_sig[15]),
+ .toggle_counter_sig_16(vga_control_unit_toggle_counter_sig[16]),
+ .toggle_counter_sig_17(vga_control_unit_toggle_counter_sig[17]),
+ .toggle_counter_sig_18(vga_control_unit_toggle_counter_sig[18]),
+ .toggle_counter_sig_19(vga_control_unit_toggle_counter_sig[19]),
+ .toggle_counter_sig_20(vga_control_unit_toggle_counter_sig[20]),
+ .toggle_counter_sig_21(vga_control_unit_toggle_counter_sig[21]),
+ .toggle_counter_sig_22(vga_control_unit_toggle_counter_sig[22]),
+ .toggle_counter_sig_23(vga_control_unit_toggle_counter_sig[23]),
+ .toggle_counter_sig_24(vga_control_unit_toggle_counter_sig[24]),
+ .h_enable_sig(vga_driver_unit_h_enable_sig),
+ .g(vga_control_unit_g),
+ .b(vga_control_unit_b),
+ .v_enable_sig(vga_driver_unit_v_enable_sig),
+ .r(vga_control_unit_r),
+ .toggle_sig(vga_control_unit_toggle_sig),
+ .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
+ .clk_pin_c(G_33)
+);
+endmodule /* vga */
+
--- /dev/null
+vendor_name = Synplicity
+source_file = 0, noname, synplify
+source_file = 1, /opt/synplify/fpga_c200906/lib/vhd/std.vhd, synplify
+source_file = 2, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_pak.vhd, synplify
+source_file = 3, /opt/synplify/fpga_c200906/lib/vhd/std1164.vhd, synplify
+source_file = 4, /opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd, synplify
+source_file = 5, /opt/synplify/fpga_c200906/lib/vhd/arith.vhd, synplify
+source_file = 6, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_ent.vhd, synplify
+source_file = 7, /homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_ent.vhd, synplify
+source_file = 8, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_ent.vhd, synplify
+source_file = 9, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_ent.vhd, synplify
+source_file = 10, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_arc.vhd, synplify
+source_file = 11, /homes/burban/didelu/dide_16/bsp2/Designflow/src/board_driver_arc.vhd, synplify
+source_file = 12, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_control_arc.vhd, synplify
+source_file = 13, /homes/burban/didelu/dide_16/bsp2/Designflow/src/vga_driver_arc.vhd, synplify
+design_name=vga
+instance = port, clk_pin, , vga, 6, 41:7:41:13
+instance = port, reset_pin, , vga, 6, 42:7:42:15
+instance = port, r0_pin, , vga, 6, 44:7:44:12
+instance = port, r1_pin, , vga, 6, 44:15:44:20
+instance = port, r2_pin, , vga, 6, 44:23:44:28
+instance = port, g0_pin, , vga, 6, 45:7:45:12
+instance = port, g1_pin, , vga, 6, 45:15:45:20
+instance = port, g2_pin, , vga, 6, 45:23:45:28
+instance = port, b0_pin, , vga, 6, 46:7:46:12
+instance = port, b1_pin, , vga, 6, 46:15:46:20
+instance = port, hsync_pin, , vga, 6, 47:7:47:15
+instance = port, vsync_pin, , vga, 6, 48:7:48:15
+instance = port, seven_seg_pin[13:0], , vga, 6, 50:7:50:19
+instance = port, d_hsync, , vga, 6, 52:7:52:13
+instance = port, d_vsync, , vga, 6, 52:16:52:22
+instance = port, d_column_counter[9:0], , vga, 6, 53:7:53:22
+instance = port, d_line_counter[8:0], , vga, 6, 54:7:54:20
+instance = port, d_set_column_counter, , vga, 6, 55:7:55:26
+instance = port, d_set_line_counter, , vga, 6, 55:29:55:46
+instance = port, d_hsync_counter[9:0], , vga, 6, 56:7:56:21
+instance = port, d_vsync_counter[9:0], , vga, 6, 57:7:57:21
+instance = port, d_set_hsync_counter, , vga, 6, 58:7:58:25
+instance = port, d_set_vsync_counter, , vga, 6, 58:28:58:46
+instance = port, d_h_enable, , vga, 6, 59:7:59:16
+instance = port, d_v_enable, , vga, 6, 60:7:60:16
+instance = port, d_r, , vga, 6, 61:7:61:9
+instance = port, d_g, , vga, 6, 61:12:61:14
+instance = port, d_b, , vga, 6, 61:17:61:19
+instance = port, d_hsync_state[0:6], , vga, 6, 62:7:62:19
+instance = port, d_vsync_state[0:6], , vga, 6, 63:7:63:19
+instance = port, d_state_clk, , vga, 6, 64:7:64:17
+instance = port, d_toggle, , vga, 6, 65:7:65:14
+instance = port, d_toggle_counter[24:0], , vga, 6, 66:7:66:22
+instance = comp, dly_counter_1_, , vga, 10, 113:4:113:5
+instance = comp, dly_counter_0_, , vga, 10, 113:4:113:5
+instance = comp, reset_pin_in, , vga, 6, 42:7:42:15
+instance = comp, clk_pin_in, , vga, 6, 41:7:41:13
+instance = comp, d_toggle_counter_out_24_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_23_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_22_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_21_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_20_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_19_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_18_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_17_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_16_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_15_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_14_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_13_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_12_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_11_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_10_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_9_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_8_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_7_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_6_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_5_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_4_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_3_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_2_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_1_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_counter_out_0_, , vga, 6, 66:7:66:22
+instance = comp, d_toggle_out, , vga, 6, 65:7:65:14
+instance = comp, d_state_clk_out, , vga, 6, 64:7:64:17
+instance = comp, d_vsync_state_out_0_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_1_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_2_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_3_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_4_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_5_, , vga, 6, 63:7:63:19
+instance = comp, d_vsync_state_out_6_, , vga, 6, 63:7:63:19
+instance = comp, d_hsync_state_out_0_, , vga, 6, 62:7:62:19
+instance = comp, d_hsync_state_out_1_, , vga, 6, 62:7:62:19
+instance = comp, d_hsync_state_out_2_, , vga, 6, 62:7:62:19
+instance = comp, d_hsync_state_out_3_, , vga, 6, 62:7:62:19
+instance = comp, d_hsync_state_out_4_, , vga, 6, 62:7:62:19
+instance = comp, d_hsync_state_out_5_, , vga, 6, 62:7:62:19
+instance = comp, d_hsync_state_out_6_, , vga, 6, 62:7:62:19
+instance = comp, d_b_out, , vga, 6, 61:17:61:19
+instance = comp, d_g_out, , vga, 6, 61:12:61:14
+instance = comp, d_r_out, , vga, 6, 61:7:61:9
+instance = comp, d_v_enable_out, , vga, 6, 60:7:60:16
+instance = comp, d_h_enable_out, , vga, 6, 59:7:59:16
+instance = comp, d_set_vsync_counter_out, , vga, 6, 58:28:58:46
+instance = comp, d_set_hsync_counter_out, , vga, 6, 58:7:58:25
+instance = comp, d_vsync_counter_out_9_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_8_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_7_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_6_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_5_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_4_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_3_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_2_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_1_, , vga, 6, 57:7:57:21
+instance = comp, d_vsync_counter_out_0_, , vga, 6, 57:7:57:21
+instance = comp, d_hsync_counter_out_9_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_8_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_7_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_6_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_5_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_4_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_3_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_2_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_1_, , vga, 6, 56:7:56:21
+instance = comp, d_hsync_counter_out_0_, , vga, 6, 56:7:56:21
+instance = comp, d_set_line_counter_out, , vga, 6, 55:29:55:46
+instance = comp, d_set_column_counter_out, , vga, 6, 55:7:55:26
+instance = comp, d_line_counter_out_8_, , vga, 6, 54:7:54:20
+instance = comp, d_line_counter_out_7_, , vga, 6, 54:7:54:20
+instance = comp, d_line_counter_out_6_, , vga, 6, 54:7:54:20
+instance = comp, d_line_counter_out_5_, , vga, 6, 54:7:54:20
+instance = comp, d_line_counter_out_4_, , vga, 6, 54:7:54:20
+instance = comp, d_line_counter_out_3_, , vga, 6, 54:7:54:20
+instance = comp, d_line_counter_out_2_, , vga, 6, 54:7:54:20
+instance = comp, d_line_counter_out_1_, , vga, 6, 54:7:54:20
+instance = comp, d_line_counter_out_0_, , vga, 6, 54:7:54:20
+instance = comp, d_column_counter_out_9_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_8_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_7_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_6_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_5_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_4_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_3_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_2_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_1_, , vga, 6, 53:7:53:22
+instance = comp, d_column_counter_out_0_, , vga, 6, 53:7:53:22
+instance = comp, d_vsync_out, , vga, 6, 52:16:52:22
+instance = comp, d_hsync_out, , vga, 6, 52:7:52:13
+instance = comp, seven_seg_pin_tri_13_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_out_12_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_out_11_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_out_10_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_out_9_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_out_8_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_out_7_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_tri_6_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_tri_5_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_tri_4_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_tri_3_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_out_2_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_out_1_, , vga, 6, 50:7:50:19
+instance = comp, seven_seg_pin_tri_0_, , vga, 6, 50:7:50:19
+instance = comp, vsync_pin_out, , vga, 6, 48:7:48:15
+instance = comp, hsync_pin_out, , vga, 6, 47:7:47:15
+instance = comp, b1_pin_out, , vga, 6, 46:15:46:20
+instance = comp, b0_pin_out, , vga, 6, 46:7:46:12
+instance = comp, g2_pin_out, , vga, 6, 45:23:45:28
+instance = comp, g1_pin_out, , vga, 6, 45:15:45:20
+instance = comp, g0_pin_out, , vga, 6, 45:7:45:12
+instance = comp, r2_pin_out, , vga, 6, 44:23:44:28
+instance = comp, r1_pin_out, , vga, 6, 44:15:44:20
+instance = comp, r0_pin_out, , vga, 6, 44:7:44:12
+instance = comp, vga_driver_unit, , vga, 10, 161:0:161:14
+instance = comp, vga_control_unit, , vga, 10, 186:2:186:17
+design_name=vga_control
+instance = comp, toggle_counter_sig_24_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_23_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_22_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_21_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_20_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_19_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_18_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_17_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_16_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_15_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_14_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_13_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_12_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_11_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_10_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_9_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_8_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_7_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_6_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_5_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_4_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_3_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_2_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_1_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_counter_sig_0_, , vga_control, 12, 99:4:99:5
+instance = comp, toggle_sig_Z, , vga_control, 12, 99:4:99:5
+instance = comp, r_Z, , vga_control, 12, 60:4:60:5
+instance = comp, b_Z, , vga_control, 12, 60:4:60:5
+instance = comp, g_Z, , vga_control, 12, 60:4:60:5
+instance = comp, BLINKER_next_un1_toggle_counter_siglto18, , vga_control, 12, 111:7:111:38
+instance = comp, b_next_0_sqmuxa_7_5_cZ, , vga_control, 12, 75:10:76:60
+instance = comp, b_next_0_sqmuxa_7_4_cZ, , vga_control, 12, 75:10:76:60
+instance = comp, b_next_0_sqmuxa_7_4_a_cZ, , vga_control, 12, 75:10:76:60
+instance = comp, b_next_0_sqmuxa_7_3_cZ, , vga_control, 12, 75:10:76:60
+instance = comp, BLINKER_next_un1_toggle_counter_siglto15, , vga_control, 12, 111:7:111:38
+instance = comp, DRAW_SQUARE_next_un5_v_enablelto5, , vga_control, 12, 75:38:75:60
+instance = comp, BLINKER_next_un1_toggle_counter_siglto12, , vga_control, 12, 111:7:111:38
+instance = comp, DRAW_SQUARE_next_un13_v_enablelto6, , vga_control, 12, 76:10:76:32
+instance = comp, DRAW_SQUARE_next_un9_v_enablelto6, , vga_control, 12, 75:10:75:32
+instance = comp, BLINKER_next_un1_toggle_counter_siglto9, , vga_control, 12, 111:7:111:38
+instance = comp, DRAW_SQUARE_next_un17_v_enablelto3, , vga_control, 12, 76:38:76:60
+instance = comp, b_next_0_sqmuxa_7_2_cZ, , vga_control, 12, 75:10:76:60
+instance = comp, DRAW_SQUARE_next_un9_v_enablelto4, , vga_control, 12, 75:10:75:32
+instance = comp, DRAW_SQUARE_next_un5_v_enablelt2, , vga_control, 12, 75:38:75:60
+instance = comp, DRAW_SQUARE_next_un13_v_enablelto4_0, , vga_control, 12, 76:10:76:32
+instance = comp, BLINKER_next_un1_toggle_counter_siglt6, , vga_control, 12, 111:7:111:38
+instance = comp, un2_toggle_counter_next_0_, , vga_control, 12, 115:29:115:52
+design_name=vga_driver
+instance = comp, hsync_counter_0_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_1_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_2_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_3_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_4_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_5_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_6_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_7_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_8_, , vga_driver, 13, 158:4:158:5
+instance = comp, hsync_counter_9_, , vga_driver, 13, 158:4:158:5
+instance = comp, vsync_counter_0_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_1_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_2_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_3_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_4_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_5_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_6_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_7_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_8_, , vga_driver, 13, 267:4:267:5
+instance = comp, vsync_counter_9_, , vga_driver, 13, 267:4:267:5
+instance = comp, column_counter_sig_9_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_8_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_7_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_6_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_5_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_4_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_3_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_2_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_1_, , vga_driver, 13, 97:4:97:5
+instance = comp, column_counter_sig_0_, , vga_driver, 13, 97:4:97:5
+instance = comp, hsync_state_6_, , vga_driver, 13, 187:4:187:5
+instance = comp, vsync_state_0_, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_1_, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_6_, , vga_driver, 13, 300:4:300:5
+instance = comp, line_counter_sig_8_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_7_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_6_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_5_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_4_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_3_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_2_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_1_, , vga_driver, 13, 125:4:125:5
+instance = comp, line_counter_sig_0_, , vga_driver, 13, 125:4:125:5
+instance = comp, v_enable_sig_Z, , vga_driver, 13, 187:4:187:5
+instance = comp, h_enable_sig_Z, , vga_driver, 13, 300:4:300:5
+instance = comp, h_sync_Z, , vga_driver, 13, 187:4:187:5
+instance = comp, v_sync_Z, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_5_, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_4_, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_3_, , vga_driver, 13, 300:4:300:5
+instance = comp, vsync_state_2_, , vga_driver, 13, 300:4:300:5
+instance = comp, hsync_state_5_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_4_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_3_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_2_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_1_, , vga_driver, 13, 187:4:187:5
+instance = comp, hsync_state_0_, , vga_driver, 13, 187:4:187:5
+instance = comp, vsync_state_next_2_sqmuxa_cZ, , vga_driver, 13, 97:4:97:5
+instance = comp, un1_hsync_state_next_1_sqmuxa_0_cZ, , vga_driver, 13, 206:4:206:7
+instance = comp, un1_vsync_state_next_1_sqmuxa_0_cZ, , vga_driver, 13, 319:4:319:7
+instance = comp, LINE_COUNT_next_un10_line_counter_siglto8, , vga_driver, 13, 139:9:139:40
+instance = comp, G_2, , vga_driver, 10, 161:0:161:14
+instance = comp, vsync_state_next_1_sqmuxa_1_cZ, , vga_driver, 13, 326:11:326:32
+instance = comp, vsync_state_next_1_sqmuxa_2_cZ, , vga_driver, 13, 331:11:331:33
+instance = comp, vsync_state_next_1_sqmuxa_3_cZ, , vga_driver, 13, 339:11:339:34
+instance = comp, G_16, , vga_driver, 10, 161:0:161:14
+instance = comp, COLUMN_COUNT_next_un10_column_counter_siglto9, , vga_driver, 13, 111:9:111:41
+instance = comp, hsync_state_next_1_sqmuxa_2_cZ, , vga_driver, 13, 218:11:218:33
+instance = comp, hsync_state_next_1_sqmuxa_1_cZ, , vga_driver, 13, 213:11:213:32
+instance = comp, HSYNC_FSM_next_un13_hsync_counter, , vga_driver, 13, 231:11:231:32
+instance = comp, HSYNC_COUNT_next_un9_hsync_counterlt9, , vga_driver, 13, 172:9:172:36
+instance = comp, VSYNC_COUNT_next_un9_vsync_counterlt9, , vga_driver, 13, 281:9:281:36
+instance = comp, HSYNC_FSM_next_un12_hsync_counter, , vga_driver, 13, 226:11:226:34
+instance = comp, LINE_COUNT_next_un10_line_counter_siglto5, , vga_driver, 13, 139:9:139:40
+instance = comp, VSYNC_FSM_next_un15_vsync_counter_4, , vga_driver, 13, 344:11:344:32
+instance = comp, VSYNC_FSM_next_un13_vsync_counter_4, , vga_driver, 13, 331:11:331:33
+instance = comp, COLUMN_COUNT_next_un10_column_counter_siglt6, , vga_driver, 13, 111:9:111:41
+instance = comp, hsync_counter_next_1_sqmuxa_cZ, , vga_driver, 13, 169:7:169:32
+instance = comp, VSYNC_FSM_next_un14_vsync_counter_8, , vga_driver, 13, 339:11:339:34
+instance = comp, line_counter_next_0_sqmuxa_1_1_cZ, , vga_driver, 13, 139:9:139:40
+instance = comp, vsync_counter_next_1_sqmuxa_cZ, , vga_driver, 13, 278:7:278:32
+instance = comp, column_counter_next_0_sqmuxa_1_1_cZ, , vga_driver, 13, 111:9:111:41
+instance = comp, HSYNC_FSM_next_un12_hsync_counter_4, , vga_driver, 13, 226:11:226:34
+instance = comp, HSYNC_FSM_next_un12_hsync_counter_3, , vga_driver, 13, 226:11:226:34
+instance = comp, HSYNC_FSM_next_un11_hsync_counter_3, , vga_driver, 13, 218:11:218:33
+instance = comp, HSYNC_FSM_next_un11_hsync_counter_2, , vga_driver, 13, 218:11:218:33
+instance = comp, HSYNC_COUNT_next_un9_hsync_counterlt9_3, , vga_driver, 13, 172:9:172:36
+instance = comp, HSYNC_FSM_next_un13_hsync_counter_2, , vga_driver, 13, 231:11:231:32
+instance = comp, VSYNC_COUNT_next_un9_vsync_counterlt9_6, , vga_driver, 13, 281:9:281:36
+instance = comp, VSYNC_COUNT_next_un9_vsync_counterlt9_5, , vga_driver, 13, 281:9:281:36
+instance = comp, HSYNC_FSM_next_un10_hsync_counter_4, , vga_driver, 13, 213:11:213:32
+instance = comp, HSYNC_FSM_next_un10_hsync_counter_3, , vga_driver, 13, 213:11:213:32
+instance = comp, VSYNC_FSM_next_un15_vsync_counter_3, , vga_driver, 13, 344:11:344:32
+instance = comp, VSYNC_FSM_next_un13_vsync_counter_3, , vga_driver, 13, 331:11:331:33
+instance = comp, COLUMN_COUNT_next_un10_column_counter_siglt6_4, , vga_driver, 13, 111:9:111:41
+instance = comp, LINE_COUNT_next_un10_line_counter_siglt4_2, , vga_driver, 13, 139:9:139:40
+instance = comp, HSYNC_FSM_next_un10_hsync_counter_1, , vga_driver, 13, 213:11:213:32
+instance = comp, VSYNC_FSM_next_un12_vsync_counter_6, , vga_driver, 13, 326:11:326:32
+instance = comp, VSYNC_FSM_next_un12_vsync_counter_7, , vga_driver, 13, 326:11:326:32
+instance = comp, HSYNC_FSM_next_un13_hsync_counter_7, , vga_driver, 13, 231:11:231:32
+instance = comp, un1_hsync_state_3_0_cZ, , vga_driver, 13, 206:4:206:7
+instance = comp, un1_vsync_state_2_0_cZ, , vga_driver, 13, 319:4:319:7
+instance = comp, d_set_hsync_counter_cZ, , vga_driver, 13, 248:4:248:7
+instance = comp, d_set_vsync_counter_cZ, , vga_driver, 13, 361:4:361:7
+instance = comp, un1_line_counter_sig_9_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_8_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_7_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_6_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_5_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_4_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_3_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_2_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_a_1_, , vga_driver, 13, 141:31:141:52
+instance = comp, un1_line_counter_sig_1_, , vga_driver, 13, 141:31:141:52
+instance = comp, un2_column_counter_next_9_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_8_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_7_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_6_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_5_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_4_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_3_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_2_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_1_, , vga_driver, 13, 112:31:112:54
+instance = comp, un2_column_counter_next_0_, , vga_driver, 13, 112:31:112:54
--- /dev/null
+source "/opt/synplify/fpga_c200906/lib/altera/quartus_cons.tcl"
+syn_create_and_open_prj vga
+source $::quartus(binpath)/prj_asd_import.tcl
+syn_create_and_open_csf vga
+syn_handle_cons vga
+syn_compile_quartus
--- /dev/null
+set_global_assignment -name TOP_LEVEL_ENTITY "|vga" -remove
+set_global_assignment -name FAMILY -remove
+set_global_assignment -name TAO_FILE "myresults.tao" -remove
+set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000" -remove
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON -remove
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF" -remove
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF" -remove
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "OFF" -remove
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF" -remove
+set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF" -remove
+#set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY" -remove
+create_base_clock clk_pin_setting -fmax 25.175mhz -duty_cycle 50.00 -target clk_pin -disable
--- /dev/null
+#-- Synplicity, Inc.
+#-- Version C-2009.06
+#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/vga.prd
+#-- Written on Wed Oct 21 17:34:16 2009
+
+#
+### Watch Implementation type ###
+#
+watch_impl -all
+#
+### Watch Implementation properties ###
+#
+watch_prop -clear
--- /dev/null
+#-- Synplicity, Inc.
+#-- Version C-2009.06
+#-- Project file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/vga.prj
+#-- Written on Wed Oct 21 17:34:16 2009
+
+
+#project files
+add_file -vhdl -lib work "../src/vga_pak.vhd"
+add_file -vhdl -lib work "../src/vga_ent.vhd"
+add_file -vhdl -lib work "../src/vga_arc.vhd"
+add_file -vhdl -lib work "../src/board_driver_ent.vhd"
+add_file -vhdl -lib work "../src/board_driver_arc.vhd"
+add_file -vhdl -lib work "../src/vga_control_ent.vhd"
+add_file -vhdl -lib work "../src/vga_control_arc.vhd"
+add_file -vhdl -lib work "../src/vga_driver_ent.vhd"
+add_file -vhdl -lib work "../src/vga_driver_arc.vhd"
+
+
+#implementation: "rev_1"
+impl -add rev_1 -type fpga
+
+#device options
+set_option -technology STRATIX
+set_option -part EP1S25
+set_option -package FC672
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "vga"
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# mapper_options
+set_option -frequency 25.175
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# Altera STRATIX
+set_option -run_prop_extract 1
+set_option -maxfan 500
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -quartus_version 9.0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./rev_1/vga.vqm"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "rev_1"
--- /dev/null
+# // ModelSim SE 6.5b May 21 2009 Linux 2.6.18-128.2.1.el5
+# //
+# // Copyright 1991-2009 Mentor Graphics Corporation
+# // All Rights Reserved.
+# //
+# // THIS WORK CONTAINS TRADE SECRET AND
+# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
+# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
+# // AND IS SUBJECT TO LICENSE TERMS.
+# //
+vmap -del stratix
+# ** Error: (vmap-20) Cannot access for writing file "/opt/modelsim/modeltech/linux/../modelsim.ini".
+# Permission denied. (errno = EACCES)
projects / dide_16.git / commitdiff