-- -- Written by Synplicity -- Product Version "C-2009.06" -- Program "Synplify Pro", Mapper "map450rc, Build 029R" -- Wed Oct 21 17:26:36 2009 -- -- -- Written by Synplify Pro version Build 029R -- Wed Oct 21 17:26:36 2009 -- -- library ieee, stratix; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; use stratix.stratix_components.all; entity vga_control is port( line_counter_sig_0 : in std_logic; line_counter_sig_2 : in std_logic; line_counter_sig_1 : in std_logic; line_counter_sig_3 : in std_logic; line_counter_sig_6 : in std_logic; line_counter_sig_5 : in std_logic; line_counter_sig_4 : in std_logic; line_counter_sig_7 : in std_logic; line_counter_sig_8 : in std_logic; column_counter_sig_0 : in std_logic; column_counter_sig_1 : in std_logic; column_counter_sig_2 : in std_logic; column_counter_sig_8 : in std_logic; column_counter_sig_3 : in std_logic; column_counter_sig_5 : in std_logic; column_counter_sig_4 : in std_logic; column_counter_sig_9 : in std_logic; column_counter_sig_7 : in std_logic; column_counter_sig_6 : in std_logic; toggle_counter_sig_0 : out std_logic; toggle_counter_sig_1 : out std_logic; toggle_counter_sig_2 : out std_logic; toggle_counter_sig_3 : out std_logic; toggle_counter_sig_4 : out std_logic; toggle_counter_sig_5 : out std_logic; toggle_counter_sig_6 : out std_logic; toggle_counter_sig_7 : out std_logic; toggle_counter_sig_8 : out std_logic; toggle_counter_sig_9 : out std_logic; toggle_counter_sig_10 : out std_logic; toggle_counter_sig_11 : out std_logic; toggle_counter_sig_12 : out std_logic; toggle_counter_sig_13 : out std_logic; toggle_counter_sig_14 : out std_logic; toggle_counter_sig_15 : out std_logic; toggle_counter_sig_16 : out std_logic; toggle_counter_sig_17 : out std_logic; toggle_counter_sig_18 : out std_logic; toggle_counter_sig_19 : out std_logic; toggle_counter_sig_20 : out std_logic; toggle_counter_sig_21 : out std_logic; toggle_counter_sig_22 : out std_logic; toggle_counter_sig_23 : out std_logic; toggle_counter_sig_24 : out std_logic; h_enable_sig : in std_logic; g : out std_logic; b : out std_logic; v_enable_sig : in std_logic; r : out std_logic; toggle_sig : out std_logic; un6_dly_counter_0_x : in std_logic; clk_pin_c : in std_logic); end vga_control; architecture beh of vga_control is signal devclrn : std_logic := '1'; signal devpor : std_logic := '1'; signal devoe : std_logic := '0'; signal TOGGLE_COUNTER_SIG_COUT : std_logic_vector(18 downto 1); signal UN2_TOGGLE_COUNTER_NEXT_COUT : std_logic_vector(0 to 0); signal GND : std_logic ; signal TOGGLE_SIG_0_0_0_G1 : std_logic ; signal TOGGLE_SIG_83 : std_logic ; signal B_NEXT_0_SQMUXA_7_4 : std_logic ; signal B_NEXT_0_SQMUXA_7_5 : std_logic ; signal TOGGLE_SIG_0_0_0_G1_2 : std_logic ; signal UN1_TOGGLE_COUNTER_SIGLTO18 : std_logic ; signal UN1_TOGGLE_COUNTER_SIGLTO15 : std_logic ; signal UN5_V_ENABLELTO5 : std_logic ; signal B_NEXT_0_SQMUXA_7_3 : std_logic ; signal UN13_V_ENABLELTO6 : std_logic ; signal B_NEXT_0_SQMUXA_7_4_A : std_logic ; signal UN17_V_ENABLELTO3 : std_logic ; signal B_NEXT_0_SQMUXA_7_2 : std_logic ; signal UN9_V_ENABLELTO6 : std_logic ; signal UN1_TOGGLE_COUNTER_SIGLTO12 : std_logic ; signal UN5_V_ENABLELT2 : std_logic ; signal UN1_TOGGLE_COUNTER_SIGLTO9 : std_logic ; signal UN13_V_ENABLELTO4_0 : std_logic ; signal UN9_V_ENABLELTO4 : std_logic ; signal UN1_TOGGLE_COUNTER_SIGLT6 : std_logic ; signal TOGGLE_COUNTER_SIG_58 : std_logic ; signal TOGGLE_COUNTER_SIG_59 : std_logic ; signal TOGGLE_COUNTER_SIG_60 : std_logic ; signal TOGGLE_COUNTER_SIG_61 : std_logic ; signal TOGGLE_COUNTER_SIG_62 : std_logic ; signal TOGGLE_COUNTER_SIG_63 : std_logic ; signal TOGGLE_COUNTER_SIG_64 : std_logic ; signal TOGGLE_COUNTER_SIG_65 : std_logic ; signal TOGGLE_COUNTER_SIG_66 : std_logic ; signal TOGGLE_COUNTER_SIG_67 : std_logic ; signal TOGGLE_COUNTER_SIG_68 : std_logic ; signal TOGGLE_COUNTER_SIG_69 : std_logic ; signal TOGGLE_COUNTER_SIG_70 : std_logic ; signal TOGGLE_COUNTER_SIG_71 : std_logic ; signal TOGGLE_COUNTER_SIG_72 : std_logic ; signal TOGGLE_COUNTER_SIG_73 : std_logic ; signal TOGGLE_COUNTER_SIG_74 : std_logic ; signal TOGGLE_COUNTER_SIG_75 : std_logic ; signal TOGGLE_COUNTER_SIG_76 : std_logic ; signal TOGGLE_COUNTER_SIG_77 : std_logic ; signal TOGGLE_COUNTER_SIG_78 : std_logic ; signal TOGGLE_COUNTER_SIG_79 : std_logic ; signal TOGGLE_COUNTER_SIG_80 : std_logic ; signal TOGGLE_COUNTER_SIG_81 : std_logic ; signal TOGGLE_COUNTER_SIG_82 : std_logic ; signal VCC : std_logic ; signal TOGGLE_SIG_0_0_0_G1_I : std_logic ; begin \TOGGLE_COUNTER_SIG_24_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff00") port map ( regout => TOGGLE_COUNTER_SIG_82, clk => clk_pin_c, datad => GND, aclr => un6_dly_counter_0_x, devpor => devpor, devclrn => devclrn, dataa => VCC, datab => VCC, datac => VCC, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_23_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff00") port map ( regout => TOGGLE_COUNTER_SIG_81, clk => clk_pin_c, datad => GND, aclr => un6_dly_counter_0_x, devpor => devpor, devclrn => devclrn, dataa => VCC, datab => VCC, datac => VCC, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_22_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff00") port map ( regout => TOGGLE_COUNTER_SIG_80, clk => clk_pin_c, datad => GND, aclr => un6_dly_counter_0_x, devpor => devpor, devclrn => devclrn, dataa => VCC, datab => VCC, datac => VCC, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_21_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff00") port map ( regout => TOGGLE_COUNTER_SIG_79, clk => clk_pin_c, datad => GND, aclr => un6_dly_counter_0_x, devpor => devpor, devclrn => devclrn, dataa => VCC, datab => VCC, datac => VCC, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_20_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a5a") port map ( regout => TOGGLE_COUNTER_SIG_78, clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_78, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(18), devpor => devpor, devclrn => devclrn, datab => VCC, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_19_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c6c") port map ( regout => TOGGLE_COUNTER_SIG_77, clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_76, datab => TOGGLE_COUNTER_SIG_77, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(17), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_18_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_76, cout => TOGGLE_COUNTER_SIG_COUT(18), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_76, datab => TOGGLE_COUNTER_SIG_77, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(16), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_17_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( regout => TOGGLE_COUNTER_SIG_75, cout => TOGGLE_COUNTER_SIG_COUT(17), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_74, datab => TOGGLE_COUNTER_SIG_75, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(15), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_16_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_74, cout => TOGGLE_COUNTER_SIG_COUT(16), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_74, datab => TOGGLE_COUNTER_SIG_75, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(14), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_15_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( regout => TOGGLE_COUNTER_SIG_73, cout => TOGGLE_COUNTER_SIG_COUT(15), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_72, datab => TOGGLE_COUNTER_SIG_73, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(13), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_14_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_72, cout => TOGGLE_COUNTER_SIG_COUT(14), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_72, datab => TOGGLE_COUNTER_SIG_73, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(12), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_13_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( regout => TOGGLE_COUNTER_SIG_71, cout => TOGGLE_COUNTER_SIG_COUT(13), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_70, datab => TOGGLE_COUNTER_SIG_71, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(11), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_12_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_70, cout => TOGGLE_COUNTER_SIG_COUT(12), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_70, datab => TOGGLE_COUNTER_SIG_71, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(10), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_11_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( regout => TOGGLE_COUNTER_SIG_69, cout => TOGGLE_COUNTER_SIG_COUT(11), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_68, datab => TOGGLE_COUNTER_SIG_69, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(9), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_10_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_68, cout => TOGGLE_COUNTER_SIG_COUT(10), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_68, datab => TOGGLE_COUNTER_SIG_69, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(8), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_9_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( regout => TOGGLE_COUNTER_SIG_67, cout => TOGGLE_COUNTER_SIG_COUT(9), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_66, datab => TOGGLE_COUNTER_SIG_67, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(7), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_8_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_66, cout => TOGGLE_COUNTER_SIG_COUT(8), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_66, datab => TOGGLE_COUNTER_SIG_67, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(6), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_7_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( regout => TOGGLE_COUNTER_SIG_65, cout => TOGGLE_COUNTER_SIG_COUT(7), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_64, datab => TOGGLE_COUNTER_SIG_65, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(5), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_6_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_64, cout => TOGGLE_COUNTER_SIG_COUT(6), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_64, datab => TOGGLE_COUNTER_SIG_65, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(4), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_5_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( regout => TOGGLE_COUNTER_SIG_63, cout => TOGGLE_COUNTER_SIG_COUT(5), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_62, datab => TOGGLE_COUNTER_SIG_63, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(3), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_4_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_62, cout => TOGGLE_COUNTER_SIG_COUT(4), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_62, datab => TOGGLE_COUNTER_SIG_63, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(2), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_3_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( regout => TOGGLE_COUNTER_SIG_61, cout => TOGGLE_COUNTER_SIG_COUT(3), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_60, datab => TOGGLE_COUNTER_SIG_61, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => TOGGLE_COUNTER_SIG_COUT(1), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_2_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( regout => TOGGLE_COUNTER_SIG_60, cout => TOGGLE_COUNTER_SIG_COUT(2), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_60, datab => TOGGLE_COUNTER_SIG_61, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, cin => UN2_TOGGLE_COUNTER_NEXT_COUT(0), devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_1_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "6688") port map ( regout => TOGGLE_COUNTER_SIG_59, cout => TOGGLE_COUNTER_SIG_COUT(1), clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_58, datab => TOGGLE_COUNTER_SIG_59, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \TOGGLE_COUNTER_SIG_0_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "5555") port map ( regout => TOGGLE_COUNTER_SIG_58, clk => clk_pin_c, dataa => TOGGLE_COUNTER_SIG_58, aclr => un6_dly_counter_0_x, sclr => TOGGLE_SIG_0_0_0_G1_I, devpor => devpor, devclrn => devclrn, datab => VCC, datac => VCC, datad => VCC, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); TOGGLE_SIG_Z146: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "9999") port map ( regout => TOGGLE_SIG_83, clk => clk_pin_c, dataa => TOGGLE_SIG_83, datab => TOGGLE_SIG_0_0_0_G1, aclr => un6_dly_counter_0_x, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); R_Z147: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8000") port map ( regout => r, clk => clk_pin_c, dataa => TOGGLE_SIG_83, datab => v_enable_sig, datac => B_NEXT_0_SQMUXA_7_4, datad => B_NEXT_0_SQMUXA_7_5, aclr => un6_dly_counter_0_x, devpor => devpor, devclrn => devclrn, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); B_Z148: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "4000") port map ( regout => b, clk => clk_pin_c, dataa => TOGGLE_SIG_83, datab => v_enable_sig, datac => B_NEXT_0_SQMUXA_7_4, datad => B_NEXT_0_SQMUXA_7_5, aclr => un6_dly_counter_0_x, devpor => devpor, devclrn => devclrn, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); G_Z149: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff00") port map ( regout => g, clk => clk_pin_c, datad => GND, aclr => un6_dly_counter_0_x, devpor => devpor, devclrn => devclrn, dataa => VCC, datab => VCC, datac => VCC, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); TOGGLE_SIG_0_0_0_G1_Z150: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0703") port map ( combout => TOGGLE_SIG_0_0_0_G1, dataa => TOGGLE_COUNTER_SIG_77, datab => TOGGLE_COUNTER_SIG_78, datac => TOGGLE_SIG_0_0_0_G1_2, datad => UN1_TOGGLE_COUNTER_SIGLTO18, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO18: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7f77") port map ( combout => UN1_TOGGLE_COUNTER_SIGLTO18, dataa => TOGGLE_COUNTER_SIG_75, datab => TOGGLE_COUNTER_SIG_76, datac => TOGGLE_COUNTER_SIG_74, datad => UN1_TOGGLE_COUNTER_SIGLTO15, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); B_NEXT_0_SQMUXA_7_5_Z152: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7f00") port map ( combout => B_NEXT_0_SQMUXA_7_5, dataa => column_counter_sig_6, datab => column_counter_sig_7, datac => UN5_V_ENABLELTO5, datad => B_NEXT_0_SQMUXA_7_3, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); B_NEXT_0_SQMUXA_7_4_Z153: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ef23") port map ( combout => B_NEXT_0_SQMUXA_7_4, dataa => line_counter_sig_8, datab => line_counter_sig_7, datac => UN13_V_ENABLELTO6, datad => B_NEXT_0_SQMUXA_7_4_A, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); B_NEXT_0_SQMUXA_7_4_A_Z154: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0f1f") port map ( combout => B_NEXT_0_SQMUXA_7_4_A, dataa => line_counter_sig_4, datab => line_counter_sig_5, datac => line_counter_sig_6, datad => UN17_V_ENABLELTO3, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); B_NEXT_0_SQMUXA_7_3_Z155: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "e0f0") port map ( combout => B_NEXT_0_SQMUXA_7_3, dataa => column_counter_sig_7, datab => column_counter_sig_9, datac => B_NEXT_0_SQMUXA_7_2, datad => UN9_V_ENABLELTO6, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO15: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff7f") port map ( combout => UN1_TOGGLE_COUNTER_SIGLTO15, dataa => TOGGLE_COUNTER_SIG_71, datab => TOGGLE_COUNTER_SIG_72, datac => TOGGLE_COUNTER_SIG_73, datad => UN1_TOGGLE_COUNTER_SIGLTO12, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); DRAW_SQUARE_NEXT_UN5_V_ENABLELTO5: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "feee") port map ( combout => UN5_V_ENABLELTO5, dataa => column_counter_sig_4, datab => column_counter_sig_5, datac => column_counter_sig_3, datad => UN5_V_ENABLELT2, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO12: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0100") port map ( combout => UN1_TOGGLE_COUNTER_SIGLTO12, dataa => TOGGLE_COUNTER_SIG_68, datab => TOGGLE_COUNTER_SIG_69, datac => TOGGLE_COUNTER_SIG_70, datad => UN1_TOGGLE_COUNTER_SIGLTO9, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); DRAW_SQUARE_NEXT_UN13_V_ENABLELTO6: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7f77") port map ( combout => UN13_V_ENABLELTO6, dataa => line_counter_sig_5, datab => line_counter_sig_6, datac => line_counter_sig_3, datad => UN13_V_ENABLELTO4_0, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); DRAW_SQUARE_NEXT_UN9_V_ENABLELTO6: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "f7f7") port map ( combout => UN9_V_ENABLELTO6, dataa => column_counter_sig_5, datab => column_counter_sig_6, datac => UN9_V_ENABLELTO4, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO9: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7f77") port map ( combout => UN1_TOGGLE_COUNTER_SIGLTO9, dataa => TOGGLE_COUNTER_SIG_66, datab => TOGGLE_COUNTER_SIG_67, datac => TOGGLE_COUNTER_SIG_65, datad => UN1_TOGGLE_COUNTER_SIGLT6, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); DRAW_SQUARE_NEXT_UN17_V_ENABLELTO3: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "fe00") port map ( combout => UN17_V_ENABLELTO3, dataa => line_counter_sig_1, datab => line_counter_sig_2, datac => line_counter_sig_0, datad => line_counter_sig_3, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); TOGGLE_SIG_0_0_0_G1_2_Z163: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "fffe") port map ( combout => TOGGLE_SIG_0_0_0_G1_2, dataa => TOGGLE_COUNTER_SIG_81, datab => TOGGLE_COUNTER_SIG_82, datac => TOGGLE_COUNTER_SIG_79, datad => TOGGLE_COUNTER_SIG_80, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); B_NEXT_0_SQMUXA_7_2_Z164: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0004") port map ( combout => B_NEXT_0_SQMUXA_7_2, dataa => column_counter_sig_8, datab => h_enable_sig, datac => column_counter_sig_9, datad => line_counter_sig_8, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); DRAW_SQUARE_NEXT_UN9_V_ENABLELTO4: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0101") port map ( combout => UN9_V_ENABLELTO4, dataa => column_counter_sig_3, datab => column_counter_sig_4, datac => column_counter_sig_2, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); DRAW_SQUARE_NEXT_UN5_V_ENABLELT2: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "fefe") port map ( combout => UN5_V_ENABLELT2, dataa => column_counter_sig_1, datab => column_counter_sig_2, datac => column_counter_sig_0, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); DRAW_SQUARE_NEXT_UN13_V_ENABLELTO4_0: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "1111") port map ( combout => UN13_V_ENABLELTO4_0, dataa => line_counter_sig_4, datab => line_counter_sig_2, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLT6: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7777") port map ( combout => UN1_TOGGLE_COUNTER_SIGLT6, dataa => TOGGLE_COUNTER_SIG_64, datab => TOGGLE_COUNTER_SIG_63, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \UN2_TOGGLE_COUNTER_NEXT_0_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "5588") port map ( cout => UN2_TOGGLE_COUNTER_NEXT_COUT(0), dataa => TOGGLE_COUNTER_SIG_58, datab => TOGGLE_COUNTER_SIG_59, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); GND <= '0'; VCC <= '1'; TOGGLE_SIG_0_0_0_G1_I <= not TOGGLE_SIG_0_0_0_G1; toggle_counter_sig_0 <= TOGGLE_COUNTER_SIG_58; toggle_counter_sig_1 <= TOGGLE_COUNTER_SIG_59; toggle_counter_sig_2 <= TOGGLE_COUNTER_SIG_60; toggle_counter_sig_3 <= TOGGLE_COUNTER_SIG_61; toggle_counter_sig_4 <= TOGGLE_COUNTER_SIG_62; toggle_counter_sig_5 <= TOGGLE_COUNTER_SIG_63; toggle_counter_sig_6 <= TOGGLE_COUNTER_SIG_64; toggle_counter_sig_7 <= TOGGLE_COUNTER_SIG_65; toggle_counter_sig_8 <= TOGGLE_COUNTER_SIG_66; toggle_counter_sig_9 <= TOGGLE_COUNTER_SIG_67; toggle_counter_sig_10 <= TOGGLE_COUNTER_SIG_68; toggle_counter_sig_11 <= TOGGLE_COUNTER_SIG_69; toggle_counter_sig_12 <= TOGGLE_COUNTER_SIG_70; toggle_counter_sig_13 <= TOGGLE_COUNTER_SIG_71; toggle_counter_sig_14 <= TOGGLE_COUNTER_SIG_72; toggle_counter_sig_15 <= TOGGLE_COUNTER_SIG_73; toggle_counter_sig_16 <= TOGGLE_COUNTER_SIG_74; toggle_counter_sig_17 <= TOGGLE_COUNTER_SIG_75; toggle_counter_sig_18 <= TOGGLE_COUNTER_SIG_76; toggle_counter_sig_19 <= TOGGLE_COUNTER_SIG_77; toggle_counter_sig_20 <= TOGGLE_COUNTER_SIG_78; toggle_counter_sig_21 <= TOGGLE_COUNTER_SIG_79; toggle_counter_sig_22 <= TOGGLE_COUNTER_SIG_80; toggle_counter_sig_23 <= TOGGLE_COUNTER_SIG_81; toggle_counter_sig_24 <= TOGGLE_COUNTER_SIG_82; toggle_sig <= TOGGLE_SIG_83; end beh; -- library ieee, stratix; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; use stratix.stratix_components.all; entity vga_driver is port( line_counter_sig_0 : out std_logic; line_counter_sig_1 : out std_logic; line_counter_sig_2 : out std_logic; line_counter_sig_3 : out std_logic; line_counter_sig_4 : out std_logic; line_counter_sig_5 : out std_logic; line_counter_sig_6 : out std_logic; line_counter_sig_7 : out std_logic; line_counter_sig_8 : out std_logic; dly_counter_1 : in std_logic; dly_counter_0 : in std_logic; vsync_state_2 : out std_logic; vsync_state_5 : out std_logic; vsync_state_3 : out std_logic; vsync_state_6 : out std_logic; vsync_state_4 : out std_logic; vsync_state_1 : out std_logic; vsync_state_0 : out std_logic; hsync_state_2 : out std_logic; hsync_state_4 : out std_logic; hsync_state_0 : out std_logic; hsync_state_5 : out std_logic; hsync_state_1 : out std_logic; hsync_state_3 : out std_logic; hsync_state_6 : out std_logic; column_counter_sig_0 : out std_logic; column_counter_sig_1 : out std_logic; column_counter_sig_2 : out std_logic; column_counter_sig_3 : out std_logic; column_counter_sig_4 : out std_logic; column_counter_sig_5 : out std_logic; column_counter_sig_6 : out std_logic; column_counter_sig_7 : out std_logic; column_counter_sig_8 : out std_logic; column_counter_sig_9 : out std_logic; vsync_counter_9 : out std_logic; vsync_counter_8 : out std_logic; vsync_counter_7 : out std_logic; vsync_counter_6 : out std_logic; vsync_counter_5 : out std_logic; vsync_counter_4 : out std_logic; vsync_counter_3 : out std_logic; vsync_counter_2 : out std_logic; vsync_counter_1 : out std_logic; vsync_counter_0 : out std_logic; hsync_counter_9 : out std_logic; hsync_counter_8 : out std_logic; hsync_counter_7 : out std_logic; hsync_counter_6 : out std_logic; hsync_counter_5 : out std_logic; hsync_counter_4 : out std_logic; hsync_counter_3 : out std_logic; hsync_counter_2 : out std_logic; hsync_counter_1 : out std_logic; hsync_counter_0 : out std_logic; d_set_vsync_counter : out std_logic; v_sync : out std_logic; h_sync : out std_logic; h_enable_sig : out std_logic; v_enable_sig : out std_logic; reset_pin_c : in std_logic; un6_dly_counter_0_x : out std_logic; d_set_hsync_counter : out std_logic; clk_pin_c : in std_logic); end vga_driver; architecture beh of vga_driver is signal devclrn : std_logic := '1'; signal devpor : std_logic := '1'; signal devoe : std_logic := '0'; signal HSYNC_COUNTER_COUT : std_logic_vector(8 downto 0); signal VSYNC_COUNTER_COUT : std_logic_vector(8 downto 0); signal UN2_COLUMN_COUNTER_NEXT_COMBOUT : std_logic_vector(9 downto 1); signal UN1_LINE_COUNTER_SIG_COMBOUT : std_logic_vector(9 downto 1); signal UN1_LINE_COUNTER_SIG_COUT : std_logic_vector(7 downto 1); signal UN1_LINE_COUNTER_SIG_A_COUT : std_logic_vector(1 to 1); signal UN2_COLUMN_COUNTER_NEXT_COUT : std_logic_vector(7 downto 0); signal HSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ; signal G_2_I : std_logic ; signal UN9_HSYNC_COUNTERLT9 : std_logic ; signal VSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ; signal G_16_I : std_logic ; signal UN9_VSYNC_COUNTERLT9 : std_logic ; signal UN10_COLUMN_COUNTER_SIGLTO9 : std_logic ; signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ; signal \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\ : std_logic ; signal UN6_DLY_COUNTER_0_X_56 : std_logic ; signal VSYNC_STATE_NEXT_2_SQMUXA : std_logic ; signal UN12_VSYNC_COUNTER_7 : std_logic ; signal UN13_VSYNC_COUNTER_4 : std_logic ; signal UN10_LINE_COUNTER_SIGLTO8 : std_logic ; signal LINE_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ; signal V_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ; signal H_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ; signal H_SYNC_1_0_0_0_G1 : std_logic ; signal V_SYNC_1_0_0_0_G1 : std_logic ; signal UN14_VSYNC_COUNTER_8 : std_logic ; signal \HSYNC_STATE_3_0_0_0__G0_0\ : std_logic ; signal UN10_HSYNC_COUNTER_3 : std_logic ; signal UN10_HSYNC_COUNTER_1 : std_logic ; signal UN10_HSYNC_COUNTER_4 : std_logic ; signal UN12_HSYNC_COUNTER : std_logic ; signal UN11_HSYNC_COUNTER_2 : std_logic ; signal UN11_HSYNC_COUNTER_3 : std_logic ; signal UN13_HSYNC_COUNTER : std_logic ; signal VSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ; signal VSYNC_STATE_NEXT_1_SQMUXA_3 : std_logic ; signal UN1_VSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ; signal HSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ; signal HSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ; signal UN1_HSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ; signal UN12_VSYNC_COUNTER_6 : std_logic ; signal UN15_VSYNC_COUNTER_4 : std_logic ; signal VSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ; signal UN10_LINE_COUNTER_SIGLTO5 : std_logic ; signal UN10_COLUMN_COUNTER_SIGLT6 : std_logic ; signal UN13_HSYNC_COUNTER_2 : std_logic ; signal UN13_HSYNC_COUNTER_7 : std_logic ; signal UN9_HSYNC_COUNTERLT9_3 : std_logic ; signal UN9_VSYNC_COUNTERLT9_5 : std_logic ; signal UN9_VSYNC_COUNTERLT9_6 : std_logic ; signal UN12_HSYNC_COUNTER_3 : std_logic ; signal UN12_HSYNC_COUNTER_4 : std_logic ; signal UN10_LINE_COUNTER_SIGLT4_2 : std_logic ; signal UN15_VSYNC_COUNTER_3 : std_logic ; signal UN13_VSYNC_COUNTER_3 : std_logic ; signal UN10_COLUMN_COUNTER_SIGLT6_4 : std_logic ; signal D_SET_HSYNC_COUNTER_57 : std_logic ; signal V_SYNC_54 : std_logic ; signal UN1_VSYNC_STATE_2_0 : std_logic ; signal H_SYNC_55 : std_logic ; signal UN1_HSYNC_STATE_3_0 : std_logic ; signal D_SET_VSYNC_COUNTER_53 : std_logic ; signal VCC : std_logic ; signal LINE_COUNTER_SIG_0_0 : std_logic ; signal LINE_COUNTER_SIG_1_0 : std_logic ; signal LINE_COUNTER_SIG_2_0 : std_logic ; signal LINE_COUNTER_SIG_3_0 : std_logic ; signal LINE_COUNTER_SIG_4_0 : std_logic ; signal LINE_COUNTER_SIG_5_0 : std_logic ; signal LINE_COUNTER_SIG_6_0 : std_logic ; signal LINE_COUNTER_SIG_7_0 : std_logic ; signal LINE_COUNTER_SIG_8_0 : std_logic ; signal VSYNC_STATE_9 : std_logic ; signal VSYNC_STATE_10 : std_logic ; signal VSYNC_STATE_11 : std_logic ; signal VSYNC_STATE_12 : std_logic ; signal VSYNC_STATE_13 : std_logic ; signal VSYNC_STATE_14 : std_logic ; signal VSYNC_STATE_15 : std_logic ; signal HSYNC_STATE_16 : std_logic ; signal HSYNC_STATE_17 : std_logic ; signal HSYNC_STATE_18 : std_logic ; signal HSYNC_STATE_19 : std_logic ; signal HSYNC_STATE_20 : std_logic ; signal HSYNC_STATE_21 : std_logic ; signal HSYNC_STATE_22 : std_logic ; signal COLUMN_COUNTER_SIG_23 : std_logic ; signal COLUMN_COUNTER_SIG_24 : std_logic ; signal COLUMN_COUNTER_SIG_25 : std_logic ; signal COLUMN_COUNTER_SIG_26 : std_logic ; signal COLUMN_COUNTER_SIG_27 : std_logic ; signal COLUMN_COUNTER_SIG_28 : std_logic ; signal COLUMN_COUNTER_SIG_29 : std_logic ; signal COLUMN_COUNTER_SIG_30 : std_logic ; signal COLUMN_COUNTER_SIG_31 : std_logic ; signal COLUMN_COUNTER_SIG_32 : std_logic ; signal VSYNC_COUNTER_33 : std_logic ; signal VSYNC_COUNTER_34 : std_logic ; signal VSYNC_COUNTER_35 : std_logic ; signal VSYNC_COUNTER_36 : std_logic ; signal VSYNC_COUNTER_37 : std_logic ; signal VSYNC_COUNTER_38 : std_logic ; signal VSYNC_COUNTER_39 : std_logic ; signal VSYNC_COUNTER_40 : std_logic ; signal VSYNC_COUNTER_41 : std_logic ; signal VSYNC_COUNTER_42 : std_logic ; signal HSYNC_COUNTER_43 : std_logic ; signal HSYNC_COUNTER_44 : std_logic ; signal HSYNC_COUNTER_45 : std_logic ; signal HSYNC_COUNTER_46 : std_logic ; signal HSYNC_COUNTER_47 : std_logic ; signal HSYNC_COUNTER_48 : std_logic ; signal HSYNC_COUNTER_49 : std_logic ; signal HSYNC_COUNTER_50 : std_logic ; signal HSYNC_COUNTER_51 : std_logic ; signal HSYNC_COUNTER_52 : std_logic ; signal GND : std_logic ; signal LINE_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ; signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ; signal G_16_I_I : std_logic ; signal UN9_VSYNC_COUNTERLT9_I : std_logic ; signal G_2_I_I : std_logic ; signal UN9_HSYNC_COUNTERLT9_I : std_logic ; begin \HSYNC_COUNTER_0_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "55aa") port map ( regout => HSYNC_COUNTER_52, cout => HSYNC_COUNTER_COUT(0), clk => clk_pin_c, dataa => HSYNC_COUNTER_52, datab => VCC, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, devpor => devpor, devclrn => devclrn, datad => VCC, aclr => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \HSYNC_COUNTER_1_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => HSYNC_COUNTER_51, cout => HSYNC_COUNTER_COUT(1), clk => clk_pin_c, dataa => HSYNC_COUNTER_51, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(0), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \HSYNC_COUNTER_2_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => HSYNC_COUNTER_50, cout => HSYNC_COUNTER_COUT(2), clk => clk_pin_c, dataa => HSYNC_COUNTER_50, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(1), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \HSYNC_COUNTER_3_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => HSYNC_COUNTER_49, cout => HSYNC_COUNTER_COUT(3), clk => clk_pin_c, dataa => HSYNC_COUNTER_49, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(2), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \HSYNC_COUNTER_4_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => HSYNC_COUNTER_48, cout => HSYNC_COUNTER_COUT(4), clk => clk_pin_c, dataa => HSYNC_COUNTER_48, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(3), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \HSYNC_COUNTER_5_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => HSYNC_COUNTER_47, cout => HSYNC_COUNTER_COUT(5), clk => clk_pin_c, dataa => HSYNC_COUNTER_47, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(4), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \HSYNC_COUNTER_6_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => HSYNC_COUNTER_46, cout => HSYNC_COUNTER_COUT(6), clk => clk_pin_c, dataa => HSYNC_COUNTER_46, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(5), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \HSYNC_COUNTER_7_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => HSYNC_COUNTER_45, cout => HSYNC_COUNTER_COUT(7), clk => clk_pin_c, dataa => HSYNC_COUNTER_45, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(6), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \HSYNC_COUNTER_8_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => HSYNC_COUNTER_44, cout => HSYNC_COUNTER_COUT(8), clk => clk_pin_c, dataa => HSYNC_COUNTER_44, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(7), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \HSYNC_COUNTER_9_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a5a") port map ( regout => HSYNC_COUNTER_43, clk => clk_pin_c, dataa => HSYNC_COUNTER_43, datac => HSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_2_I_I, sload => UN9_HSYNC_COUNTERLT9_I, cin => HSYNC_COUNTER_COUT(8), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_0_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "6688") port map ( regout => VSYNC_COUNTER_42, cout => VSYNC_COUNTER_COUT(0), clk => clk_pin_c, dataa => VSYNC_COUNTER_42, datab => D_SET_HSYNC_COUNTER_57, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, devpor => devpor, devclrn => devclrn, datad => VCC, aclr => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \VSYNC_COUNTER_1_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => VSYNC_COUNTER_41, cout => VSYNC_COUNTER_COUT(1), clk => clk_pin_c, dataa => VSYNC_COUNTER_41, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(0), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_2_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => VSYNC_COUNTER_40, cout => VSYNC_COUNTER_COUT(2), clk => clk_pin_c, dataa => VSYNC_COUNTER_40, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(1), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_3_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => VSYNC_COUNTER_39, cout => VSYNC_COUNTER_COUT(3), clk => clk_pin_c, dataa => VSYNC_COUNTER_39, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(2), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_4_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => VSYNC_COUNTER_38, cout => VSYNC_COUNTER_COUT(4), clk => clk_pin_c, dataa => VSYNC_COUNTER_38, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(3), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_5_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => VSYNC_COUNTER_37, cout => VSYNC_COUNTER_COUT(5), clk => clk_pin_c, dataa => VSYNC_COUNTER_37, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(4), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_6_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => VSYNC_COUNTER_36, cout => VSYNC_COUNTER_COUT(6), clk => clk_pin_c, dataa => VSYNC_COUNTER_36, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(5), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_7_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => VSYNC_COUNTER_35, cout => VSYNC_COUNTER_COUT(7), clk => clk_pin_c, dataa => VSYNC_COUNTER_35, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(6), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_8_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "reg_and_comb", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5aa0") port map ( regout => VSYNC_COUNTER_34, cout => VSYNC_COUNTER_COUT(8), clk => clk_pin_c, dataa => VSYNC_COUNTER_34, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(7), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \VSYNC_COUNTER_9_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a5a") port map ( regout => VSYNC_COUNTER_33, clk => clk_pin_c, dataa => VSYNC_COUNTER_33, datac => VSYNC_COUNTER_NEXT_1_SQMUXA, sclr => G_16_I_I, sload => UN9_VSYNC_COUNTERLT9_I, cin => VSYNC_COUNTER_COUT(8), devpor => devpor, devclrn => devclrn, datab => VCC, datad => VCC, aclr => GND, ena => VCC, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_9_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "bbbb") port map ( regout => COLUMN_COUNTER_SIG_32, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9), datab => UN10_COLUMN_COUNTER_SIGLTO9, sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_8_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8080") port map ( regout => COLUMN_COUNTER_SIG_31, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8), datab => UN10_COLUMN_COUNTER_SIGLTO9, datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1, devpor => devpor, devclrn => devclrn, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_7_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8080") port map ( regout => COLUMN_COUNTER_SIG_30, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7), datab => UN10_COLUMN_COUNTER_SIGLTO9, datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1, devpor => devpor, devclrn => devclrn, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_6_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "bbbb") port map ( regout => COLUMN_COUNTER_SIG_29, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6), datab => UN10_COLUMN_COUNTER_SIGLTO9, sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_5_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "bbbb") port map ( regout => COLUMN_COUNTER_SIG_28, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5), datab => UN10_COLUMN_COUNTER_SIGLTO9, sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_4_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "bbbb") port map ( regout => COLUMN_COUNTER_SIG_27, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4), datab => UN10_COLUMN_COUNTER_SIGLTO9, sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_3_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "bbbb") port map ( regout => COLUMN_COUNTER_SIG_26, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3), datab => UN10_COLUMN_COUNTER_SIGLTO9, sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_2_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "bbbb") port map ( regout => COLUMN_COUNTER_SIG_25, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2), datab => UN10_COLUMN_COUNTER_SIGLTO9, sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_1_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "bbbb") port map ( regout => COLUMN_COUNTER_SIG_24, clk => clk_pin_c, dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1), datab => UN10_COLUMN_COUNTER_SIGLTO9, sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \COLUMN_COUNTER_SIG_0_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "7777") port map ( regout => COLUMN_COUNTER_SIG_23, clk => clk_pin_c, dataa => COLUMN_COUNTER_SIG_23, datab => UN10_COLUMN_COUNTER_SIGLTO9, sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \HSYNC_STATE_6_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff00") port map ( regout => HSYNC_STATE_22, clk => clk_pin_c, datad => UN6_DLY_COUNTER_0_X_56, devpor => devpor, devclrn => devclrn, dataa => VCC, datab => VCC, datac => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \VSYNC_STATE_0_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0cae") port map ( regout => VSYNC_STATE_15, clk => clk_pin_c, dataa => VSYNC_STATE_15, datab => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\, datac => UN6_DLY_COUNTER_0_X_56, datad => VSYNC_STATE_NEXT_2_SQMUXA, devpor => devpor, devclrn => devclrn, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \VSYNC_STATE_1_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0080") port map ( regout => VSYNC_STATE_14, clk => clk_pin_c, dataa => VSYNC_STATE_13, datab => UN12_VSYNC_COUNTER_7, datac => UN13_VSYNC_COUNTER_4, datad => UN6_DLY_COUNTER_0_X_56, devpor => devpor, devclrn => devclrn, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \VSYNC_STATE_6_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_and_comb", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7f7f") port map ( combout => UN6_DLY_COUNTER_0_X_56, regout => VSYNC_STATE_12, clk => clk_pin_c, dataa => reset_pin_c, datab => dly_counter_0, datac => dly_counter_1, devpor => devpor, devclrn => devclrn, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_8_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "dddd") port map ( regout => LINE_COUNTER_SIG_8_0, clk => clk_pin_c, dataa => UN10_LINE_COUNTER_SIGLTO8, datab => UN1_LINE_COUNTER_SIG_COMBOUT(9), sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_7_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "dddd") port map ( regout => LINE_COUNTER_SIG_7_0, clk => clk_pin_c, dataa => UN10_LINE_COUNTER_SIGLTO8, datab => UN1_LINE_COUNTER_SIG_COMBOUT(8), sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_6_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "dddd") port map ( regout => LINE_COUNTER_SIG_6_0, clk => clk_pin_c, dataa => UN10_LINE_COUNTER_SIGLTO8, datab => UN1_LINE_COUNTER_SIG_COMBOUT(7), sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_5_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8080") port map ( regout => LINE_COUNTER_SIG_5_0, clk => clk_pin_c, dataa => UN10_LINE_COUNTER_SIGLTO8, datab => UN1_LINE_COUNTER_SIG_COMBOUT(6), datac => LINE_COUNTER_NEXT_0_SQMUXA_1_1, devpor => devpor, devclrn => devclrn, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_4_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "dddd") port map ( regout => LINE_COUNTER_SIG_4_0, clk => clk_pin_c, dataa => UN10_LINE_COUNTER_SIGLTO8, datab => UN1_LINE_COUNTER_SIG_COMBOUT(5), sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_3_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "dddd") port map ( regout => LINE_COUNTER_SIG_3_0, clk => clk_pin_c, dataa => UN10_LINE_COUNTER_SIGLTO8, datab => UN1_LINE_COUNTER_SIG_COMBOUT(4), sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_2_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "dddd") port map ( regout => LINE_COUNTER_SIG_2_0, clk => clk_pin_c, dataa => UN10_LINE_COUNTER_SIGLTO8, datab => UN1_LINE_COUNTER_SIG_COMBOUT(3), sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_1_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "dddd") port map ( regout => LINE_COUNTER_SIG_1_0, clk => clk_pin_c, dataa => UN10_LINE_COUNTER_SIGLTO8, datab => UN1_LINE_COUNTER_SIG_COMBOUT(2), sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \LINE_COUNTER_SIG_0_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "bbbb") port map ( regout => LINE_COUNTER_SIG_0_0, clk => clk_pin_c, dataa => UN1_LINE_COUNTER_SIG_COMBOUT(1), datab => UN10_LINE_COUNTER_SIGLTO8, sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); V_ENABLE_SIG_Z283: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "eeee") port map ( regout => v_enable_sig, clk => clk_pin_c, dataa => HSYNC_STATE_21, datab => HSYNC_STATE_20, sclr => UN6_DLY_COUNTER_0_X_56, ena => V_ENABLE_SIG_1_0_0_0_G0_I_O4, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); H_ENABLE_SIG_Z284: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "eeee") port map ( regout => h_enable_sig, clk => clk_pin_c, dataa => VSYNC_STATE_11, datab => VSYNC_STATE_14, sclr => UN6_DLY_COUNTER_0_X_56, ena => H_ENABLE_SIG_1_0_0_0_G0_I_O4, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); H_SYNC_Z285: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff7f") port map ( regout => H_SYNC_55, clk => clk_pin_c, dataa => reset_pin_c, datab => dly_counter_0, datac => dly_counter_1, datad => H_SYNC_1_0_0_0_G1, devpor => devpor, devclrn => devclrn, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); V_SYNC_Z286: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff7f") port map ( regout => V_SYNC_54, clk => clk_pin_c, dataa => reset_pin_c, datab => dly_counter_0, datac => dly_counter_1, datad => V_SYNC_1_0_0_0_G1, devpor => devpor, devclrn => devclrn, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \VSYNC_STATE_5_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "eeee") port map ( regout => VSYNC_STATE_10, clk => clk_pin_c, dataa => VSYNC_STATE_12, datab => VSYNC_STATE_15, sclr => UN6_DLY_COUNTER_0_X_56, ena => VSYNC_STATE_NEXT_2_SQMUXA, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \VSYNC_STATE_4_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "2000") port map ( regout => VSYNC_STATE_13, clk => clk_pin_c, dataa => VSYNC_COUNTER_42, datab => VSYNC_COUNTER_33, datac => VSYNC_STATE_10, datad => UN14_VSYNC_COUNTER_8, sclr => UN6_DLY_COUNTER_0_X_56, ena => VSYNC_STATE_NEXT_2_SQMUXA, devpor => devpor, devclrn => devclrn, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \VSYNC_STATE_3_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "aaaa") port map ( regout => VSYNC_STATE_11, clk => clk_pin_c, dataa => VSYNC_STATE_14, sclr => UN6_DLY_COUNTER_0_X_56, ena => VSYNC_STATE_NEXT_2_SQMUXA, devpor => devpor, devclrn => devclrn, datab => VCC, datac => VCC, datad => VCC, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \VSYNC_STATE_2_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "8000") port map ( regout => VSYNC_STATE_9, clk => clk_pin_c, dataa => VSYNC_COUNTER_42, datab => VSYNC_COUNTER_33, datac => VSYNC_STATE_11, datad => UN14_VSYNC_COUNTER_8, sclr => UN6_DLY_COUNTER_0_X_56, ena => VSYNC_STATE_NEXT_2_SQMUXA, devpor => devpor, devclrn => devclrn, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \HSYNC_STATE_5_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "eeee") port map ( regout => HSYNC_STATE_19, clk => clk_pin_c, dataa => HSYNC_STATE_22, datab => HSYNC_STATE_18, sclr => UN6_DLY_COUNTER_0_X_56, ena => \HSYNC_STATE_3_0_0_0__G0_0\, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \HSYNC_STATE_4_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "8000") port map ( regout => HSYNC_STATE_17, clk => clk_pin_c, dataa => HSYNC_STATE_19, datab => UN10_HSYNC_COUNTER_3, datac => UN10_HSYNC_COUNTER_1, datad => UN10_HSYNC_COUNTER_4, sclr => UN6_DLY_COUNTER_0_X_56, ena => \HSYNC_STATE_3_0_0_0__G0_0\, devpor => devpor, devclrn => devclrn, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \HSYNC_STATE_3_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "aaaa") port map ( regout => HSYNC_STATE_21, clk => clk_pin_c, dataa => HSYNC_STATE_20, sclr => UN6_DLY_COUNTER_0_X_56, ena => \HSYNC_STATE_3_0_0_0__G0_0\, devpor => devpor, devclrn => devclrn, datab => VCC, datac => VCC, datad => VCC, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \HSYNC_STATE_2_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "8888") port map ( regout => HSYNC_STATE_16, clk => clk_pin_c, dataa => HSYNC_STATE_21, datab => UN12_HSYNC_COUNTER, sclr => UN6_DLY_COUNTER_0_X_56, ena => \HSYNC_STATE_3_0_0_0__G0_0\, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \HSYNC_STATE_1_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "8000") port map ( regout => HSYNC_STATE_20, clk => clk_pin_c, dataa => HSYNC_STATE_17, datab => UN11_HSYNC_COUNTER_2, datac => UN10_HSYNC_COUNTER_1, datad => UN11_HSYNC_COUNTER_3, sclr => UN6_DLY_COUNTER_0_X_56, ena => \HSYNC_STATE_3_0_0_0__G0_0\, devpor => devpor, devclrn => devclrn, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); \HSYNC_STATE_0_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "on", sum_lutc_input => "datac", lut_mask => "8888") port map ( regout => HSYNC_STATE_18, clk => clk_pin_c, dataa => HSYNC_STATE_16, datab => UN13_HSYNC_COUNTER, sclr => UN6_DLY_COUNTER_0_X_56, ena => \HSYNC_STATE_3_0_0_0__G0_0\, devpor => devpor, devclrn => devclrn, datac => VCC, datad => VCC, aclr => GND, sload => GND, cin => GND, inverta => GND, aload => GND); VSYNC_STATE_NEXT_2_SQMUXA_Z297: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "aaab") port map ( combout => VSYNC_STATE_NEXT_2_SQMUXA, dataa => UN6_DLY_COUNTER_0_X_56, datab => VSYNC_STATE_NEXT_1_SQMUXA_1, datac => VSYNC_STATE_NEXT_1_SQMUXA_3, datad => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \HSYNC_STATE_3_0_0_0__G0_0_Z298\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "f0f1") port map ( combout => \HSYNC_STATE_3_0_0_0__G0_0\, dataa => HSYNC_STATE_NEXT_1_SQMUXA_1, datab => HSYNC_STATE_NEXT_1_SQMUXA_2, datac => UN6_DLY_COUNTER_0_X_56, datad => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); UN1_HSYNC_STATE_NEXT_1_SQMUXA_0_Z299: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0ace") port map ( combout => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0, dataa => HSYNC_STATE_16, datab => HSYNC_STATE_21, datac => UN13_HSYNC_COUNTER, datad => UN12_HSYNC_COUNTER, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); UN1_VSYNC_STATE_NEXT_1_SQMUXA_0_Z300: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff2a") port map ( combout => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0, dataa => VSYNC_STATE_9, datab => UN12_VSYNC_COUNTER_6, datac => UN15_VSYNC_COUNTER_4, datad => VSYNC_STATE_NEXT_1_SQMUXA_2, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \VSYNC_STATE_3_IV_0_0__G0_0_A3_0_Z301\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8080") port map ( combout => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\, dataa => VSYNC_STATE_9, datab => UN12_VSYNC_COUNTER_6, datac => UN15_VSYNC_COUNTER_4, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO8: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff7f") port map ( combout => UN10_LINE_COUNTER_SIGLTO8, dataa => LINE_COUNTER_SIG_6_0, datab => LINE_COUNTER_SIG_7_0, datac => LINE_COUNTER_SIG_8_0, datad => UN10_LINE_COUNTER_SIGLTO5, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); G_2: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0f1f") port map ( combout => G_2_I, dataa => HSYNC_STATE_18, datab => HSYNC_STATE_22, datac => UN9_HSYNC_COUNTERLT9, datad => UN6_DLY_COUNTER_0_X_56, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_STATE_NEXT_1_SQMUXA_1_Z304: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "d0f0") port map ( combout => VSYNC_STATE_NEXT_1_SQMUXA_1, dataa => VSYNC_COUNTER_42, datab => VSYNC_COUNTER_33, datac => VSYNC_STATE_10, datad => UN14_VSYNC_COUNTER_8, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_STATE_NEXT_1_SQMUXA_2_Z305: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "2a2a") port map ( combout => VSYNC_STATE_NEXT_1_SQMUXA_2, dataa => VSYNC_STATE_13, datab => UN12_VSYNC_COUNTER_7, datac => UN13_VSYNC_COUNTER_4, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_STATE_NEXT_1_SQMUXA_3_Z306: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "70f0") port map ( combout => VSYNC_STATE_NEXT_1_SQMUXA_3, dataa => VSYNC_COUNTER_42, datab => VSYNC_COUNTER_33, datac => VSYNC_STATE_11, datad => UN14_VSYNC_COUNTER_8, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); G_16: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0f1f") port map ( combout => G_16_I, dataa => VSYNC_STATE_15, datab => VSYNC_STATE_12, datac => UN9_VSYNC_COUNTERLT9, datad => UN6_DLY_COUNTER_0_X_56, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLTO9: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "1f0f") port map ( combout => UN10_COLUMN_COUNTER_SIGLTO9, dataa => COLUMN_COUNTER_SIG_30, datab => COLUMN_COUNTER_SIG_31, datac => COLUMN_COUNTER_SIG_32, datad => UN10_COLUMN_COUNTER_SIGLT6, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_STATE_NEXT_1_SQMUXA_2_Z309: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "2aaa") port map ( combout => HSYNC_STATE_NEXT_1_SQMUXA_2, dataa => HSYNC_STATE_17, datab => UN11_HSYNC_COUNTER_2, datac => UN10_HSYNC_COUNTER_1, datad => UN11_HSYNC_COUNTER_3, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_STATE_NEXT_1_SQMUXA_1_Z310: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "2aaa") port map ( combout => HSYNC_STATE_NEXT_1_SQMUXA_1, dataa => HSYNC_STATE_19, datab => UN10_HSYNC_COUNTER_3, datac => UN10_HSYNC_COUNTER_1, datad => UN10_HSYNC_COUNTER_4, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "1000") port map ( combout => UN13_HSYNC_COUNTER, dataa => HSYNC_COUNTER_46, datab => HSYNC_COUNTER_45, datac => UN13_HSYNC_COUNTER_2, datad => UN13_HSYNC_COUNTER_7, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "f7ff") port map ( combout => UN9_HSYNC_COUNTERLT9, dataa => HSYNC_COUNTER_44, datab => HSYNC_COUNTER_43, datac => UN9_HSYNC_COUNTERLT9_3, datad => UN13_HSYNC_COUNTER_7, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "fff7") port map ( combout => UN9_VSYNC_COUNTERLT9, dataa => VSYNC_COUNTER_38, datab => VSYNC_COUNTER_37, datac => UN9_VSYNC_COUNTERLT9_5, datad => UN9_VSYNC_COUNTERLT9_6, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8000") port map ( combout => UN12_HSYNC_COUNTER, dataa => HSYNC_COUNTER_52, datab => HSYNC_COUNTER_51, datac => UN12_HSYNC_COUNTER_3, datad => UN12_HSYNC_COUNTER_4, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO5: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0f07") port map ( combout => UN10_LINE_COUNTER_SIGLTO5, dataa => LINE_COUNTER_SIG_1_0, datab => LINE_COUNTER_SIG_2_0, datac => LINE_COUNTER_SIG_5_0, datad => UN10_LINE_COUNTER_SIGLT4_2, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_4: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "1010") port map ( combout => UN15_VSYNC_COUNTER_4, dataa => VSYNC_COUNTER_41, datab => VSYNC_COUNTER_38, datac => UN15_VSYNC_COUNTER_3, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_4: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8080") port map ( combout => UN13_VSYNC_COUNTER_4, dataa => VSYNC_COUNTER_42, datab => VSYNC_COUNTER_37, datac => UN13_VSYNC_COUNTER_3, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ff7f") port map ( combout => UN10_COLUMN_COUNTER_SIGLT6, dataa => COLUMN_COUNTER_SIG_27, datab => COLUMN_COUNTER_SIG_29, datac => COLUMN_COUNTER_SIG_28, datad => UN10_COLUMN_COUNTER_SIGLT6_4, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_COUNTER_NEXT_1_SQMUXA_Z319: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0080") port map ( combout => HSYNC_COUNTER_NEXT_1_SQMUXA, dataa => reset_pin_c, datab => dly_counter_0, datac => dly_counter_1, datad => D_SET_HSYNC_COUNTER_57, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_FSM_NEXT_UN14_VSYNC_COUNTER_8: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8888") port map ( combout => UN14_VSYNC_COUNTER_8, dataa => UN12_VSYNC_COUNTER_6, datab => UN12_VSYNC_COUNTER_7, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); LINE_COUNTER_NEXT_0_SQMUXA_1_1_Z321: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0080") port map ( combout => LINE_COUNTER_NEXT_0_SQMUXA_1_1, dataa => reset_pin_c, datab => dly_counter_0, datac => dly_counter_1, datad => VSYNC_STATE_14, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); V_SYNC_1_0_0_0_G1_Z322: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ccd8") port map ( combout => V_SYNC_1_0_0_0_G1, dataa => VSYNC_STATE_9, datab => V_SYNC_54, datac => VSYNC_STATE_13, datad => UN1_VSYNC_STATE_2_0, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); H_ENABLE_SIG_1_0_0_0_G0_I_O4_Z323: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "f1f1") port map ( combout => H_ENABLE_SIG_1_0_0_0_G0_I_O4, dataa => VSYNC_STATE_13, datab => VSYNC_STATE_10, datac => UN6_DLY_COUNTER_0_X_56, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_COUNTER_NEXT_1_SQMUXA_Z324: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0080") port map ( combout => VSYNC_COUNTER_NEXT_1_SQMUXA, dataa => reset_pin_c, datab => dly_counter_0, datac => dly_counter_1, datad => D_SET_VSYNC_COUNTER_53, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); V_ENABLE_SIG_1_0_0_0_G0_I_O4_Z325: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "f1f1") port map ( combout => V_ENABLE_SIG_1_0_0_0_G0_I_O4, dataa => HSYNC_STATE_17, datab => HSYNC_STATE_19, datac => UN6_DLY_COUNTER_0_X_56, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); H_SYNC_1_0_0_0_G1_Z326: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "ccd8") port map ( combout => H_SYNC_1_0_0_0_G1, dataa => HSYNC_STATE_16, datab => H_SYNC_55, datac => HSYNC_STATE_17, datad => UN1_HSYNC_STATE_3_0, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_Z327: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0080") port map ( combout => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1, dataa => reset_pin_c, datab => dly_counter_0, datac => dly_counter_1, datad => HSYNC_STATE_20, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_4: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0010") port map ( combout => UN12_HSYNC_COUNTER_4, dataa => HSYNC_COUNTER_46, datab => HSYNC_COUNTER_45, datac => HSYNC_COUNTER_43, datad => HSYNC_COUNTER_49, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_3: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0008") port map ( combout => UN12_HSYNC_COUNTER_3, dataa => HSYNC_COUNTER_50, datab => HSYNC_COUNTER_44, datac => HSYNC_COUNTER_48, datad => HSYNC_COUNTER_47, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_3: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0008") port map ( combout => UN11_HSYNC_COUNTER_3, dataa => HSYNC_COUNTER_52, datab => HSYNC_COUNTER_51, datac => HSYNC_COUNTER_49, datad => HSYNC_COUNTER_48, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_2: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0808") port map ( combout => UN11_HSYNC_COUNTER_2, dataa => HSYNC_COUNTER_50, datab => HSYNC_COUNTER_45, datac => HSYNC_COUNTER_46, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9_3: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7fff") port map ( combout => UN9_HSYNC_COUNTERLT9_3, dataa => HSYNC_COUNTER_46, datab => HSYNC_COUNTER_45, datac => HSYNC_COUNTER_48, datad => HSYNC_COUNTER_47, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_2: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0080") port map ( combout => UN13_HSYNC_COUNTER_2, dataa => HSYNC_COUNTER_44, datab => HSYNC_COUNTER_43, datac => HSYNC_COUNTER_48, datad => HSYNC_COUNTER_47, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_6: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7fff") port map ( combout => UN9_VSYNC_COUNTERLT9_6, dataa => VSYNC_COUNTER_40, datab => VSYNC_COUNTER_39, datac => VSYNC_COUNTER_42, datad => VSYNC_COUNTER_41, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_5: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7fff") port map ( combout => UN9_VSYNC_COUNTERLT9_5, dataa => VSYNC_COUNTER_34, datab => VSYNC_COUNTER_33, datac => VSYNC_COUNTER_36, datad => VSYNC_COUNTER_35, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_4: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8000") port map ( combout => UN10_HSYNC_COUNTER_4, dataa => HSYNC_COUNTER_48, datab => HSYNC_COUNTER_46, datac => HSYNC_COUNTER_51, datad => HSYNC_COUNTER_49, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_3: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0101") port map ( combout => UN10_HSYNC_COUNTER_3, dataa => HSYNC_COUNTER_52, datab => HSYNC_COUNTER_45, datac => HSYNC_COUNTER_50, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_3: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0020") port map ( combout => UN15_VSYNC_COUNTER_3, dataa => VSYNC_COUNTER_33, datab => VSYNC_COUNTER_40, datac => VSYNC_COUNTER_39, datad => VSYNC_COUNTER_42, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_3: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0001") port map ( combout => UN13_VSYNC_COUNTER_3, dataa => VSYNC_COUNTER_36, datab => VSYNC_COUNTER_35, datac => VSYNC_COUNTER_34, datad => VSYNC_COUNTER_33, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6_4: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7fff") port map ( combout => UN10_COLUMN_COUNTER_SIGLT6_4, dataa => COLUMN_COUNTER_SIG_25, datab => COLUMN_COUNTER_SIG_26, datac => COLUMN_COUNTER_SIG_23, datad => COLUMN_COUNTER_SIG_24, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLT4_2: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "7f7f") port map ( combout => UN10_LINE_COUNTER_SIGLT4_2, dataa => LINE_COUNTER_SIG_3_0, datab => LINE_COUNTER_SIG_4_0, datac => LINE_COUNTER_SIG_0_0, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_1: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0101") port map ( combout => UN10_HSYNC_COUNTER_1, dataa => HSYNC_COUNTER_47, datab => HSYNC_COUNTER_44, datac => HSYNC_COUNTER_43, devpor => devpor, devclrn => devclrn, clk => GND, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_6: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0001") port map ( combout => UN12_VSYNC_COUNTER_6, dataa => VSYNC_COUNTER_35, datab => VSYNC_COUNTER_34, datac => VSYNC_COUNTER_37, datad => VSYNC_COUNTER_36, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_7: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0001") port map ( combout => UN12_VSYNC_COUNTER_7, dataa => VSYNC_COUNTER_39, datab => VSYNC_COUNTER_38, datac => VSYNC_COUNTER_41, datad => VSYNC_COUNTER_40, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_7: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "8000") port map ( combout => UN13_HSYNC_COUNTER_7, dataa => HSYNC_COUNTER_50, datab => HSYNC_COUNTER_49, datac => HSYNC_COUNTER_52, datad => HSYNC_COUNTER_51, devpor => devpor, devclrn => devclrn, clk => GND, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); UN1_HSYNC_STATE_3_0_Z346: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "eeee") port map ( combout => UN1_HSYNC_STATE_3_0, dataa => HSYNC_STATE_21, datab => HSYNC_STATE_20, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); UN1_VSYNC_STATE_2_0_Z347: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "eeee") port map ( combout => UN1_VSYNC_STATE_2_0, dataa => VSYNC_STATE_11, datab => VSYNC_STATE_14, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); D_SET_HSYNC_COUNTER_Z348: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "eeee") port map ( combout => D_SET_HSYNC_COUNTER_57, dataa => HSYNC_STATE_22, datab => HSYNC_STATE_18, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); D_SET_VSYNC_COUNTER_Z349: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "eeee") port map ( combout => D_SET_VSYNC_COUNTER_53, dataa => VSYNC_STATE_12, datab => VSYNC_STATE_15, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_9_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c6c") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(9), dataa => LINE_COUNTER_SIG_7_0, datab => LINE_COUNTER_SIG_8_0, cin => UN1_LINE_COUNTER_SIG_COUT(7), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_8_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a5a") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(8), dataa => LINE_COUNTER_SIG_7_0, cin => UN1_LINE_COUNTER_SIG_COUT(6), devpor => devpor, devclrn => devclrn, clk => GND, datab => VCC, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_7_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(7), cout => UN1_LINE_COUNTER_SIG_COUT(7), dataa => LINE_COUNTER_SIG_5_0, datab => LINE_COUNTER_SIG_6_0, cin => UN1_LINE_COUNTER_SIG_COUT(5), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_6_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(6), cout => UN1_LINE_COUNTER_SIG_COUT(6), dataa => LINE_COUNTER_SIG_5_0, datab => LINE_COUNTER_SIG_6_0, cin => UN1_LINE_COUNTER_SIG_COUT(4), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_5_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(5), cout => UN1_LINE_COUNTER_SIG_COUT(5), dataa => LINE_COUNTER_SIG_3_0, datab => LINE_COUNTER_SIG_4_0, cin => UN1_LINE_COUNTER_SIG_COUT(3), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_4_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(4), cout => UN1_LINE_COUNTER_SIG_COUT(4), dataa => LINE_COUNTER_SIG_3_0, datab => LINE_COUNTER_SIG_4_0, cin => UN1_LINE_COUNTER_SIG_COUT(2), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_3_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(3), cout => UN1_LINE_COUNTER_SIG_COUT(3), dataa => LINE_COUNTER_SIG_1_0, datab => LINE_COUNTER_SIG_2_0, cin => UN1_LINE_COUNTER_SIG_COUT(1), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_2_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(2), cout => UN1_LINE_COUNTER_SIG_COUT(2), dataa => LINE_COUNTER_SIG_1_0, datab => LINE_COUNTER_SIG_2_0, cin => UN1_LINE_COUNTER_SIG_A_COUT(1), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_A_1_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "0088") port map ( cout => UN1_LINE_COUNTER_SIG_A_COUT(1), dataa => D_SET_HSYNC_COUNTER_57, datab => LINE_COUNTER_SIG_0_0, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \UN1_LINE_COUNTER_SIG_1_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "6688") port map ( combout => UN1_LINE_COUNTER_SIG_COMBOUT(1), cout => UN1_LINE_COUNTER_SIG_COUT(1), dataa => D_SET_HSYNC_COUNTER_57, datab => LINE_COUNTER_SIG_0_0, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_9_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c6c") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9), dataa => COLUMN_COUNTER_SIG_31, datab => COLUMN_COUNTER_SIG_32, cin => UN2_COLUMN_COUNTER_NEXT_COUT(7), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_8_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a5a") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8), dataa => COLUMN_COUNTER_SIG_31, cin => UN2_COLUMN_COUNTER_NEXT_COUT(6), devpor => devpor, devclrn => devclrn, clk => GND, datab => VCC, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_7_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7), cout => UN2_COLUMN_COUNTER_NEXT_COUT(7), dataa => COLUMN_COUNTER_SIG_29, datab => COLUMN_COUNTER_SIG_30, cin => UN2_COLUMN_COUNTER_NEXT_COUT(5), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_6_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6), cout => UN2_COLUMN_COUNTER_NEXT_COUT(6), dataa => COLUMN_COUNTER_SIG_29, datab => COLUMN_COUNTER_SIG_30, cin => UN2_COLUMN_COUNTER_NEXT_COUT(4), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_5_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5), cout => UN2_COLUMN_COUNTER_NEXT_COUT(5), dataa => COLUMN_COUNTER_SIG_27, datab => COLUMN_COUNTER_SIG_28, cin => UN2_COLUMN_COUNTER_NEXT_COUT(3), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_4_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4), cout => UN2_COLUMN_COUNTER_NEXT_COUT(4), dataa => COLUMN_COUNTER_SIG_27, datab => COLUMN_COUNTER_SIG_28, cin => UN2_COLUMN_COUNTER_NEXT_COUT(2), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_3_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "6c80") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3), cout => UN2_COLUMN_COUNTER_NEXT_COUT(3), dataa => COLUMN_COUNTER_SIG_25, datab => COLUMN_COUNTER_SIG_26, cin => UN2_COLUMN_COUNTER_NEXT_COUT(1), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_2_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "cin", cin_used => "true", lut_mask => "5a80") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2), cout => UN2_COLUMN_COUNTER_NEXT_COUT(2), dataa => COLUMN_COUNTER_SIG_25, datab => COLUMN_COUNTER_SIG_26, cin => UN2_COLUMN_COUNTER_NEXT_COUT(0), devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_1_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "6688") port map ( combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1), cout => UN2_COLUMN_COUNTER_NEXT_COUT(1), dataa => COLUMN_COUNTER_SIG_23, datab => COLUMN_COUNTER_SIG_24, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \UN2_COLUMN_COUNTER_NEXT_0_\: stratix_lcell generic map ( operation_mode => "arithmetic", output_mode => "comb_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "5588") port map ( cout => UN2_COLUMN_COUNTER_NEXT_COUT(0), dataa => COLUMN_COUNTER_SIG_23, datab => COLUMN_COUNTER_SIG_24, devpor => devpor, devclrn => devclrn, clk => GND, datac => VCC, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); VCC <= '1'; GND <= '0'; LINE_COUNTER_NEXT_0_SQMUXA_1_1_I <= not LINE_COUNTER_NEXT_0_SQMUXA_1_1; COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I <= not COLUMN_COUNTER_NEXT_0_SQMUXA_1_1; G_16_I_I <= not G_16_I; UN9_VSYNC_COUNTERLT9_I <= not UN9_VSYNC_COUNTERLT9; G_2_I_I <= not G_2_I; UN9_HSYNC_COUNTERLT9_I <= not UN9_HSYNC_COUNTERLT9; line_counter_sig_0 <= LINE_COUNTER_SIG_0_0; line_counter_sig_1 <= LINE_COUNTER_SIG_1_0; line_counter_sig_2 <= LINE_COUNTER_SIG_2_0; line_counter_sig_3 <= LINE_COUNTER_SIG_3_0; line_counter_sig_4 <= LINE_COUNTER_SIG_4_0; line_counter_sig_5 <= LINE_COUNTER_SIG_5_0; line_counter_sig_6 <= LINE_COUNTER_SIG_6_0; line_counter_sig_7 <= LINE_COUNTER_SIG_7_0; line_counter_sig_8 <= LINE_COUNTER_SIG_8_0; vsync_state_2 <= VSYNC_STATE_9; vsync_state_5 <= VSYNC_STATE_10; vsync_state_3 <= VSYNC_STATE_11; vsync_state_6 <= VSYNC_STATE_12; vsync_state_4 <= VSYNC_STATE_13; vsync_state_1 <= VSYNC_STATE_14; vsync_state_0 <= VSYNC_STATE_15; hsync_state_2 <= HSYNC_STATE_16; hsync_state_4 <= HSYNC_STATE_17; hsync_state_0 <= HSYNC_STATE_18; hsync_state_5 <= HSYNC_STATE_19; hsync_state_1 <= HSYNC_STATE_20; hsync_state_3 <= HSYNC_STATE_21; hsync_state_6 <= HSYNC_STATE_22; column_counter_sig_0 <= COLUMN_COUNTER_SIG_23; column_counter_sig_1 <= COLUMN_COUNTER_SIG_24; column_counter_sig_2 <= COLUMN_COUNTER_SIG_25; column_counter_sig_3 <= COLUMN_COUNTER_SIG_26; column_counter_sig_4 <= COLUMN_COUNTER_SIG_27; column_counter_sig_5 <= COLUMN_COUNTER_SIG_28; column_counter_sig_6 <= COLUMN_COUNTER_SIG_29; column_counter_sig_7 <= COLUMN_COUNTER_SIG_30; column_counter_sig_8 <= COLUMN_COUNTER_SIG_31; column_counter_sig_9 <= COLUMN_COUNTER_SIG_32; vsync_counter_9 <= VSYNC_COUNTER_33; vsync_counter_8 <= VSYNC_COUNTER_34; vsync_counter_7 <= VSYNC_COUNTER_35; vsync_counter_6 <= VSYNC_COUNTER_36; vsync_counter_5 <= VSYNC_COUNTER_37; vsync_counter_4 <= VSYNC_COUNTER_38; vsync_counter_3 <= VSYNC_COUNTER_39; vsync_counter_2 <= VSYNC_COUNTER_40; vsync_counter_1 <= VSYNC_COUNTER_41; vsync_counter_0 <= VSYNC_COUNTER_42; hsync_counter_9 <= HSYNC_COUNTER_43; hsync_counter_8 <= HSYNC_COUNTER_44; hsync_counter_7 <= HSYNC_COUNTER_45; hsync_counter_6 <= HSYNC_COUNTER_46; hsync_counter_5 <= HSYNC_COUNTER_47; hsync_counter_4 <= HSYNC_COUNTER_48; hsync_counter_3 <= HSYNC_COUNTER_49; hsync_counter_2 <= HSYNC_COUNTER_50; hsync_counter_1 <= HSYNC_COUNTER_51; hsync_counter_0 <= HSYNC_COUNTER_52; d_set_vsync_counter <= D_SET_VSYNC_COUNTER_53; v_sync <= V_SYNC_54; h_sync <= H_SYNC_55; un6_dly_counter_0_x <= UN6_DLY_COUNTER_0_X_56; d_set_hsync_counter <= D_SET_HSYNC_COUNTER_57; end beh; -- library ieee, stratix; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; use stratix.stratix_components.all; entity vga is port( clk_pin : in std_logic; reset_pin : in std_logic; r0_pin : out std_logic; r1_pin : out std_logic; r2_pin : out std_logic; g0_pin : out std_logic; g1_pin : out std_logic; g2_pin : out std_logic; b0_pin : out std_logic; b1_pin : out std_logic; hsync_pin : out std_logic; vsync_pin : out std_logic; seven_seg_pin : out std_logic_vector(13 downto 0); d_hsync : out std_logic; d_vsync : out std_logic; d_column_counter : out std_logic_vector(9 downto 0); d_line_counter : out std_logic_vector(8 downto 0); d_set_column_counter : out std_logic; d_set_line_counter : out std_logic; d_hsync_counter : out std_logic_vector(9 downto 0); d_vsync_counter : out std_logic_vector(9 downto 0); d_set_hsync_counter : out std_logic; d_set_vsync_counter : out std_logic; d_h_enable : out std_logic; d_v_enable : out std_logic; d_r : out std_logic; d_g : out std_logic; d_b : out std_logic; d_hsync_state : out std_logic_vector(0 to 6); d_vsync_state : out std_logic_vector(0 to 6); d_state_clk : out std_logic; d_toggle : out std_logic; d_toggle_counter : out std_logic_vector(24 downto 0)); end vga; architecture beh of vga is signal devclrn : std_logic := '1'; signal devpor : std_logic := '1'; signal devoe : std_logic := '0'; signal DLY_COUNTER : std_logic_vector(1 downto 0); signal \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\ : std_logic_vector(9 downto 0); signal \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\ : std_logic_vector(8 downto 0); signal \VGA_DRIVER_UNIT.HSYNC_COUNTER\ : std_logic_vector(9 downto 0); signal \VGA_DRIVER_UNIT.VSYNC_COUNTER\ : std_logic_vector(9 downto 0); signal \VGA_DRIVER_UNIT.HSYNC_STATE\ : std_logic_vector(6 downto 0); signal \VGA_DRIVER_UNIT.VSYNC_STATE\ : std_logic_vector(6 downto 0); signal \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\ : std_logic_vector(24 downto 0); signal SEVEN_SEG_PINZ : std_logic_vector(13 downto 0); signal D_COLUMN_COUNTERZ : std_logic_vector(9 downto 0); signal D_LINE_COUNTERZ : std_logic_vector(8 downto 0); signal D_HSYNC_COUNTERZ : std_logic_vector(9 downto 0); signal D_VSYNC_COUNTERZ : std_logic_vector(9 downto 0); signal D_HSYNC_STATEZ : std_logic_vector(6 downto 0); signal D_VSYNC_STATEZ : std_logic_vector(6 downto 0); signal D_TOGGLE_COUNTERZ : std_logic_vector(24 downto 0); signal VCC : std_logic ; signal GND : std_logic ; signal \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\ : std_logic ; signal \VGA_DRIVER_UNIT.H_SYNC\ : std_logic ; signal \VGA_DRIVER_UNIT.V_SYNC\ : std_logic ; signal \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\ : std_logic ; signal \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\ : std_logic ; signal \VGA_DRIVER_UNIT.H_ENABLE_SIG\ : std_logic ; signal \VGA_DRIVER_UNIT.V_ENABLE_SIG\ : std_logic ; signal \VGA_CONTROL_UNIT.R\ : std_logic ; signal \VGA_CONTROL_UNIT.G\ : std_logic ; signal \VGA_CONTROL_UNIT.B\ : std_logic ; signal G_33 : std_logic ; signal \VGA_CONTROL_UNIT.TOGGLE_SIG\ : std_logic ; signal CLK_PIN_C : std_logic ; signal RESET_PIN_C : std_logic ; signal CLK_PIN_INTERNAL : std_logic ; signal RESET_PIN_INTERNAL : std_logic ; signal N_1 : std_logic ; signal N_2 : std_logic ; signal N_84_0 : std_logic ; signal N_85_0 : std_logic ; signal N_86_0 : std_logic ; signal N_87_0 : std_logic ; signal N_88_0 : std_logic ; signal N_89_0 : std_logic ; signal N_90_0 : std_logic ; signal N_91_0 : std_logic ; signal N_92_0 : std_logic ; signal N_93_0 : std_logic ; signal N_94_0 : std_logic ; signal N_95_0 : std_logic ; signal N_96_0 : std_logic ; signal N_97_0 : std_logic ; signal N_98_0 : std_logic ; signal N_99_0 : std_logic ; signal N_100_0 : std_logic ; signal N_101_0 : std_logic ; signal N_102_0 : std_logic ; signal N_103_0 : std_logic ; signal N_104_0 : std_logic ; signal N_105_0 : std_logic ; signal N_106_0 : std_logic ; signal N_107_0 : std_logic ; signal N_108_0 : std_logic ; signal N_109_0 : std_logic ; signal N_110_0 : std_logic ; signal N_111_0 : std_logic ; signal N_112_0 : std_logic ; signal N_113_0 : std_logic ; signal N_114_0 : std_logic ; signal N_115_0 : std_logic ; signal N_116_0 : std_logic ; signal N_117_0 : std_logic ; signal N_118 : std_logic ; signal N_119 : std_logic ; signal N_120 : std_logic ; signal N_121 : std_logic ; signal N_122 : std_logic ; signal N_123 : std_logic ; signal N_124 : std_logic ; signal N_125 : std_logic ; signal N_126 : std_logic ; signal N_127 : std_logic ; signal N_128 : std_logic ; signal N_129 : std_logic ; signal N_130 : std_logic ; signal N_131 : std_logic ; signal N_132 : std_logic ; signal N_133 : std_logic ; signal N_134 : std_logic ; signal N_135 : std_logic ; signal N_136 : std_logic ; signal N_137 : std_logic ; signal N_138 : std_logic ; signal N_139 : std_logic ; signal N_140 : std_logic ; signal N_141 : std_logic ; signal N_142 : std_logic ; signal N_143 : std_logic ; signal N_144 : std_logic ; signal N_145 : std_logic ; signal N_146 : std_logic ; signal N_147 : std_logic ; signal N_148 : std_logic ; signal N_149 : std_logic ; signal N_150 : std_logic ; signal N_151 : std_logic ; signal N_152 : std_logic ; signal N_153 : std_logic ; signal N_154 : std_logic ; signal N_155 : std_logic ; signal N_156 : std_logic ; signal N_157 : std_logic ; signal N_158 : std_logic ; signal N_159 : std_logic ; signal N_160 : std_logic ; signal N_161 : std_logic ; signal N_162 : std_logic ; signal N_163 : std_logic ; signal N_164 : std_logic ; signal N_165 : std_logic ; signal N_166 : std_logic ; signal N_167 : std_logic ; signal N_168 : std_logic ; signal N_169 : std_logic ; signal N_170 : std_logic ; signal N_171 : std_logic ; signal N_172 : std_logic ; signal N_173 : std_logic ; signal N_174 : std_logic ; signal N_175 : std_logic ; signal N_176 : std_logic ; signal N_177 : std_logic ; signal N_178 : std_logic ; signal N_179 : std_logic ; signal N_180 : std_logic ; signal N_181 : std_logic ; signal N_182 : std_logic ; signal N_183 : std_logic ; signal N_184 : std_logic ; signal N_185 : std_logic ; signal N_186 : std_logic ; signal N_187 : std_logic ; signal N_188 : std_logic ; signal N_189 : std_logic ; signal N_190 : std_logic ; signal N_191 : std_logic ; signal N_192 : std_logic ; signal N_193 : std_logic ; signal N_194 : std_logic ; signal N_195 : std_logic ; signal N_196 : std_logic ; signal N_197 : std_logic ; signal N_198 : std_logic ; signal R0_PINZ : std_logic ; signal R1_PINZ : std_logic ; signal R2_PINZ : std_logic ; signal G0_PINZ : std_logic ; signal G1_PINZ : std_logic ; signal G2_PINZ : std_logic ; signal B0_PINZ : std_logic ; signal B1_PINZ : std_logic ; signal HSYNC_PINZ : std_logic ; signal VSYNC_PINZ : std_logic ; signal D_HSYNCZ : std_logic ; signal D_VSYNCZ : std_logic ; signal D_SET_COLUMN_COUNTERZ : std_logic ; signal D_SET_LINE_COUNTERZ : std_logic ; signal D_SET_HSYNC_COUNTERZ : std_logic ; signal D_SET_VSYNC_COUNTERZ : std_logic ; signal D_H_ENABLEZ : std_logic ; signal D_V_ENABLEZ : std_logic ; signal D_RZ : std_logic ; signal D_GZ : std_logic ; signal D_BZ : std_logic ; signal D_STATE_CLKZ : std_logic ; signal D_TOGGLEZ : std_logic ; component vga_driver port( line_counter_sig_0 : out std_logic; line_counter_sig_1 : out std_logic; line_counter_sig_2 : out std_logic; line_counter_sig_3 : out std_logic; line_counter_sig_4 : out std_logic; line_counter_sig_5 : out std_logic; line_counter_sig_6 : out std_logic; line_counter_sig_7 : out std_logic; line_counter_sig_8 : out std_logic; dly_counter_1 : in std_logic; dly_counter_0 : in std_logic; vsync_state_2 : out std_logic; vsync_state_5 : out std_logic; vsync_state_3 : out std_logic; vsync_state_6 : out std_logic; vsync_state_4 : out std_logic; vsync_state_1 : out std_logic; vsync_state_0 : out std_logic; hsync_state_2 : out std_logic; hsync_state_4 : out std_logic; hsync_state_0 : out std_logic; hsync_state_5 : out std_logic; hsync_state_1 : out std_logic; hsync_state_3 : out std_logic; hsync_state_6 : out std_logic; column_counter_sig_0 : out std_logic; column_counter_sig_1 : out std_logic; column_counter_sig_2 : out std_logic; column_counter_sig_3 : out std_logic; column_counter_sig_4 : out std_logic; column_counter_sig_5 : out std_logic; column_counter_sig_6 : out std_logic; column_counter_sig_7 : out std_logic; column_counter_sig_8 : out std_logic; column_counter_sig_9 : out std_logic; vsync_counter_9 : out std_logic; vsync_counter_8 : out std_logic; vsync_counter_7 : out std_logic; vsync_counter_6 : out std_logic; vsync_counter_5 : out std_logic; vsync_counter_4 : out std_logic; vsync_counter_3 : out std_logic; vsync_counter_2 : out std_logic; vsync_counter_1 : out std_logic; vsync_counter_0 : out std_logic; hsync_counter_9 : out std_logic; hsync_counter_8 : out std_logic; hsync_counter_7 : out std_logic; hsync_counter_6 : out std_logic; hsync_counter_5 : out std_logic; hsync_counter_4 : out std_logic; hsync_counter_3 : out std_logic; hsync_counter_2 : out std_logic; hsync_counter_1 : out std_logic; hsync_counter_0 : out std_logic; d_set_vsync_counter : out std_logic; v_sync : out std_logic; h_sync : out std_logic; h_enable_sig : out std_logic; v_enable_sig : out std_logic; reset_pin_c : in std_logic; un6_dly_counter_0_x : out std_logic; d_set_hsync_counter : out std_logic; clk_pin_c : in std_logic ); end component; component vga_control port( line_counter_sig_0 : in std_logic; line_counter_sig_2 : in std_logic; line_counter_sig_1 : in std_logic; line_counter_sig_3 : in std_logic; line_counter_sig_6 : in std_logic; line_counter_sig_5 : in std_logic; line_counter_sig_4 : in std_logic; line_counter_sig_7 : in std_logic; line_counter_sig_8 : in std_logic; column_counter_sig_0 : in std_logic; column_counter_sig_1 : in std_logic; column_counter_sig_2 : in std_logic; column_counter_sig_8 : in std_logic; column_counter_sig_3 : in std_logic; column_counter_sig_5 : in std_logic; column_counter_sig_4 : in std_logic; column_counter_sig_9 : in std_logic; column_counter_sig_7 : in std_logic; column_counter_sig_6 : in std_logic; toggle_counter_sig_0 : out std_logic; toggle_counter_sig_1 : out std_logic; toggle_counter_sig_2 : out std_logic; toggle_counter_sig_3 : out std_logic; toggle_counter_sig_4 : out std_logic; toggle_counter_sig_5 : out std_logic; toggle_counter_sig_6 : out std_logic; toggle_counter_sig_7 : out std_logic; toggle_counter_sig_8 : out std_logic; toggle_counter_sig_9 : out std_logic; toggle_counter_sig_10 : out std_logic; toggle_counter_sig_11 : out std_logic; toggle_counter_sig_12 : out std_logic; toggle_counter_sig_13 : out std_logic; toggle_counter_sig_14 : out std_logic; toggle_counter_sig_15 : out std_logic; toggle_counter_sig_16 : out std_logic; toggle_counter_sig_17 : out std_logic; toggle_counter_sig_18 : out std_logic; toggle_counter_sig_19 : out std_logic; toggle_counter_sig_20 : out std_logic; toggle_counter_sig_21 : out std_logic; toggle_counter_sig_22 : out std_logic; toggle_counter_sig_23 : out std_logic; toggle_counter_sig_24 : out std_logic; h_enable_sig : in std_logic; g : out std_logic; b : out std_logic; v_enable_sig : in std_logic; r : out std_logic; toggle_sig : out std_logic; un6_dly_counter_0_x : in std_logic; clk_pin_c : in std_logic ); end component; begin VCC <= '1'; GND <= '0'; \DLY_COUNTER_1_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "a8a8") port map ( regout => DLY_COUNTER(1), clk => CLK_PIN_C, dataa => RESET_PIN_C, datab => DLY_COUNTER(0), datac => DLY_COUNTER(1), devpor => devpor, devclrn => devclrn, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); \DLY_COUNTER_0_\: stratix_lcell generic map ( operation_mode => "normal", output_mode => "reg_only", synch_mode => "off", sum_lutc_input => "datac", lut_mask => "a2a2") port map ( regout => DLY_COUNTER(0), clk => CLK_PIN_C, dataa => RESET_PIN_C, datab => DLY_COUNTER(0), datac => DLY_COUNTER(1), devpor => devpor, devclrn => devclrn, datad => VCC, aclr => GND, sclr => GND, sload => GND, ena => VCC, cin => GND, inverta => GND, aload => GND); RESET_PIN_IN: stratix_io generic map ( operation_mode => "input" ) port map ( padio => N_2, combout => RESET_PIN_C, oe => GND, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); CLK_PIN_IN: stratix_io generic map ( operation_mode => "input" ) port map ( padio => N_1, combout => CLK_PIN_C, oe => GND, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_24_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(24), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_23_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(23), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_22_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(22), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_21_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(21), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_20_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(20), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_19_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(19), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_18_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(18), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_17_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(17), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_16_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(16), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_15_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(15), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_14_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(14), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_13_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(13), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_12_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(12), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_11_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(11), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_10_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(10), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_9_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(9), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_8_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(8), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_7_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(7), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_6_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(6), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_5_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(5), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_4_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(4), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_3_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(3), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_2_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(2), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_1_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(1), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_TOGGLE_COUNTER_OUT_0_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLE_COUNTERZ(0), datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_TOGGLE_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_TOGGLEZ, datain => \VGA_CONTROL_UNIT.TOGGLE_SIG\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_STATE_CLK_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_STATE_CLKZ, datain => G_33, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_STATE_OUT_0_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_STATEZ(0), datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(0), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_STATE_OUT_1_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_STATEZ(1), datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_STATE_OUT_2_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_STATEZ(2), datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(2), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_STATE_OUT_3_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_STATEZ(3), datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(3), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_STATE_OUT_4_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_STATEZ(4), datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(4), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_STATE_OUT_5_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_STATEZ(5), datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(5), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_STATE_OUT_6_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_STATEZ(6), datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(6), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_STATE_OUT_0_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_STATEZ(0), datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(0), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_STATE_OUT_1_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_STATEZ(1), datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_STATE_OUT_2_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_STATEZ(2), datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(2), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_STATE_OUT_3_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_STATEZ(3), datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(3), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_STATE_OUT_4_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_STATEZ(4), datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(4), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_STATE_OUT_5_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_STATEZ(5), datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(5), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_STATE_OUT_6_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_STATEZ(6), datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(6), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_B_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_BZ, datain => \VGA_CONTROL_UNIT.B\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_G_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_GZ, datain => \VGA_CONTROL_UNIT.G\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_R_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_RZ, datain => \VGA_CONTROL_UNIT.R\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_V_ENABLE_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_V_ENABLEZ, datain => \VGA_DRIVER_UNIT.V_ENABLE_SIG\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_H_ENABLE_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_H_ENABLEZ, datain => \VGA_DRIVER_UNIT.H_ENABLE_SIG\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_SET_VSYNC_COUNTER_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_SET_VSYNC_COUNTERZ, datain => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_SET_HSYNC_COUNTER_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_SET_HSYNC_COUNTERZ, datain => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_9_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(9), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_8_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(8), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_7_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(7), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_6_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(6), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_5_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(5), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_4_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(4), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_3_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(3), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_2_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(2), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_1_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(1), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_VSYNC_COUNTER_OUT_0_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNC_COUNTERZ(0), datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_9_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(9), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_8_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(8), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_7_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(7), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_6_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(6), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_5_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(5), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_4_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(4), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_3_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(3), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_2_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(2), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_1_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(1), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_HSYNC_COUNTER_OUT_0_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNC_COUNTERZ(0), datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_SET_LINE_COUNTER_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_SET_LINE_COUNTERZ, datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_SET_COLUMN_COUNTER_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_SET_COLUMN_COUNTERZ, datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_8_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(8), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_7_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(7), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_6_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(6), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_5_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(5), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_4_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(4), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_3_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(3), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_2_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(2), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_1_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(1), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_LINE_COUNTER_OUT_0_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_LINE_COUNTERZ(0), datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_9_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(9), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_8_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(8), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_7_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(7), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_6_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(6), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_5_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(5), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_4_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(4), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_3_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(3), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_2_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(2), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_1_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(1), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \D_COLUMN_COUNTER_OUT_0_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_COLUMN_COUNTERZ(0), datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0), oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_VSYNC_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_VSYNCZ, datain => \VGA_DRIVER_UNIT.V_SYNC\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); D_HSYNC_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => D_HSYNCZ, datain => \VGA_DRIVER_UNIT.H_SYNC\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_TRI_13_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(13), datain => VCC, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_OUT_12_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(12), datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_OUT_11_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(11), datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_OUT_10_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(10), datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_OUT_9_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(9), datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_OUT_8_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(8), datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_OUT_7_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(7), datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_TRI_6_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(6), datain => VCC, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_TRI_5_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(5), datain => VCC, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_TRI_4_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(4), datain => VCC, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_TRI_3_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(3), datain => VCC, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_OUT_2_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(2), datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_OUT_1_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(1), datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); \SEVEN_SEG_PIN_TRI_0_\: stratix_io generic map ( operation_mode => "output" ) port map ( padio => SEVEN_SEG_PINZ(0), datain => VCC, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); VSYNC_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => VSYNC_PINZ, datain => \VGA_DRIVER_UNIT.V_SYNC\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); HSYNC_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => HSYNC_PINZ, datain => \VGA_DRIVER_UNIT.H_SYNC\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); B1_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => B1_PINZ, datain => \VGA_CONTROL_UNIT.B\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); B0_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => B0_PINZ, datain => \VGA_CONTROL_UNIT.B\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); G2_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => G2_PINZ, datain => \VGA_CONTROL_UNIT.G\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); G1_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => G1_PINZ, datain => \VGA_CONTROL_UNIT.G\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); G0_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => G0_PINZ, datain => \VGA_CONTROL_UNIT.G\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); R2_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => R2_PINZ, datain => \VGA_CONTROL_UNIT.R\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); R1_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => R1_PINZ, datain => \VGA_CONTROL_UNIT.R\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); R0_PIN_OUT: stratix_io generic map ( operation_mode => "output" ) port map ( padio => R0_PINZ, datain => \VGA_CONTROL_UNIT.R\, oe => VCC, devpor => devpor, devclrn => devclrn, devoe => devoe, outclkena => VCC, inclkena => VCC, areset => GND, sreset => GND); G_33 <= CLK_PIN_C; VGA_DRIVER_UNIT: vga_driver port map ( line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0), line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1), line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2), line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3), line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4), line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5), line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6), line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7), line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8), dly_counter_1 => DLY_COUNTER(1), dly_counter_0 => DLY_COUNTER(0), vsync_state_2 => \VGA_DRIVER_UNIT.VSYNC_STATE\(2), vsync_state_5 => \VGA_DRIVER_UNIT.VSYNC_STATE\(5), vsync_state_3 => \VGA_DRIVER_UNIT.VSYNC_STATE\(3), vsync_state_6 => \VGA_DRIVER_UNIT.VSYNC_STATE\(6), vsync_state_4 => \VGA_DRIVER_UNIT.VSYNC_STATE\(4), vsync_state_1 => \VGA_DRIVER_UNIT.VSYNC_STATE\(1), vsync_state_0 => \VGA_DRIVER_UNIT.VSYNC_STATE\(0), hsync_state_2 => \VGA_DRIVER_UNIT.HSYNC_STATE\(2), hsync_state_4 => \VGA_DRIVER_UNIT.HSYNC_STATE\(4), hsync_state_0 => \VGA_DRIVER_UNIT.HSYNC_STATE\(0), hsync_state_5 => \VGA_DRIVER_UNIT.HSYNC_STATE\(5), hsync_state_1 => \VGA_DRIVER_UNIT.HSYNC_STATE\(1), hsync_state_3 => \VGA_DRIVER_UNIT.HSYNC_STATE\(3), hsync_state_6 => \VGA_DRIVER_UNIT.HSYNC_STATE\(6), column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0), column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1), column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2), column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3), column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4), column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5), column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6), column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7), column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8), column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9), vsync_counter_9 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9), vsync_counter_8 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8), vsync_counter_7 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7), vsync_counter_6 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6), vsync_counter_5 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5), vsync_counter_4 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4), vsync_counter_3 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3), vsync_counter_2 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2), vsync_counter_1 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1), vsync_counter_0 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0), hsync_counter_9 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9), hsync_counter_8 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8), hsync_counter_7 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7), hsync_counter_6 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6), hsync_counter_5 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5), hsync_counter_4 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4), hsync_counter_3 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3), hsync_counter_2 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2), hsync_counter_1 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1), hsync_counter_0 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0), d_set_vsync_counter => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\, v_sync => \VGA_DRIVER_UNIT.V_SYNC\, h_sync => \VGA_DRIVER_UNIT.H_SYNC\, h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\, v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\, reset_pin_c => RESET_PIN_C, un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, d_set_hsync_counter => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\, clk_pin_c => CLK_PIN_C); VGA_CONTROL_UNIT: vga_control port map ( line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0), line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2), line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1), line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3), line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6), line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5), line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4), line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7), line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8), column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0), column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1), column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2), column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8), column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3), column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5), column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4), column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9), column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7), column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6), toggle_counter_sig_0 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0), toggle_counter_sig_1 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1), toggle_counter_sig_2 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2), toggle_counter_sig_3 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3), toggle_counter_sig_4 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4), toggle_counter_sig_5 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5), toggle_counter_sig_6 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6), toggle_counter_sig_7 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7), toggle_counter_sig_8 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8), toggle_counter_sig_9 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9), toggle_counter_sig_10 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10), toggle_counter_sig_11 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11), toggle_counter_sig_12 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12), toggle_counter_sig_13 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13), toggle_counter_sig_14 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14), toggle_counter_sig_15 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15), toggle_counter_sig_16 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16), toggle_counter_sig_17 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17), toggle_counter_sig_18 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18), toggle_counter_sig_19 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19), toggle_counter_sig_20 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20), toggle_counter_sig_21 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21), toggle_counter_sig_22 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22), toggle_counter_sig_23 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23), toggle_counter_sig_24 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24), h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\, g => \VGA_CONTROL_UNIT.G\, b => \VGA_CONTROL_UNIT.B\, v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\, r => \VGA_CONTROL_UNIT.R\, toggle_sig => \VGA_CONTROL_UNIT.TOGGLE_SIG\, un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\, clk_pin_c => CLK_PIN_C); N_1 <= CLK_PIN_INTERNAL; N_2 <= RESET_PIN_INTERNAL; N_84_0 <= R0_PINZ; N_85_0 <= R1_PINZ; N_86_0 <= R2_PINZ; N_87_0 <= G0_PINZ; N_88_0 <= G1_PINZ; N_89_0 <= G2_PINZ; N_90_0 <= B0_PINZ; N_91_0 <= B1_PINZ; N_92_0 <= HSYNC_PINZ; N_93_0 <= VSYNC_PINZ; N_94_0 <= SEVEN_SEG_PINZ(0); N_95_0 <= SEVEN_SEG_PINZ(1); N_96_0 <= SEVEN_SEG_PINZ(2); N_97_0 <= SEVEN_SEG_PINZ(3); N_98_0 <= SEVEN_SEG_PINZ(4); N_99_0 <= SEVEN_SEG_PINZ(5); N_100_0 <= SEVEN_SEG_PINZ(6); N_101_0 <= SEVEN_SEG_PINZ(7); N_102_0 <= SEVEN_SEG_PINZ(8); N_103_0 <= SEVEN_SEG_PINZ(9); N_104_0 <= SEVEN_SEG_PINZ(10); N_105_0 <= SEVEN_SEG_PINZ(11); N_106_0 <= SEVEN_SEG_PINZ(12); N_107_0 <= SEVEN_SEG_PINZ(13); N_108_0 <= D_HSYNCZ; N_109_0 <= D_VSYNCZ; N_110_0 <= D_COLUMN_COUNTERZ(0); N_111_0 <= D_COLUMN_COUNTERZ(1); N_112_0 <= D_COLUMN_COUNTERZ(2); N_113_0 <= D_COLUMN_COUNTERZ(3); N_114_0 <= D_COLUMN_COUNTERZ(4); N_115_0 <= D_COLUMN_COUNTERZ(5); N_116_0 <= D_COLUMN_COUNTERZ(6); N_117_0 <= D_COLUMN_COUNTERZ(7); N_118 <= D_COLUMN_COUNTERZ(8); N_119 <= D_COLUMN_COUNTERZ(9); N_120 <= D_LINE_COUNTERZ(0); N_121 <= D_LINE_COUNTERZ(1); N_122 <= D_LINE_COUNTERZ(2); N_123 <= D_LINE_COUNTERZ(3); N_124 <= D_LINE_COUNTERZ(4); N_125 <= D_LINE_COUNTERZ(5); N_126 <= D_LINE_COUNTERZ(6); N_127 <= D_LINE_COUNTERZ(7); N_128 <= D_LINE_COUNTERZ(8); N_129 <= D_SET_COLUMN_COUNTERZ; N_130 <= D_SET_LINE_COUNTERZ; N_131 <= D_HSYNC_COUNTERZ(0); N_132 <= D_HSYNC_COUNTERZ(1); N_133 <= D_HSYNC_COUNTERZ(2); N_134 <= D_HSYNC_COUNTERZ(3); N_135 <= D_HSYNC_COUNTERZ(4); N_136 <= D_HSYNC_COUNTERZ(5); N_137 <= D_HSYNC_COUNTERZ(6); N_138 <= D_HSYNC_COUNTERZ(7); N_139 <= D_HSYNC_COUNTERZ(8); N_140 <= D_HSYNC_COUNTERZ(9); N_141 <= D_VSYNC_COUNTERZ(0); N_142 <= D_VSYNC_COUNTERZ(1); N_143 <= D_VSYNC_COUNTERZ(2); N_144 <= D_VSYNC_COUNTERZ(3); N_145 <= D_VSYNC_COUNTERZ(4); N_146 <= D_VSYNC_COUNTERZ(5); N_147 <= D_VSYNC_COUNTERZ(6); N_148 <= D_VSYNC_COUNTERZ(7); N_149 <= D_VSYNC_COUNTERZ(8); N_150 <= D_VSYNC_COUNTERZ(9); N_151 <= D_SET_HSYNC_COUNTERZ; N_152 <= D_SET_VSYNC_COUNTERZ; N_153 <= D_H_ENABLEZ; N_154 <= D_V_ENABLEZ; N_155 <= D_RZ; N_156 <= D_GZ; N_157 <= D_BZ; N_158 <= D_HSYNC_STATEZ(6); N_159 <= D_HSYNC_STATEZ(5); N_160 <= D_HSYNC_STATEZ(4); N_161 <= D_HSYNC_STATEZ(3); N_162 <= D_HSYNC_STATEZ(2); N_163 <= D_HSYNC_STATEZ(1); N_164 <= D_HSYNC_STATEZ(0); N_165 <= D_VSYNC_STATEZ(6); N_166 <= D_VSYNC_STATEZ(5); N_167 <= D_VSYNC_STATEZ(4); N_168 <= D_VSYNC_STATEZ(3); N_169 <= D_VSYNC_STATEZ(2); N_170 <= D_VSYNC_STATEZ(1); N_171 <= D_VSYNC_STATEZ(0); N_172 <= D_STATE_CLKZ; N_173 <= D_TOGGLEZ; N_174 <= D_TOGGLE_COUNTERZ(0); N_175 <= D_TOGGLE_COUNTERZ(1); N_176 <= D_TOGGLE_COUNTERZ(2); N_177 <= D_TOGGLE_COUNTERZ(3); N_178 <= D_TOGGLE_COUNTERZ(4); N_179 <= D_TOGGLE_COUNTERZ(5); N_180 <= D_TOGGLE_COUNTERZ(6); N_181 <= D_TOGGLE_COUNTERZ(7); N_182 <= D_TOGGLE_COUNTERZ(8); N_183 <= D_TOGGLE_COUNTERZ(9); N_184 <= D_TOGGLE_COUNTERZ(10); N_185 <= D_TOGGLE_COUNTERZ(11); N_186 <= D_TOGGLE_COUNTERZ(12); N_187 <= D_TOGGLE_COUNTERZ(13); N_188 <= D_TOGGLE_COUNTERZ(14); N_189 <= D_TOGGLE_COUNTERZ(15); N_190 <= D_TOGGLE_COUNTERZ(16); N_191 <= D_TOGGLE_COUNTERZ(17); N_192 <= D_TOGGLE_COUNTERZ(18); N_193 <= D_TOGGLE_COUNTERZ(19); N_194 <= D_TOGGLE_COUNTERZ(20); N_195 <= D_TOGGLE_COUNTERZ(21); N_196 <= D_TOGGLE_COUNTERZ(22); N_197 <= D_TOGGLE_COUNTERZ(23); N_198 <= D_TOGGLE_COUNTERZ(24); r0_pin <= N_84_0; r1_pin <= N_85_0; r2_pin <= N_86_0; g0_pin <= N_87_0; g1_pin <= N_88_0; g2_pin <= N_89_0; b0_pin <= N_90_0; b1_pin <= N_91_0; hsync_pin <= N_92_0; vsync_pin <= N_93_0; seven_seg_pin(0) <= N_94_0; seven_seg_pin(1) <= N_95_0; seven_seg_pin(2) <= N_96_0; seven_seg_pin(3) <= N_97_0; seven_seg_pin(4) <= N_98_0; seven_seg_pin(5) <= N_99_0; seven_seg_pin(6) <= N_100_0; seven_seg_pin(7) <= N_101_0; seven_seg_pin(8) <= N_102_0; seven_seg_pin(9) <= N_103_0; seven_seg_pin(10) <= N_104_0; seven_seg_pin(11) <= N_105_0; seven_seg_pin(12) <= N_106_0; seven_seg_pin(13) <= N_107_0; d_hsync <= N_108_0; d_vsync <= N_109_0; d_column_counter(0) <= N_110_0; d_column_counter(1) <= N_111_0; d_column_counter(2) <= N_112_0; d_column_counter(3) <= N_113_0; d_column_counter(4) <= N_114_0; d_column_counter(5) <= N_115_0; d_column_counter(6) <= N_116_0; d_column_counter(7) <= N_117_0; d_column_counter(8) <= N_118; d_column_counter(9) <= N_119; d_line_counter(0) <= N_120; d_line_counter(1) <= N_121; d_line_counter(2) <= N_122; d_line_counter(3) <= N_123; d_line_counter(4) <= N_124; d_line_counter(5) <= N_125; d_line_counter(6) <= N_126; d_line_counter(7) <= N_127; d_line_counter(8) <= N_128; d_set_column_counter <= N_129; d_set_line_counter <= N_130; d_hsync_counter(0) <= N_131; d_hsync_counter(1) <= N_132; d_hsync_counter(2) <= N_133; d_hsync_counter(3) <= N_134; d_hsync_counter(4) <= N_135; d_hsync_counter(5) <= N_136; d_hsync_counter(6) <= N_137; d_hsync_counter(7) <= N_138; d_hsync_counter(8) <= N_139; d_hsync_counter(9) <= N_140; d_vsync_counter(0) <= N_141; d_vsync_counter(1) <= N_142; d_vsync_counter(2) <= N_143; d_vsync_counter(3) <= N_144; d_vsync_counter(4) <= N_145; d_vsync_counter(5) <= N_146; d_vsync_counter(6) <= N_147; d_vsync_counter(7) <= N_148; d_vsync_counter(8) <= N_149; d_vsync_counter(9) <= N_150; d_set_hsync_counter <= N_151; d_set_vsync_counter <= N_152; d_h_enable <= N_153; d_v_enable <= N_154; d_r <= N_155; d_g <= N_156; d_b <= N_157; d_hsync_state(6) <= N_158; d_hsync_state(5) <= N_159; d_hsync_state(4) <= N_160; d_hsync_state(3) <= N_161; d_hsync_state(2) <= N_162; d_hsync_state(1) <= N_163; d_hsync_state(0) <= N_164; d_vsync_state(6) <= N_165; d_vsync_state(5) <= N_166; d_vsync_state(4) <= N_167; d_vsync_state(3) <= N_168; d_vsync_state(2) <= N_169; d_vsync_state(1) <= N_170; d_vsync_state(0) <= N_171; d_state_clk <= N_172; d_toggle <= N_173; d_toggle_counter(0) <= N_174; d_toggle_counter(1) <= N_175; d_toggle_counter(2) <= N_176; d_toggle_counter(3) <= N_177; d_toggle_counter(4) <= N_178; d_toggle_counter(5) <= N_179; d_toggle_counter(6) <= N_180; d_toggle_counter(7) <= N_181; d_toggle_counter(8) <= N_182; d_toggle_counter(9) <= N_183; d_toggle_counter(10) <= N_184; d_toggle_counter(11) <= N_185; d_toggle_counter(12) <= N_186; d_toggle_counter(13) <= N_187; d_toggle_counter(14) <= N_188; d_toggle_counter(15) <= N_189; d_toggle_counter(16) <= N_190; d_toggle_counter(17) <= N_191; d_toggle_counter(18) <= N_192; d_toggle_counter(19) <= N_193; d_toggle_counter(20) <= N_194; d_toggle_counter(21) <= N_195; d_toggle_counter(22) <= N_196; d_toggle_counter(23) <= N_197; d_toggle_counter(24) <= N_198; CLK_PIN_INTERNAL <= clk_pin; RESET_PIN_INTERNAL <= reset_pin; end beh;