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Add support for Intel Sandybridge CPU
[coreboot.git] / src / cpu / intel / slot_1 /
2011-08-04 Keith Huicpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. tree | commitdiff
2010-10-16 Keith HuiMove support for Deschutes Slot 1 CPUs (model_65x)... tree | commitdiff
2010-10-15 Uwe HermannDrop unused DCACHE_RAM_BASE from intel/car/cache_as_ram... tree | commitdiff
2010-10-13 Keith HuiMove out Katmai Slot 1 CPUs (model_67x) from model_6xx... tree | commitdiff
2010-10-12 Keith HuiAdd missing include of model_6bx for slot_1. tree | commitdiff
2010-10-06 Uwe HermannConvert all Intel 440BX boards to Cache-as-RAM (CAR). tree | commitdiff
2010-09-30 Patrick GeorgiRename build system variables to be more intuitive... tree | commitdiff
2010-05-14 Nils Jacobslicense header fixes tree | commitdiff
2010-03-05 Keith HuiAdd proper Slot 1 CPU support code/infrastructure. tree | commitdiff
my coreboot WIP stuff (asus m5a99x-evo board)