Add proper Slot 1 CPU support code/infrastructure.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 24a9b4d9c4a73790368d943babaf9d9f35a27f59..3e38e477adfdae4ed196817a4a822148e7a675f0 100644 (file)
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -8,6 +8,7 @@ source src/cpu/intel/model_106cx/Kconfig
 source src/cpu/intel/bga956/Kconfig
 source src/cpu/intel/ep80579/Kconfig
 source src/cpu/intel/slot_2/Kconfig
+source src/cpu/intel/slot_1/Kconfig
 source src/cpu/intel/socket_mFCPGA478/Kconfig
 source src/cpu/intel/socket_mPGA478/Kconfig
 source src/cpu/intel/socket_mPGA479M/Kconfig

diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index f5de4b80906abc95498b592f0341ed1cc0ea9abc..c94b56ff31e3940a28fc48c54c29b083e32c38fc 100644 (file)
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
+subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 
 #socket_mPGA604_533Mhz
 #socket_mPGA604_800Mhz

diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
new file mode 100644 (file)
index 0000000..31eea99
--- /dev/null
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -0,0 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config CPU_INTEL_SLOT_1
+       bool
+
+config DCACHE_RAM_BASE
+       hex
+       default 0xc0000
+       depends on CPU_INTEL_SLOT_1
+
+config DCACHE_RAM_SIZE
+       hex
+       default 0x01000
+       depends on CPU_INTEL_SLOT_1
+

diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
new file mode 100644 (file)
index 0000000..1692656
--- /dev/null
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -0,0 +1,29 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+obj-y += slot_1.o
+subdirs-y += ../model_6xx
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+

diff --git a/src/cpu/intel/slot_1/chip.h b/src/cpu/intel/slot_1/chip.h
new file mode 100644 (file)
index 0000000..6721d6e
--- /dev/null
+++ b/src/cpu/intel/slot_1/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_slot_1_ops;
+
+struct cpu_intel_slot_1_config {
+};

diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c
new file mode 100644 (file)
index 0000000..548127f
--- /dev/null
+++ b/src/cpu/intel/slot_1/slot_1.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_intel_slot_1_ops = {
+       CHIP_NAME("Slot 1 CPU")
+};