/* this is to be filled by SB code - startup value what was found */
u8 acpi_slp_type = 0;
-int acpi_is_wakeup(void)
+static int acpi_is_wakeup(void)
{
return (acpi_slp_type == 3);
}
memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
/* copy wakeup trampoline in place */
- memcpy(WAKEUP_BASE, &__wakeup, &__wakeup_size);
+ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
}
#include <ip_checksum.h>
#include <boot/tables.h>
#include <boot/coreboot_tables.h>
-#include "coreboot_table.h"
+#include <arch/coreboot_tables.h>
#include <string.h>
#include <version.h>
#include <device/device.h>
+++ /dev/null
-#ifndef COREBOOT_TABLE_H
-#define COREBOOT_TABLE_H
-
-#include <boot/coreboot_tables.h>
-
-/* This file holds function prototypes for building the coreboot table. */
-unsigned long write_coreboot_table(
- unsigned long low_table_start, unsigned long low_table_end,
- unsigned long rom_table_start, unsigned long rom_table_end);
-
-void lb_memory_range(struct lb_memory *mem,
- uint32_t type, uint64_t start, uint64_t size);
-
-/* Routines to extract part so the coreboot table or information
- * from the coreboot table.
- */
-struct lb_memory *get_lb_mem(void);
-
-extern struct cmos_option_table option_table;
-
-/* defined by mainboard.c if the mainboard requires extra resources */
-int add_mainboard_resources(struct lb_memory *mem);
-
-#endif /* COREBOOT_TABLE_H */
#include <string.h>
#include <device/pci.h>
-#if (CONFIG_DEBUG==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+#ifndef CONFIG_IRQ_SLOT_COUNT
+#warning "CONFIG_IRQ_SLOT_COUNT is not defined. PIRQ won't work correctly."
+#endif
+
+#if CONFIG_DEBUG
static void check_pirq_routing_table(struct irq_routing_table *rt)
{
uint8_t *addr = (uint8_t *)rt;
printk_info("Checking Interrupt Routing Table consistency...\n");
-#if defined(CONFIG_IRQ_SLOT_COUNT)
if (sizeof(struct irq_routing_table) != rt->size) {
printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
sizeof(struct irq_routing_table),
);
rt->size=sizeof(struct irq_routing_table);
}
-#endif
for (i = 0; i < rt->size; i++)
sum += addr[i];
return 0;
}
-#else
-#define verify_copy_pirq_routing_table(addr)
#endif
-#if CONFIG_GENERATE_PIRQ_TABLE==1
unsigned long copy_pirq_routing_table(unsigned long addr)
{
/* Align the table to be 16 byte aligned. */
pirq_routing_irqs(addr);
return addr + intel_irq_routing_table.size;
}
-#endif
-#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+#if CONFIG_PIRQ_ROUTE
void pirq_routing_irqs(unsigned long addr)
{
int i, j, k, num_entries;
#include <cpu/cpu.h>
#include <boot/tables.h>
#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
#include <arch/pirq_routing.h>
#include <arch/smp/mpspec.h>
#include <arch/acpi.h>
#include <string.h>
#include <cpu/x86/multiboot.h>
-#include "coreboot_table.h"
#include <cbmem.h>
#include <lib.h>
acpi_write_rsdp(low_rsdp,
(acpi_rsdt_t *)(high_rsdp->rsdt_address),
- (acpi_xsdt_t *)(high_rsdp->xsdt_address));
+ (acpi_xsdt_t *)((unsigned long)high_rsdp->xsdt_address));
} else {
printk_err("ERROR: Didn't find RSDP in high table.\n");
}
} __attribute__ ((packed)) acpi_ecdt_t;
-/* These are implemented by the target port */
+/* These are implemented by the target port or north/southbridge*/
unsigned long write_acpi_tables(unsigned long addr);
unsigned long acpi_fill_madt(unsigned long current);
unsigned long acpi_fill_mcfg(unsigned long current);
#endif
+/* northbridge/amd/amdfam10/amdfam10_acpi.c */
unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current);
+/* cpu/intel/speedstep/acpi.c */
+void generate_cpu_entries(void);
#define ACPI_WRITE_MADT_IOAPIC(dev,id) \
do { \
--- /dev/null
+#ifndef COREBOOT_TABLE_H
+#define COREBOOT_TABLE_H
+
+#include <boot/coreboot_tables.h>
+
+/* This file holds function prototypes for building the coreboot table. */
+unsigned long write_coreboot_table(
+ unsigned long low_table_start, unsigned long low_table_end,
+ unsigned long rom_table_start, unsigned long rom_table_end);
+
+void lb_memory_range(struct lb_memory *mem,
+ uint32_t type, uint64_t start, uint64_t size);
+
+/* Routines to extract part so the coreboot table or information
+ * from the coreboot table.
+ */
+struct lb_memory *get_lb_mem(void);
+
+extern struct cmos_option_table option_table;
+
+/* defined by mainboard.c if the mainboard requires extra resources */
+int add_mainboard_resources(struct lb_memory *mem);
+int add_northbridge_resources(struct lb_memory *mem);
+
+#endif /* COREBOOT_TABLE_H */
unsigned char mpf_checksum; /* Checksum (makes sum 0) */
unsigned char mpf_feature1; /* Standard or configuration ? */
unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
+#define MP_FEATURE_VIRTUALWIRE (1 << 7)
+#define MP_FEATURE_PIC (0 << 7)
unsigned char mpf_feature3; /* Unused (0) */
unsigned char mpf_feature4; /* Unused (0) */
unsigned char mpf_feature5; /* Unused (0) */
-extern int do_printk(int msg_level, const char *fmt, ...);
-
#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
#define printk_alert(fmt, arg...) do_printk(BIOS_ALERT ,fmt, ##arg)
#define printk_crit(fmt, arg...) do_printk(BIOS_CRIT ,fmt, ##arg)
info = cpu_info();
- printk_notice("Initializing CPU #%ld\n", info->index);
+ printk_info("Initializing CPU #%ld\n", info->index);
cpu = info->cpu;
if (!cpu) {
#include <device/pci.h>
#include <delay.h>
#include <stdlib.h>
-#include <part/hard_reset.h>
-#include <part/init_timer.h>
+#include <reset.h>
#include <boot/tables.h>
#include <boot/elf.h>
#include <cbfs.h>
*/
#include <console/console.h>
-#include <part/fallback_boot.h>
+#include <fallback.h>
#include <boot/elf.h>
#include <boot/elf_boot.h>
#include <boot/coreboot_tables.h>
real_main(bist);
/* No servicable parts below this line .. */
-
-#if CAR_DEBUG
+#ifdef CAR_DEBUG
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
/* No servicable parts below this line .. */
-#if CAR_DEBUG
+#ifdef CAR_DEBUG
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
-/* Copyright (C) 2009 coresystems GmbH
- (Written by Patrick Georgi <patrick.georgi@coresystems.de> for coresystems GmbH
-*/
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009-2010 coresystems GmbH
+ * Written by Patrick Georgi <patrick.georgi@coresystems.de>
+ * for coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
-void cbfs_and_run_core(char*, unsigned ebp);
+void cbfs_and_run_core(const char *, unsigned ebp);
static void copy_and_run(unsigned cpu_reset)
{
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
-#include <part/hard_reset.h>
-#include <part/fallback_boot.h>
/* The hypertransport link is already optimized in pre-ram code
* so don't do it again
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <part/hard_reset.h>
-#include <part/fallback_boot.h>
#include <delay.h>
#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
#include <device/hypertransport.h>
resource = new_resource(dev, PNP_IDX_DRQ1);
resource->size = 1;
resource->flags |= IORESOURCE_DRQ;
- }
+ }
+ /* These are not IRQs, but set the flag to have the
+ * resource allocator do the right thing
+ */
+ if (info->flags & PNP_EN) {
+ resource = new_resource(dev, PNP_IDX_EN);
+ resource->size = 1;
+ resource->flags |= IORESOURCE_IRQ;
+ }
+ if (info->flags & PNP_MSC0) {
+ resource = new_resource(dev, PNP_IDX_MSC0);
+ resource->size = 1;
+ resource->flags |= IORESOURCE_IRQ;
+ }
+ if (info->flags & PNP_MSC1) {
+ resource = new_resource(dev, PNP_IDX_MSC1);
+ resource->size = 1;
+ resource->flags |= IORESOURCE_IRQ;
+ }
}
void pnp_enable_devices(device_t base_dev, struct device_operations *ops,
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <part/hard_reset.h>
+#include <reset.h>
/**
* Read the resources for the root device,
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
-#include <part/hard_reset.h>
+#include <reset.h>
#include <delay.h>
#include "chip.h"
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
#include <cpu/x86/msr.h>
#include "chip.h"
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
#include <cpu/x86/msr.h>
#include "chip.h"
#if CONFIG_HAVE_SMI_HANDLER
void smm_init(void);
+void smm_lock(void);
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
#endif
#define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
#ifndef CPU_X86_BIST_H
#define CPU_X86_BIST_H
-static void report_bist_failure(unsigned long bist)
+static void report_bist_failure(u32 bist)
{
if (bist != 0) {
#if CONFIG_USE_PRINTK_IN_CAR
*/
static inline __attribute__((always_inline)) void stop_this_cpu(void)
{
-
/* Called by an AP when it is ready to halt and wait for a new task */
for(;;) {
hlt();
}
}
+#else
+void stop_this_cpu(void);
#endif
#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
asm volatile ("rdtsc" : "=A" (val));
return val;
}
-
-void init_timer(void);
#endif
-
#endif /* CPU_X86_TSC_H */
#ifndef DELAY_H
#define DELAY_H
+
#if !defined( __ROMCC__)
+#if CONFIG_HAVE_INIT_TIMER == 1
+void init_timer(void);
+#else
+#define init_timer() do{} while(0)
+#endif
+
void udelay(unsigned usecs);
void mdelay(unsigned msecs);
void delay(unsigned secs);
struct device_operations *ops;
unsigned function;
unsigned flags;
-#define PNP_IO0 0x01
-#define PNP_IO1 0x02
-#define PNP_IO2 0x04
-#define PNP_IO3 0x08
-#define PNP_IRQ0 0x10
-#define PNP_IRQ1 0x20
-#define PNP_DRQ0 0x40
-#define PNP_DRQ1 0x80
+#define PNP_IO0 0x001
+#define PNP_IO1 0x002
+#define PNP_IO2 0x004
+#define PNP_IO3 0x008
+#define PNP_IRQ0 0x010
+#define PNP_IRQ1 0x020
+#define PNP_DRQ0 0x040
+#define PNP_DRQ1 0x080
+#define PNP_EN 0x100
+#define PNP_MSC0 0x200
+#define PNP_MSC1 0x400
struct io_info io0, io1, io2, io3;
};
struct resource *pnp_get_resource(device_t dev, unsigned index);
#ifndef DEVICE_PNP_DEF_H
#define DEVICE_PNP_DEF_H
+#define PNP_IDX_EN 0x30
#define PNP_IDX_IO0 0x60
#define PNP_IDX_IO1 0x62
#define PNP_IDX_IO2 0x64
#define PNP_IDX_IRQ1 0x72
#define PNP_IDX_DRQ0 0x74
#define PNP_IDX_DRQ1 0x75
-
+#define PNP_IDX_MSC0 0xf0
+#define PNP_IDX_MSC1 0xf1
#endif /* DEVICE_PNP_DEF_H */
--- /dev/null
+#ifndef FALLBACK_H
+#define FALLBACK_H
+
+#ifndef ASSEMBLY
+
+#if CONFIG_HAVE_FALLBACK_BOOT == 1
+void set_boot_successful(void);
+#else
+#define set_boot_successful()
+#endif
+
+void boot_successful(void);
+
+#endif /* ASSEMBLY */
+
+#define RTC_BOOT_BYTE 48
+
+#endif /* FALLBACK_H */
+++ /dev/null
-#ifndef PART_FALLBACK_BOOT_H
-#define PART_FALLBACK_BOOT_H
-
-#ifndef ASSEMBLY
-
-#if CONFIG_HAVE_FALLBACK_BOOT == 1
-void set_boot_successful(void);
-#else
-#define set_boot_successful()
-#endif
-
-void boot_successful(void);
-
-#endif /* ASSEMBLY */
-
-#define RTC_BOOT_BYTE 48
-
-#endif /* PART_FALLBACK_BOOT_H */
+++ /dev/null
-#ifndef PART_HARD_RESET_H
-#define PART_HARD_RESET_H
-
-#if CONFIG_HAVE_HARD_RESET == 1
-void hard_reset(void);
-#else
-#define hard_reset() do {} while(0)
-#endif
-
-
-#endif
+++ /dev/null
-#ifndef PART_INIT_TIMER_H
-#define PART_DELAY_H
-
-#if CONFIG_HAVE_INIT_TIMER == 1
-void init_timer(void);
-#else
-#define init_timer() do{} while(0)
-#endif
-
-#endif /* PART_INIT_TIMER_H */
+++ /dev/null
-#ifndef PART_WATCHDOG_H
-#define PART_WATCHDOG_H
-
-#if CONFIG_USE_WATCHDOG_ON_BOOT == 1
-void watchdog_off(void);
-#else
-#define watchdog_off()
-#endif
-
-#endif /* PART_WATCHDOG_H */
--- /dev/null
+#ifndef RESET_H
+#define RESET_H
+
+#if CONFIG_HAVE_HARD_RESET == 1
+void hard_reset(void);
+#else
+#define hard_reset() do {} while(0)
+#endif
+void soft_reset(void);
+
+#endif
--- /dev/null
+#ifndef WATCHDOG_H
+#define WATCHDOG_H
+
+#if CONFIG_USE_WATCHDOG_ON_BOOT == 1
+void watchdog_off(void);
+#else
+#define watchdog_off()
+#endif
+
+#endif /* WATCHDOG_H */
if (acpi_slp_type == 3) {
if (!cbmem_reinit(high_tables_base)) {
/* Something went wrong, our high memory area got wiped */
- acpi_slp_type == 0;
+ acpi_slp_type = 0;
cbmem_init(high_tables_base, high_tables_size);
}
} else {
#include <console/console.h>
-#include <part/fallback_boot.h>
-#include <part/watchdog.h>
+#include <fallback.h>
+#include <watchdog.h>
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
* Fill.
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("DRAM fill: 0x%08x-0x%08x\r\n", start, stop);
+ printk_debug("DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop);
#else
print_debug("DRAM fill: ");
print_debug_hex32(start);
/* Display address being filled */
if (!(addr & 0xfffff)) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%08x \r", addr);
+ printk_debug("%08lx \r", addr);
#else
print_debug_hex32(addr);
print_debug(" \r");
};
/* Display final address */
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%08x\r\nDRAM filled\r\n", addr);
+ printk_debug("%08lx\r\nDRAM filled\r\n", addr);
#else
print_debug_hex32(addr);
print_debug("\r\nDRAM filled\r\n");
* Verify.
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("DRAM verify: 0x%08x-0x%08x\r\n", start, stop);
+ printk_debug("DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop);
#else
print_debug("DRAM verify: ");
print_debug_hex32(start);
/* Display address being tested */
if (!(addr & 0xfffff)) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%08x \r", addr);
+ printk_debug("%08lx \r", addr);
#else
print_debug_hex32(addr);
print_debug(" \r");
if (value != addr) {
/* Display address with error */
#if CONFIG_USE_PRINTK_IN_CAR
- printk_err("Fail: @0x%08x Read value=0x%08x\r\n", addr, value);
+ printk_err("Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value);
#else
print_err("Fail: @0x");
print_err_hex32(addr);
}
/* Display final address */
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%08x", addr);
+ printk_debug("%08lx", addr);
#else
print_debug_hex32(addr);
#endif
* are tested. -Tyson
*/
#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("Testing DRAM : %08x - %08x\r\n", start, stop);
+ printk_debug("Testing DRAM : %08lx - %08lx\r\n", start, stop);
#else
print_debug("Testing DRAM : ");
print_debug_hex32(start);
int
default 2
depends on BOARD_INTEL_D945GCLF
+
+config HAVE_ACPI_SLIC
+ bool
+ default n
+ depends on BOARD_INTEL_D945GCLF
+
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
-void generate_cpu_entries(void); // from cpu/intel/speedstep
-unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
#if OLD_ACPI
typedef struct acpi_oemb {
string
default "amipci_01.20"
depends on BOARD_KONTRON_986LCD_M
+
+config HAVE_ACPI_SLIC
+ bool
+ default n
+ depends on BOARD_KONTRON_986LCD_M
+
#include "dmi.h"
extern unsigned char AmlCode[];
-#if HAVE_ACPI_SLIC
+#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
-void generate_cpu_entries(void); // from cpu/intel/speedstep
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
acpi_mcfg_t *mcfg;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
-#if HAVE_ACPI_SLIC
+#if CONFIG_HAVE_ACPI_SLIC
acpi_header_t *slic;
#endif
acpi_header_t *ssdt;
/* Pack GNVS into the ACPI table area */
for (i=0; i < dsdt->length; i++) {
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
- printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current);
+ printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
break;
}
}
/* And fill it */
- acpi_create_gnvs(current);
+ acpi_create_gnvs((global_nvs_t *)current);
current += 0x100;
ALIGN_CURRENT;
printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
-#if HAVE_ACPI_SLIC
+#if CONFIG_HAVE_ACPI_SLIC
printk_debug("ACPI: * SLIC\n");
slic = (acpi_header_t *)current;
current += acpi_create_slic(current);
device pnp 4e.3 on # COM4
io 0x60 = 0x2e8
irq 0x70 = 10
+ irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
end
device pnp 4e.5 off # Keyboard
end
#include <x86emu/x86emu.h>
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
+#include <arch/coreboot_tables.h>
#include "chip.h"
-int add_northbridge_resources(struct lb_memory *mem);
-
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
struct device *riser = NULL, *firewire = NULL;
int i;
int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus;
+ int ioapic_id;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
smp_write_bus(mc, isa_bus, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ ioapic_id = 2;
+ smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
/* Legacy Interrupts */
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
/* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
-
- /* Firewire 4:0.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
+
+ /* Internal PCI bus (Firewire, PCI slot) */
if (firewire) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
}
if (riser) {
/* Old riser card */
// riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, 0x2, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
// riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, 0x2, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
// riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, 0x2, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
/* New Riser Card */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, 0x2, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, 0x2, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, 0x2, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
}
+ /* PCIe slot */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
+
/* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
return smp_next_mpe_entry(mc);
}
+/* MP table generation in coreboot is not very well designed;
+ * One of the issues is that it knows nothing about Virtual
+ * Wire mode, which everyone uses since a decade or so. This
+ * function fixes up our floating table. This spares us doing
+ * a half-baked fix of adding a new parameter to 200+ calls
+ * to smp_write_floating_table()
+ */
+static void fixup_virtual_wire(void *v)
+{
+ struct intel_mp_floating *mf = v;
+
+ mf->mpf_checksum = 0;
+ mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
+ mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
+}
+
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
+ fixup_virtual_wire(v);
return (unsigned long)smp_write_config_table(v);
}
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2007-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
+#include <console/console.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/x86/bist.h>
//
#include "lib/cbmem.c"
+#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
+
void real_main(unsigned long bist)
{
u32 reg32;
* day.
*/
if (resume_backup_memory)
- memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+ memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
#endif
}
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
hex
default 0x6886
depends on BOARD_RODA_RK886EX
+
+config HAVE_ACPI_SLIC
+ bool
+ default n
+ depends on BOARD_RODA_RK886EX
+
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
-void generate_cpu_entries(void); // from cpu/intel/speedstep
-unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
#define OLD_ACPI 0
#if OLD_ACPI
extern unsigned char AmlCode_ssdt[];
extern u32 wake_vec;
-extern u8 acpi_sleep_type;
/*
* These four macros are copied from <arch/smp/mpspec.h>, I have to do this
return current;
}
-int acpi_is_wakeup(void)
-{
- return (acpi_sleep_type == 3);
-}
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
-#include <part/init_timer.h> /* for jason_tsc_count_end */
#include "wakeup.h"
int enable_a20(void);
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
+#include <reset.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
#include <cpu/amd/model_fxx_rev.h>
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
typedef struct northbridge_intel_e7520_config config_t;
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
typedef struct northbridge_intel_i3100_config config_t;
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
typedef struct northbridge_intel_i3100_config config_t;
#include <boot/tables.h>
#include "chip.h"
#include "i945.h"
+#include <arch/coreboot_tables.h>
-int get_pcie_bar(u32 *base, u32 *len)
+static int get_pcie_bar(u32 *base, u32 *len)
{
device_t dev;
u32 pciexbar_reg;
die("No memory installed.\n");
}
- /* The chipset might be able to do this. What the heck, legacy bios
- * just beeps when a single DIMM is in the Channel 1 socket. So let's
- * not bother until someone needs this enough to cope with it.
- */
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- printk_err("Channel 0 has no memory populated. This setup is not usable. Please move the DIMM.\n");
+ printk_info("Channel 0 has no memory populated.\n");
}
}
{
int i, j, idx;
int lowest_common_cas = 0;
- int max_ram_speed;
+ int max_ram_speed = 0;
const u8 ddr2_speeds_table[] = {
0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */
if (sysinfo->banks[i] != 8)
continue;
- printk_spew("DIMM%d has 8 banks.\n");
+ printk_spew("DIMM%d has 8 banks.\n", i);
if (i & 1)
MCHBAR16(off32) |= 0x50;
reg8 |= (1 << 2);
pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
-#if C2_SELF_REFRESH_DISABLE
+#ifdef C2_SELF_REFRESH_DISABLE
if (integrated_graphics) {
printk_debug("C2 self-refresh with IGD\n");
} __attribute__ ((packed));
+void receive_enable_adjust(struct sys_info *sysinfo);
+
#endif /* RAMINIT_H */
#include <pc80/mc146818rtc.h>
-#include <part/fallback_boot.h>
+#include <fallback.h>
#ifndef CONFIG_MAX_REBOOT_CNT
#error "CONFIG_MAX_REBOOT_CNT not defined"
-#include <part/fallback_boot.h>
-
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
-#include <part/fallback_boot.h>
#include "../lib/usbdebug_direct.c"
static void early_usbdebug_direct_init(void)
#include <device/pciexp.h>
#include <arch/io.h>
#include "chip.h"
-#include <part/hard_reset.h>
+#include <reset.h>
#define PCIE_LCTL 0x50
#define PCIE_LSTS 0x52
config SOUTHBRIDGE_INTEL_I82801GX
bool
select IOAPIC
+ select USE_WATCHDOG_ON_BOOT
extern void i82801gx_enable(device_t dev);
#endif
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS 0x06
+#define SMLT 0x1b
+#define SECSTS 0x1e
+#define INTR 0x3c
+#define BCTRL 0x3e
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
+
/* PCI Configuration Space (D31:F0): LPC */
#define SERIRQ_CNTL 0x64
typedef struct southbridge_intel_i82801gx_config config_t;
-static int set_bits(u8 * port, u32 mask, u32 val)
+static int set_bits(u32 port, u32 mask, u32 val)
{
u32 reg32;
int count;
return 0;
}
-static int codec_detect(u8 * base)
+static int codec_detect(u32 base)
{
u32 reg32;
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u8 *base)
+static int wait_for_ready(u32 base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
* is non-operative
*/
-static int wait_for_valid(u8 *base)
+static int wait_for_valid(u32 base)
{
u32 reg32;
return -1;
}
-static void codec_init(struct device *dev, u8 * base, int addr)
+static void codec_init(struct device *dev, u32 base, int addr)
{
u32 reg32;
u32 *verb;
printk_debug("Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u8 * base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
static void azalia_init(struct device *dev)
{
- u8 *base;
+ u32 base;
struct resource *res;
u32 codec_mask;
u8 reg8;
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u8 *) ((u32)res->base);
+ base = (u32)res->base;
printk_debug("Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
#include <pc80/i8259.h>
#include <arch/io.h>
#include "i82801gx.h"
-#include "i82801gx_power.h"
#define NMI_OFF 0
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include "i82801gx.h"
static void pci_init(struct device *dev)
{
pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */
- pci_write_config8(dev, 0x3c, 0xff);
+ pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, 0x3e);
+ reg16 = pci_read_config16(dev, BCTRL);
reg16 &= ~(1 << 0);
reg16 &= ~(1 << 1);
- pci_write_config16(dev, 0x3e, reg16);
+ pci_write_config16(dev, BCTRL, reg16);
/* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, 0x1b);
+ reg8 = pci_read_config8(dev, SMLT);
reg8 &= 0x07;
reg8 |= (0x04 << 3);
- pci_write_config8(dev, 0x1b, reg8);
+ pci_write_config8(dev, SMLT, reg8);
/* Will this improve throughput of bus masters? */
pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
- reg16 = pci_read_config16(dev, 0x06);
+ reg16 = pci_read_config16(dev, PSTS);
//reg16 |= 0xf900;
- pci_write_config16(dev, 0x06, reg16);
+ pci_write_config16(dev, PSTS, reg16);
- reg16 = pci_read_config16(dev, 0x1e);
+ reg16 = pci_read_config16(dev, SECSTS);
// reg16 |= 0xf900;
- pci_write_config16(dev, 0x1e, reg16);
+ pci_write_config16(dev, SECSTS, reg16);
}
#undef PCI_BRIDGE_UPDATE_COMMAND
reg16 |= (1 << 6);
pci_write_config16(dev, 0x50, reg16);
-#if EVEN_MORE_DEBUG
+#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
printk_spew(" MBL = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x24);
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-#define MAINBOARD_POWER_KEEP 2
-
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
*/
#include <arch/io.h>
+#include <reset.h>
void soft_reset(void)
{
#include <device/pci.h>
#include <console/console.h>
#include <arch/io.h>
+#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
extern uint8_t smm_relocation_start, smm_relocation_end;
-void smm_relocate(void)
+static void smm_relocate(void)
{
u32 smi_en;
u16 pm1_en;
outb(0x00, 0xb2);
}
-void smm_install(void)
+static void smm_install(void)
{
/* enable the SMM memory window */
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
#include <cpu/x86/smm.h>
#include <device/pci_def.h>
#include "i82801gx.h"
-#include "i82801gx_power.h"
#define DEBUG_SMI
/* Clear any pending port changes */
res = find_resource(dev, 0x10);
base = res->base;
- reg32 = read32((u8 *)base + 0x24) | (1 << 2);
- write32((u8 *)base + 0x24, reg32);
+ reg32 = read32(base + 0x24) | (1 << 2);
+ write32(base + 0x24, reg32);
/* workaround */
reg8 = pci_read_config8(dev, 0x84);
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
+#include <watchdog.h>
void watchdog_off(void)
{
*/
#include <arch/io.h>
-#include <part/hard_reset.h>
+#include <reset.h>
#define PCI_DEV(BUS, DEV, FN) ( \
(((BUS) & 0xFFF) << 20) | \
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
#include <cpu/amd/model_fxx_rev.h>
-
-//#include "amdk8.h"
-
#include <arch/io.h>
/**
{ &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, { 0x7f8, 0 }, },
/* No 4 { 0,}, */
- { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
{ &ops, W83627THG_GPIO2,},
- { &ops, W83627THG_GPIO3,},
+ { &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },
{ &ops, W83627THG_ACPI, PNP_IRQ0, },
{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
};
echo "CONFIG_MAINBOARD_DIR=\"$VENDOR/$MAINBOARD\"" >> .config
if [ "$PAYLOAD" != "/dev/null" ]; then
echo "# CONFIG_PAYLOAD_NONE is not set" >> .config
- echo "CONFIG_PAYLOAD_ELF=\"$PAYLOAD\"" >> .config
+ echo "CONFIG_PAYLOAD_ELF=y" >> .config
+ echo "CONFIG_FALLBACK_PAYLOAD_FILE=\"$PAYLOAD\"" >> .config
fi
if [ "$loglevel" != "default" ]; then
printf "(loglevel override) "
- echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$loglevel=y"
- echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel"
- echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$loglevel=y"
- echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel"
+ echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$loglevel=y" >> .config
+ echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel" >> .config
+ echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$loglevel=y" >> .config
+ echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel" >> .config
fi
fi
ret=$?
mv .config ${build_dir}/config.build
mv .xcompile ${build_dir}/xcompile.build
- mv ..config.tmp ${build_dir}/config.deps
cd $TARGET/${VENDOR}_${MAINBOARD}
etime=`perl -e 'print time();' 2>/dev/null || date +%s`
duration=$(( $etime - $stime ))
static int is_imm32(struct triple *imm)
{
- return ((imm->op == OP_INTCONST) && (imm->u.cval <= 0xffffffffUL)) ||
+ // second condition commented out to prevent compiler warning:
+ // imm->u.cval is always 32bit unsigned, so the comparison is
+ // always true.
+ return ((imm->op == OP_INTCONST) /* && (imm->u.cval <= 0xffffffffUL) */ ) ||
(imm->op == OP_ADDRCONST);
}
projects / coreboot.git / commitdiff