2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
26 static void pci_init(struct device *dev)
31 printk_debug("Initializing ICH7 PCIe bridge.\n");
33 /* Enable Bus Master */
34 reg32 = pci_read_config32(dev, PCI_COMMAND);
35 reg32 |= PCI_COMMAND_MASTER;
36 pci_write_config32(dev, PCI_COMMAND, reg32);
38 /* Set Cache Line Size to 0x10 */
39 // This has no effect but the OS might expect it
40 pci_write_config8(dev, 0x0c, 0x10);
42 reg16 = pci_read_config16(dev, 0x3e);
43 reg16 &= ~(1 << 0); /* disable parity error response */
44 // reg16 &= ~(1 << 1); /* disable SERR */
45 reg16 |= (1 << 2); /* ISA enable */
46 pci_write_config16(dev, 0x3e, reg16);
48 /* Enable IO xAPIC on this PCIe port */
49 reg32 = pci_read_config32(dev, 0xd8);
51 pci_write_config32(dev, 0xd8, reg32);
53 /* Enable Backbone Clock Gating */
54 reg32 = pci_read_config32(dev, 0xe1);
55 reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
56 pci_write_config32(dev, 0xe1, reg32);
58 #if CONFIG_MMCONF_SUPPORT
59 /* Set VC0 transaction class */
60 reg32 = pci_mmio_read_config32(dev, 0x114);
63 pci_mmio_write_config32(dev, 0x114, reg32);
65 /* Mask completion timeouts */
66 reg32 = pci_mmio_read_config32(dev, 0x148);
68 pci_mmio_write_config32(dev, 0x148, reg32);
70 #error "MMIO needed for ICH7 PCIe"
72 /* Enable common clock configuration */
73 // Are there cases when we don't want that?
74 reg16 = pci_read_config16(dev, 0x50);
76 pci_write_config16(dev, 0x50, reg16);
79 reg32 = pci_read_config32(dev, 0x20);
80 printk_spew(" MBL = 0x%08x\n", reg32);
81 reg32 = pci_read_config32(dev, 0x24);
82 printk_spew(" PMBL = 0x%08x\n", reg32);
83 reg32 = pci_read_config32(dev, 0x28);
84 printk_spew(" PMBU32 = 0x%08x\n", reg32);
85 reg32 = pci_read_config32(dev, 0x2c);
86 printk_spew(" PMLU32 = 0x%08x\n", reg32);
89 /* Clear errors in status registers */
90 reg16 = pci_read_config16(dev, 0x06);
92 pci_write_config16(dev, 0x06, reg16);
94 reg16 = pci_read_config16(dev, 0x1e);
96 pci_write_config16(dev, 0x1e, reg16);
99 static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
101 /* NOTE: This is not the default position! */
102 if (!vendor || !device) {
103 pci_write_config32(dev, 0x94,
104 pci_read_config32(dev, 0));
106 pci_write_config32(dev, 0x94,
107 ((device & 0xffff) << 16) | (vendor & 0xffff));
111 static struct pci_operations pci_ops = {
112 .set_subsystem = pcie_set_subsystem,
115 static struct device_operations device_ops = {
116 .read_resources = pci_bus_read_resources,
117 .set_resources = pci_dev_set_resources,
118 .enable_resources = pci_bus_enable_resources,
120 .scan_bus = pci_scan_bridge,
124 /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
125 static const struct pci_driver i82801gx_pcie_port1 __pci_driver = {
127 .vendor = PCI_VENDOR_ID_INTEL,
131 /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
132 static const struct pci_driver i82801gx_pcie_port2 __pci_driver = {
134 .vendor = PCI_VENDOR_ID_INTEL,
138 /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
139 static const struct pci_driver i82801gx_pcie_port3 __pci_driver = {
141 .vendor = PCI_VENDOR_ID_INTEL,
145 /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
146 static const struct pci_driver i82801gx_pcie_port4 __pci_driver = {
148 .vendor = PCI_VENDOR_ID_INTEL,
152 /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */
153 static const struct pci_driver i82801gx_pcie_port5 __pci_driver = {
155 .vendor = PCI_VENDOR_ID_INTEL,
159 /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */
160 static const struct pci_driver i82801gx_pcie_port6 __pci_driver = {
162 .vendor = PCI_VENDOR_ID_INTEL,