src/mainboard/kontron/986lcd-m/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
  23 #define __PRE_RAM__
  24
  25 /* Configuration of the i945 driver */
  26 #define CHIPSET_I945GM 1
  27 /* Usually system firmware turns off system memory clock signals to
  28  * unused SO-DIMM slots to reduce EMI and power consumption.
  29  * However, the Kontron 986LCD-M does not like unused clock signals to
  30  * be disabled. If other similar mainboard occur, it would make sense
  31  * to make this an entry in the sysinfo structure, and pre-initialize that
  32  * structure in the mainboard's romstage.c main() function. For now a
  33  * #define will do.
  34  */
  35 #define OVERRIDE_CLOCK_DISABLE 1
  36 #define CHANNEL_XOR_RANDOMIZATION 1
  37
  38 #include <stdint.h>
  39 #include <string.h>
  40 #include <arch/io.h>
  41 #include <arch/romcc_io.h>
  42 #include <device/pci_def.h>
  43 #include <device/pnp_def.h>
  44 #include <cpu/x86/lapic.h>
  45
  46 #include "superio/winbond/w83627thg/w83627thg.h"
  47
  48 #include "option_table.h"
  49 #include "pc80/mc146818rtc_early.c"
  50
  51 #include "pc80/serial.c"
  52 #include "arch/i386/lib/console.c"
  53 #include <cpu/x86/bist.h>
  54
  55 #if CONFIG_USBDEBUG_DIRECT
  56 #define DBGP_DEFAULT 1
  57 #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
  58 #include "pc80/usbdebug_direct_serial.c"
  59 #endif
  60
  61 #include "lib/ramtest.c"
  62 #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
  63 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
  64
  65 #include "northbridge/intel/i945/udelay.c"
  66
  67 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
  68
  69 #include "southbridge/intel/i82801gx/i82801gx.h"
  70 static void setup_ich7_gpios(void)
  71 {
  72         printk_debug(" GPIOS...");
  73         /* General Registers */
  74         outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
  75         outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
  76         outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
  77         /* Output Control Registers */
  78         outl(0x00000000, DEFAULT_GPIOBASE + 0x18);      /* GPO_BLINK */
  79         /* Input Control Registers */
  80         outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);      /* GPI_INV */
  81         outl(0x000100ff, DEFAULT_GPIOBASE + 0x30);      /* GPIO_USE_SEL2 */
  82         outl(0x00000030, DEFAULT_GPIOBASE + 0x34);      /* GP_IO_SEL2 */
  83         outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
  84 }
  85
  86 #include "northbridge/intel/i945/early_init.c"
  87
  88 static inline int spd_read_byte(unsigned device, unsigned address)
  89 {
  90         return smbus_read_byte(device, address);
  91 }
  92
  93 #include "northbridge/intel/i945/raminit.h"
  94 #include "northbridge/intel/i945/raminit.c"
  95 #include "northbridge/intel/i945/reset_test.c"
  96 #include "northbridge/intel/i945/errata.c"
  97 #include "northbridge/intel/i945/debug.c"
  98
  99 static void ich7_enable_lpc(void)
 100 {
 101         // Enable Serial IRQ
 102         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
 103         // Set COM1/COM2 decode range
 104         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
 105         // Enable COM1/COM2/KBD/SuperIO1+2
 106         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
 107         // Enable HWM at 0xa00
 108         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
 109         // COM3 decode
 110         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
 111         // COM4 decode
 112         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
 113         // io 0x300 decode
 114         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
 115 }
 116
 117
 118 /* This box has two superios, so enabling serial becomes slightly excessive.
 119  * We disable a lot of stuff to make sure that there are no conflicts between
 120  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
 121  * but safe anyways" method.
 122  */
 123 static void early_superio_config_w83627thg(void)
 124 {
 125         device_t dev;
 126
 127         dev=PNP_DEV(0x2e, W83627THG_SP1);
 128         pnp_enter_ext_func_mode(dev);
 129
 130         pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
 131
 132         pnp_write_config(dev, 0x29, 0x43); // GPIO settings
 133         pnp_write_config(dev, 0x2a, 0x40); // GPIO settings
 134
 135         dev=PNP_DEV(0x2e, W83627THG_SP1);
 136         pnp_set_logical_device(dev);
 137         pnp_set_enable(dev, 0);
 138         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
 139         pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
 140         pnp_set_enable(dev, 1);
 141
 142         dev=PNP_DEV(0x2e, W83627THG_SP2);
 143         pnp_set_logical_device(dev);
 144         pnp_set_enable(dev, 0);
 145         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
 146         pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
 147         // pnp_write_config(dev, 0xf1, 4); // IRMODE0
 148         pnp_set_enable(dev, 1);
 149
 150         dev=PNP_DEV(0x2e, W83627THG_KBC);
 151         pnp_set_logical_device(dev);
 152         pnp_set_enable(dev, 0);
 153         pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
 154         pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
 155         // pnp_write_config(dev, 0xf0, 0x82);
 156         pnp_set_enable(dev, 1);
 157
 158         dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
 159         pnp_set_logical_device(dev);
 160         pnp_set_enable(dev, 0);
 161         pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
 162         pnp_set_enable(dev, 1);
 163
 164         dev=PNP_DEV(0x2e, W83627THG_GPIO2);
 165         pnp_set_logical_device(dev);
 166         pnp_set_enable(dev, 1); // Just enable it
 167
 168         dev=PNP_DEV(0x2e, W83627THG_GPIO3);
 169         pnp_set_logical_device(dev);
 170         pnp_set_enable(dev, 0);
 171         pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
 172         pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
 173         pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
 174
 175         dev=PNP_DEV(0x2e, W83627THG_FDC);
 176         pnp_set_logical_device(dev);
 177         pnp_set_enable(dev, 0);
 178
 179         dev=PNP_DEV(0x2e, W83627THG_PP);
 180         pnp_set_logical_device(dev);
 181         pnp_set_enable(dev, 0);
 182
 183         /* Enable HWM */
 184         dev=PNP_DEV(0x2e, W83627THG_HWM);
 185         pnp_set_logical_device(dev);
 186         pnp_set_enable(dev, 0);
 187         pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
 188         pnp_set_enable(dev, 1);
 189
 190         pnp_exit_ext_func_mode(dev);
 191
 192         dev=PNP_DEV(0x4e, W83627THG_SP1);
 193         pnp_enter_ext_func_mode(dev);
 194
 195         pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
 196         pnp_set_enable(dev, 0);
 197         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
 198         pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
 199         pnp_set_enable(dev, 1);
 200
 201         dev=PNP_DEV(0x4e, W83627THG_SP2);
 202         pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
 203         pnp_set_enable(dev, 0);
 204         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
 205         pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
 206         pnp_set_enable(dev, 1);
 207
 208         dev=PNP_DEV(0x4e, W83627THG_FDC);
 209         pnp_set_logical_device(dev);
 210         pnp_set_enable(dev, 0);
 211
 212         dev=PNP_DEV(0x4e, W83627THG_PP);
 213         pnp_set_logical_device(dev);
 214         pnp_set_enable(dev, 0);
 215
 216         dev=PNP_DEV(0x4e, W83627THG_KBC);
 217         pnp_set_logical_device(dev);
 218         pnp_set_enable(dev, 0);
 219         pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
 220         pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
 221
 222         pnp_exit_ext_func_mode(dev);
 223 }
 224
 225 static void rcba_config(void)
 226 {
 227         u32 reg32;
 228
 229         /* Set up virtual channel 0 */
 230         //RCBA32(0x0014) = 0x80000001;
 231         //RCBA32(0x001c) = 0x03128010;
 232
 233         /* Device 1f interrupt pin register */
 234         RCBA32(0x3100) = 0x00042210;
 235         /* Device 1d interrupt pin register */
 236         RCBA32(0x310c) = 0x00214321;
 237
 238         /* dev irq route register */
 239         RCBA16(0x3140) = 0x0132;
 240         RCBA16(0x3142) = 0x3241;
 241         RCBA16(0x3144) = 0x0237;
 242         RCBA16(0x3146) = 0x3210;
 243         RCBA16(0x3148) = 0x3210;
 244
 245         /* Enable IOAPIC */
 246         RCBA8(0x31ff) = 0x03;
 247
 248         /* Enable upper 128bytes of CMOS */
 249         RCBA32(0x3400) = (1 << 2);
 250
 251         /* Now, this is a bit ugly. As per PCI specification, function 0 of a
 252          * device always has to be implemented. So disabling ethernet port 1
 253          * would essentially disable all three ethernet ports of the mainboard.
 254          * It's possible to rename the ports to achieve compatibility to the
 255          * PCI spec but this will confuse all (static!) tables containing
 256          * interrupt routing information.
 257          * To avoid this, we enable (unused) port 6 and swap it with port 1
 258          * in the case that ethernet port 1 is disabled. Since no devices
 259          * are connected to that port, we don't have to worry about interrupt
 260          * routing.
 261          */
 262         int port_shuffle = 0;
 263
 264         /* Disable unused devices */
 265         reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
 266         reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
 267
 268         if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) {
 269                 printk_debug("Disabling ethernet adapter 1.\n");
 270                 reg32 |= FD_PCIE1;
 271         }
 272         if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) {
 273                 printk_debug("Disabling ethernet adapter 2.\n");
 274                 reg32 |= FD_PCIE2;
 275         } else {
 276                 if (reg32 & FD_PCIE1)
 277                         port_shuffle = 1;
 278         }
 279         if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) {
 280                 printk_debug("Disabling ethernet adapter 3.\n");
 281                 reg32 |= FD_PCIE3;
 282         } else {
 283                 if (reg32 & FD_PCIE1)
 284                         port_shuffle = 1;
 285         }
 286
 287         if (port_shuffle) {
 288                 /* Enable PCIE6 again */
 289                 reg32 &= ~FD_PCIE6;
 290                 /* Swap PCIE6 and PCIE1 */
 291                 RCBA32(RPFN) = 0x00043215;
 292         }
 293
 294         reg32 |= 1;
 295
 296         RCBA32(0x3418) = reg32;
 297
 298         /* Enable PCIe Root Port Clock Gate */
 299         // RCBA32(0x341c) = 0x00000001;
 300 }
 301
 302 static void early_ich7_init(void)
 303 {
 304         uint8_t reg8;
 305         uint32_t reg32;
 306
 307         // program secondary mlt XXX byte?
 308         pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 309
 310         // reset rtc power status
 311         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
 312         reg8 &= ~(1 << 2);
 313         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 314
 315         // usb transient disconnect
 316         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
 317         reg8 |= (3 << 0);
 318         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
 319
 320         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
 321         reg32 |= (1 << 29) | (1 << 17);
 322         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
 323
 324         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
 325         reg32 |= (1 << 31) | (1 << 27);
 326         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 327
 328         RCBA32(0x0088) = 0x0011d000;
 329         RCBA16(0x01fc) = 0x060f;
 330         RCBA32(0x01f4) = 0x86000040;
 331         RCBA32(0x0214) = 0x10030549;
 332         RCBA32(0x0218) = 0x00020504;
 333         RCBA8(0x0220) = 0xc5;
 334         reg32 = RCBA32(0x3410);
 335         reg32 |= (1 << 6);
 336         RCBA32(0x3410) = reg32;
 337         reg32 = RCBA32(0x3430);
 338         reg32 &= ~(3 << 0);
 339         reg32 |= (1 << 0);
 340         RCBA32(0x3430) = reg32;
 341         RCBA32(0x3418) |= (1 << 0);
 342         RCBA16(0x0200) = 0x2008;
 343         RCBA8(0x2027) = 0x0d;
 344         RCBA16(0x3e08) |= (1 << 7);
 345         RCBA16(0x3e48) |= (1 << 7);
 346         RCBA32(0x3e0e) |= (1 << 7);
 347         RCBA32(0x3e4e) |= (1 << 7);
 348
 349         // next step only on ich7m b0 and later:
 350         reg32 = RCBA32(0x2034);
 351         reg32 &= ~(0x0f << 16);
 352         reg32 |= (5 << 16);
 353         RCBA32(0x2034) = reg32;
 354 }
 355
 356 #if CONFIG_USE_FALLBACK_IMAGE == 1
 357 #include "southbridge/intel/i82801gx/cmos_failover.c"
 358 #endif
 359
 360 #include <cbmem.h>
 361
 362 // Now, this needs to be included because it relies on the symbol
 363 // __PRE_RAM__ being set during CAR stage (in order to compile the
 364 // BSS free versions of the functions). Either rewrite the code
 365 // to be always BSS free, or invent a flag that's better suited than
 366 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
 367 //
 368 #include "lib/cbmem.c"
 369
 370 void real_main(unsigned long bist)
 371 {
 372         u32 reg32;
 373         int boot_mode = 0;
 374
 375         if (bist == 0) {
 376                 enable_lapic();
 377         }
 378
 379         ich7_enable_lpc();
 380         early_superio_config_w83627thg();
 381
 382         /* Set up the console */
 383         uart_init();
 384
 385 #if CONFIG_USBDEBUG_DIRECT
 386         i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
 387         early_usbdebug_direct_init();
 388 #endif
 389
 390         console_init();
 391
 392         /* Halt if there was a built in self test failure */
 393         report_bist_failure(bist);
 394
 395         if (MCHBAR16(SSKPD) == 0xCAFE) {
 396                 printk_debug("soft reset detected.\n");
 397                 boot_mode = 1;
 398         }
 399
 400         /* Perform some early chipset initialization required
 401          * before RAM initialization can work
 402          */
 403         i945_early_initialization();
 404
 405         /* Read PM1_CNT */
 406         reg32 = inl(DEFAULT_PMBASE + 0x04);
 407         printk_debug("PM1_CNT: %08x\n", reg32);
 408         if (((reg32 >> 10) & 7) == 5) {
 409 #if CONFIG_HAVE_ACPI_RESUME
 410                 printk_debug("Resume from S3 detected.\n");
 411                 boot_mode = 2;
 412                 /* Clear SLP_TYPE. This will break stage2 but
 413                  * we care for that when we get there.
 414                  */
 415                 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 416
 417 #else
 418                 printk_debug("Resume from S3 detected, but disabled.\n");
 419 #endif
 420         }
 421
 422         /* Enable SPD ROMs and DDR-II DRAM */
 423         enable_smbus();
 424
 425 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 426         dump_spd_registers();
 427 #endif
 428
 429         sdram_initialize(boot_mode);
 430
 431         /* Perform some initialization that must run before stage2 */
 432         early_ich7_init();
 433
 434         /* This should probably go away. Until now it is required
 435          * and mainboard specific
 436          */
 437         rcba_config();
 438
 439         /* Chipset Errata! */
 440         fixup_i945_errata();
 441
 442         /* Initialize the internal PCIe links before we go into stage2 */
 443         i945_late_initialization();
 444
 445 #if !CONFIG_HAVE_ACPI_RESUME
 446 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 447 #if defined(DEBUG_RAM_SETUP)
 448         sdram_dump_mchbar_registers();
 449 #endif
 450
 451         {
 452                 /* This will not work if TSEG is in place! */
 453                 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 454
 455                 printk_debug("TOM: 0x%08x\n", tom);
 456                 ram_check(0x00000000, 0x000a0000);
 457                 //ram_check(0x00100000, tom);
 458         }
 459 #endif
 460 #endif
 461
 462         MCHBAR16(SSKPD) = 0xCAFE;
 463
 464 #if CONFIG_HAVE_ACPI_RESUME
 465         /* Start address of high memory tables */
 466         unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
 467
 468         /* If there is no high memory area, we didn't boot before, so
 469          * this is not a resume. In that case we just create the cbmem toc.
 470          */
 471         if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
 472                 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 473
 474                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 475                  * through stage 2. We could keep stuff like stack and heap in high tables
 476                  * memory completely, but that's a wonderful clean up task for another
 477                  * day.
 478                  */
 479                 if (resume_backup_memory)
 480                         memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 481
 482                 /* Magic for S3 resume */
 483                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
 484         }
 485 #endif
 486 }
 487
 488 #include "cpu/intel/model_6ex/cache_as_ram_disable.c"