From: Uwe Hermann Date: Wed, 13 Oct 2010 08:21:44 +0000 (+0000) Subject: Convert all Intel i810 boards to CAR. X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=commitdiff_plain;h=ab50d62ea6867712eca79e9f0770d6ac35f72ce1 Convert all Intel i810 boards to CAR. - Drop "select ROMCC" from the boards, as well as early_mtrr stuff. - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables. - In socket_PGA370/Makefile.inc add: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Other smaller related fixes. Abuild-tested and boot-tested on MSI MS-6178. Signed-off-by: Uwe Hermann Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index 1805e6a29..bfabfb847 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -21,10 +21,22 @@ config CPU_INTEL_SOCKET_PGA370 bool select MMX select UDELAY_TSC + select CACHE_AS_RAM + +if CPU_INTEL_SOCKET_PGA370 # Not all CPUs for Socket 370 can do SSE2 config SSE2 bool default n - depends on CPU_INTEL_SOCKET_PGA370 + +config DCACHE_RAM_BASE + hex + default 0xc0000 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + +endif diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc index c857bcee4..8e590506e 100644 --- a/src/cpu/intel/socket_PGA370/Makefile.inc +++ b/src/cpu/intel/socket_PGA370/Makefile.inc @@ -27,3 +27,5 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode +cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc + diff --git a/src/cpu/intel/socket_PGA370/socket_PGA370.c b/src/cpu/intel/socket_PGA370/socket_PGA370.c index 1fc62ba76..fffd983a4 100644 --- a/src/cpu/intel/socket_PGA370/socket_PGA370.c +++ b/src/cpu/intel/socket_PGA370/socket_PGA370.c @@ -1,7 +1,6 @@ #include #include "chip.h" - struct chip_operations cpu_intel_socket_PGA370_ops = { CHIP_NAME("Socket PGA370 CPU") }; diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index afe6a0dee..68ac160b3 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 51d97a37d..402789c0a 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -26,31 +26,21 @@ #include #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" /* #include "northbridge/intel/i82810/debug.c" */ +#include -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +void main(unsigned long bist) +{ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -60,6 +50,4 @@ static void main(unsigned long bist) sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index bc952dccb..4e461923a 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_LPC47B272 - select ROMCC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select UDELAY_TSC diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 30d6a8721..e4c551eb6 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -26,42 +26,28 @@ #include #include #include -#include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) - #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "northbridge/intel/i82810/raminit.c" #include "northbridge/intel/i82810/debug.c" +#include -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) +void main(unsigned long bist) +{ lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - enable_smbus(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - - /* dump_spd_registers(); */ - + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - - /* Check RAM. */ - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index eecae4d4b..7d377f471 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_ITE_IT8712F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index f84ff465c..b899d938a 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -27,37 +27,21 @@ #include #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/ite/it8712f/it8712f_early_serial.c" - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" #include "northbridge/intel/i82810/debug.c" +#include -/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) +void main(unsigned long bist) { -} - -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); - it8712f_24mhz_clkin(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter - mb_gpio_init(); uart_init(); console_init(); report_bist_failure(bist); @@ -67,6 +51,4 @@ static void main(unsigned long bist) sdram_set_spd_registers(); sdram_enable(); dump_spd_registers(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index 7186dae60..5fab95a2c 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_NSC_PC87360 - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index 50f59df2b..39cb2669c 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -26,40 +26,30 @@ #include #include #include -#include "lib/ramtest.c" /* TODO: It's a PC87364 actually! */ #include "superio/nsc/pc87360/pc87360_early_serial.c" /* TODO: It's i810E actually! */ #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" +#include /* TODO: It's a PC87364 actually! */ #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* TODO: It's a PC87364 actually! */ pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); console_init(); - enable_smbus(); - report_bist_failure(bist); - /* dump_spd_registers(); */ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 34371f583..94f117053 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -35,21 +35,15 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "gpio.c" +#include "northbridge/intel/i82810/raminit.c" +/* #include "northbridge/intel/i82810/debug.c" */ #include #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ - void main(unsigned long bist) { - /* Set southbridge and superio gpios */ + /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -62,6 +56,4 @@ void main(unsigned long bist) sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index 77ed6e915..fac565e97 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index bbf87568c..1a2d7c4f0 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -26,31 +26,21 @@ #include #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" - -#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" /* #include "northbridge/intel/i82810/debug.c" */ +#include -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) +void main(unsigned long bist) +{ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,6 +51,4 @@ static void main(unsigned long bist) sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index fc8f425d2..4b6d4e46d 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 select HAVE_MAINBOARD_RESOURCES diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 6d25c4d2e..5aab983c5 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -26,23 +26,19 @@ #include #include #include -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME */ outb(0x87, 0x2e); outb(0x87, 0x2e); @@ -61,6 +57,4 @@ static void main(unsigned long bist) sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index d0f29bb25..55050c000 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index b9a3744e3..8f71cc9d4 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -26,34 +26,25 @@ #include #include #include -#include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "northbridge/intel/i82810/raminit.c" +#include #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - enable_smbus(); - report_bist_failure(bist); - /* dump_spd_registers(); */ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c index 5bddbb60a..55af01bc2 100644 --- a/src/northbridge/intel/i82810/debug.c +++ b/src/northbridge/intel/i82810/debug.c @@ -1,6 +1,6 @@ - static void dump_spd_registers(void) { +#if CONFIG_DEBUG_RAM_SETUP int i; print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { @@ -32,4 +32,5 @@ static void dump_spd_registers(void) print_debug("\n"); } } +#endif } diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index 9927cb65c..3ddc8a02e 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -137,6 +137,11 @@ struct dimm_info { SDRAM configuration functions. -----------------------------------------------------------------------------*/ +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + /** * Send the specified RAM command to all DIMMs. *