Add support for RAM-less multi-processor init

For a hyper-threading processor, enabling cache requires that both the
BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram
implementation, partial multi-processor initialisation precedes
raminit and AP CPUs' 16bit entry must be run from ROM.

The AP CPU can only start execute real-mode code at a 4kB aligned
address below 1MB. The protected mode entry code for AP is identical
with the BSP code, which is already located at the top of bootblock.
This patch takes the simplest approach and aligns the bootblock
16 bit entry at highest possible 4kB boundary below 1MB.

The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR
used by the CAR code in romstage. Adress is not expected to ever
change, but if it does, link will fail.

Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/454
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
index 83e5eb343200024b9d1e70463f1f88de86309288..61c3d2a35ba33917dec4ca41e585c537fde4c5ce 100644 (file)
--- a/src/arch/x86/init/ldscript_failover.lb
+++ b/src/arch/x86/init/ldscript_failover.lb
@@ -29,17 +29,18 @@ MEMORY {
 TARGET(binary)
 SECTIONS
 {
 TARGET(binary)
 SECTIONS
 {

-       /* Align .rom to next 4 byte boundary so no pad byte appears
-        * between _rom and _start.
+       /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
+        * with Startup IPI message without RAM.

         */
        .bogus ROMLOC_MIN : {
         */
        .bogus ROMLOC_MIN : {

-               . = ALIGN(4);
+               . = ALIGN(4096);

                ROMLOC = .;
        } >rom = 0xff
 
        /* This section might be better named .setup */
        .rom ROMLOC : {
                _rom = .;
                ROMLOC = .;
        } >rom = 0xff
 
        /* This section might be better named .setup */
        .rom ROMLOC : {
                _rom = .;

+               ap_sipi_vector = .;

                *(.rom.text);
                *(.rom.data);
                *(.rom.data.*);
                *(.rom.text);
                *(.rom.data);
                *(.rom.data.*);


@@ -51,7 +52,11 @@ SECTIONS
         * may cause the total size of a section to change when the start
         * address gets applied.
         */
         * may cause the total size of a section to change when the start
         * address gets applied.
         */

-       ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
+       ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096;
+
+       /* Post-check proper SIPI vector. */
+       _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment");
+       _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR");

 
        /DISCARD/ : {
                *(.comment)
 
        /DISCARD/ : {
                *(.comment)

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 6e6518618b85add382f81b1a50079ce0b6511ddf..0bdef347f0406fcba28ccb0a8306ec695ea1eda5 100644 (file)
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -31,6 +31,12 @@ config SMP
          This option is used to enable certain functions to make coreboot
          work correctly on symmetric multi processor (SMP) systems.
 
          This option is used to enable certain functions to make coreboot
          work correctly on symmetric multi processor (SMP) systems.
 

+config AP_SIPI_VECTOR
+       hex
+       default 0xfffff000
+       help
+         This must equal address of ap_sipi_vector from bootblock build.
+                 

 config MMX
        bool
        help
 config MMX
        bool
        help