3 source src/cpu/amd/Kconfig
4 source src/cpu/intel/Kconfig
5 source src/cpu/via/Kconfig
6 source src/cpu/x86/Kconfig
12 config DCACHE_RAM_BASE
15 config DCACHE_RAM_SIZE
18 config DCACHE_RAM_GLOBAL_VAR_SIZE
22 config MAX_PHYSICAL_CPUS
28 default y if MAX_CPUS != 1
31 This option is used to enable certain functions to make coreboot
32 work correctly on symmetric multi processor (SMP) systems.
38 This must equal address of ap_sipi_vector from bootblock build.
43 Select MMX in your socket or model Kconfig if your CPU has MMX
44 streaming SIMD instructions. ROMCC can build more efficient
45 code if it can spill to MMX registers.
50 Select SSE in your socket or model Kconfig if your CPU has SSE
51 streaming SIMD instructions. ROMCC can build more efficient
52 code if it can spill to SSE (aka XMM) registers.
58 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
59 streaming SIMD instructions. Some parts of coreboot can be built
60 with more efficient code if SSE2 instructions are available.
66 Unset this if you don't want the MTRR code to use