src/southbridge/amd/sb600/lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pnp.h>
  24 #include <device/pci_ids.h>
  25 #include <device/pci_ops.h>
  26 #include <pc80/mc146818rtc.h>
  27 #include <pc80/isa-dma.h>
  28 #include <bitops.h>
  29 #include <arch/io.h>
  30 #include <arch/ioapic.h>
  31 #include "sb600.h"
  32
  33 static void lpc_init(device_t dev)
  34 {
  35         u8 byte;
  36         u32 dword;
  37         device_t sm_dev;
  38
  39         /* Enable the LPC Controller */
  40         sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
  41         dword = pci_read_config32(sm_dev, 0x64);
  42         dword |= 1 << 20;
  43         pci_write_config32(sm_dev, 0x64, dword);
  44
  45         /* Initialize isa dma */
  46         isa_dma_init();
  47
  48         /* RPR 7.2 Enable DMA transaction on the LPC bus */
  49         byte = pci_read_config8(dev, 0x40);
  50         byte |= (1 << 2);
  51         pci_write_config8(dev, 0x40, byte);
  52
  53         /* RPR 7.3 Disable the timeout mechanism on LPC */
  54         byte = pci_read_config8(dev, 0x48);
  55         byte &= ~(1 << 7);
  56         pci_write_config8(dev, 0x48, byte);
  57
  58         /* RPR 7.5 Disable LPC MSI Capability */
  59         byte = pci_read_config8(dev, 0x78);
  60         byte &= ~(1 << 1);
  61         pci_write_config8(dev, 0x78, byte);
  62
  63 }
  64
  65 static void sb600_lpc_read_resources(device_t dev)
  66 {
  67         struct resource *res;
  68
  69         /* Get the normal pci resources of this device */
  70         pci_dev_read_resources(dev);    /* We got one for APIC, or one more for TRAP */
  71
  72         pci_get_resource(dev, 0xA0); /* SPI ROM base address */
  73
  74         /* Add an extra subtractive resource for both memory and I/O. */
  75         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  76         res->base = 0;
  77         res->size = 0x1000;
  78         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
  79                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  80
  81         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  82         res->base = 0xff800000;
  83         res->size = 0x00800000; /* 8 MB for flash */
  84         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
  85                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  86
  87         res = new_resource(dev, 3); /* IOAPIC */
  88         res->base = IO_APIC_ADDR;
  89         res->size = 0x00001000;
  90         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  91
  92         compact_resources(dev);
  93 }
  94
  95 /**
  96  * @brief Enable resources for children devices
  97  *
  98  * @param dev the device whos children's resources are to be enabled
  99  *
 100  */
 101 static void sb600_lpc_enable_childrens_resources(device_t dev)
 102 {
 103         struct bus *link;
 104         u32 reg, reg_x;
 105         int var_num = 0;
 106         u16 reg_var[3] = {0x0, 0x0, 0x0};
 107         u8 wiosize = pci_read_config8(dev, 0x74);
 108
 109         reg = pci_read_config32(dev, 0x44);
 110         reg_x = pci_read_config32(dev, 0x48);
 111
 112         for (link = dev->link_list; link; link = link->next) {
 113                 device_t child;
 114                 for (child = link->children; child;
 115                      child = child->sibling) {
 116                         if (child->enabled
 117                             && (child->path.type == DEVICE_PATH_PNP)) {
 118                                 struct resource *res;
 119                                 for (res = child->resource_list; res; res = res->next) {
 120                                         u32 base, end;  /*  don't need long long */
 121                                         if (!(res->flags & IORESOURCE_IO))
 122                                                 continue;
 123                                         base = res->base;
 124                                         end = resource_end(res);
 125                                         printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n",
 126                                              dev_path(child), base, end);
 127                                         switch (base) {
 128                                         case 0x60:      /*  KB */
 129                                         case 0x64:      /*  MS */
 130                                                 reg |= (1 << 29);
 131                                                 break;
 132                                         case 0x3f8:     /*  COM1 */
 133                                                 reg |= (1 << 6);
 134                                                 break;
 135                                         case 0x2f8:     /*  COM2 */
 136                                                 reg |= (1 << 7);
 137                                                 break;
 138                                         case 0x378:     /*  Parallel 1 */
 139                                                 reg |= (1 << 0);
 140                                                 reg |= (1 << 1); /* + 0x778 for ECP */
 141                                                 break;
 142                                         case 0x3f0:     /*  FD0 */
 143                                                 reg |= (1 << 26);
 144                                                 break;
 145                                         case 0x220:     /*  Audio 0 */
 146                                                 reg |= (1 << 8);
 147                                                 break;
 148                                         case 0x300:     /*  Midi 0 */
 149                                                 reg |= (1 << 18);
 150                                                 break;
 151                                         case 0x400:
 152                                                 reg_x |= (1 << 16);
 153                                                 break;
 154                                         case 0x480:
 155                                                 reg_x |= (1 << 17);
 156                                                 break;
 157                                         case 0x500:
 158                                                 reg_x |= (1 << 18);
 159                                                 break;
 160                                         case 0x580:
 161                                                 reg_x |= (1 << 19);
 162                                                 break;
 163                                         case 0x4700:
 164                                                 reg_x |= (1 << 22);
 165                                                 break;
 166                                         case 0xfd60:
 167                                                 reg_x |= (1 << 23);
 168                                                 break;
 169                                         default:
 170                                                 if (var_num >= 3)
 171                                                         continue;       /* only 3 var ; compact them ? */
 172                                                 switch (var_num) {
 173                                                 case 0:
 174                                                         reg_x |= (1 << 2);
 175                                                         if ((end - base) < 16)
 176                                                                 wiosize |= (1 << 0);
 177                                                         break;
 178                                                 case 1:
 179                                                         reg_x |= (1 << 24);
 180                                                         if ((end - base) < 16)
 181                                                                 wiosize |= (1 << 2);
 182                                                         break;
 183                                                 case 2:
 184                                                         reg_x |= (1 << 25);
 185                                                         reg_x |= (1 << 24);
 186                                                         if ((end - base) < 16)
 187                                                                 wiosize |= (1 << 3);
 188                                                         break;
 189                                                 }
 190                                                 reg_var[var_num++] =
 191                                                     base & 0xffff;
 192                                         }
 193                                 }
 194                         }
 195                 }
 196         }
 197         pci_write_config32(dev, 0x44, reg);
 198         pci_write_config32(dev, 0x48, reg_x);
 199         /* Set WideIO for as many IOs found (fall through is on purpose) */
 200         switch (var_num) {
 201         case 2:
 202                 pci_write_config16(dev, 0x90, reg_var[2]);
 203         case 1:
 204                 pci_write_config16(dev, 0x66, reg_var[1]);
 205         case 0:
 206                 pci_write_config16(dev, 0x64, reg_var[0]);
 207                 break;
 208         }
 209         pci_write_config8(dev, 0x74, wiosize);
 210 }
 211
 212 static void sb600_lpc_enable_resources(device_t dev)
 213 {
 214         pci_dev_enable_resources(dev);
 215         sb600_lpc_enable_childrens_resources(dev);
 216 }
 217
 218 static struct pci_operations lops_pci = {
 219         .set_subsystem = pci_dev_set_subsystem,
 220 };
 221
 222 static struct device_operations lpc_ops = {
 223         .read_resources = sb600_lpc_read_resources,
 224         .set_resources = pci_dev_set_resources,
 225         .enable_resources = sb600_lpc_enable_resources,
 226         .init = lpc_init,
 227         .scan_bus = scan_static_bus,
 228         /* .enable           = sb600_enable, */
 229         .ops_pci = &lops_pci,
 230 };
 231 static const struct pci_driver lpc_driver __pci_driver = {
 232         .ops = &lpc_ops,
 233         .vendor = PCI_VENDOR_ID_ATI,
 234         .device = PCI_DEVICE_ID_ATI_SB600_LPC,
 235 };