We call this cache as ram everywhere, so let's call it the same in Kconfig
[coreboot.git] / src / mainboard / iei / pcisa-lx-800-r10 / Kconfig
1 if BOARD_IEI_PCISA_LX_800_R10
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_LX
7         select NORTHBRIDGE_AMD_LX
8         select SOUTHBRIDGE_AMD_CS5536
9         select SUPERIO_WINBOND_W83627HF
10         select HAVE_PIRQ_TABLE
11         select PIRQ_ROUTE
12         select CACHE_AS_RAM
13         select BOARD_ROMSIZE_KB_256
14
15 config MAINBOARD_DIR
16         string
17         default iei/pcisa-lx-800-r10
18
19 config MAINBOARD_PART_NUMBER
20         string
21         default "PCISA-LX-800-R10"
22
23 config IRQ_SLOT_COUNT
24         int
25         default 9
26
27 config RAMBASE
28         hex
29         default 0x4000
30
31 endif # BOARD_IEI_PCISA_LX_800_R10