2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
25 #include <console/console.h>
27 #if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \
28 !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \
29 !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \
30 !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \
31 !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \
32 !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR))
33 #error "you must supply these values in your mainboard-specific Kconfig file"
36 static void ti_pci1x2y_init(struct device *dev)
38 printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
40 /* Command (offset 04) */
41 pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR);
42 /* Cache Line Size (offset 0x0C) */
43 pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR);
44 /* CardBus latency timer (offset 0x1B) */
45 pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR);
46 /* Bridge control (offset 0x3E) */
47 pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR);
49 * Enable change sub-vendor ID. Clear the bit 5 to enable to write
50 * to the sub-vendor/device ids at 40 and 42.
52 pci_write_config32(dev, 0x80, 0x10);
53 pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA);
54 /* Now write the correct value for SCR. */
55 /* System control (offset 0x80) */
56 pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR);
57 /* Multifunction routing */
58 pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR);
59 /* Set the device control register (0x92) accordingly. */
60 pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
63 static struct device_operations ti_pci1x2y_ops = {
64 .read_resources = NULL, //pci_dev_read_resources,
65 .set_resources = pci_dev_set_resources,
66 .enable_resources = pci_dev_enable_resources,
67 .init = ti_pci1x2y_init,
71 static const struct pci_driver ti_pci1225_driver __pci_driver = {
72 .ops = &ti_pci1x2y_ops,
73 .vendor = PCI_VENDOR_ID_TI,
74 .device = PCI_DEVICE_ID_TI_1225,
77 static const struct pci_driver ti_pci1420_driver __pci_driver = {
78 .ops = &ti_pci1x2y_ops,
79 .vendor = PCI_VENDOR_ID_TI,
80 .device = PCI_DEVICE_ID_TI_1420,
83 static const struct pci_driver ti_pci1520_driver __pci_driver = {
84 .ops = &ti_pci1x2y_ops,
85 .vendor = PCI_VENDOR_ID_TI,
86 .device = PCI_DEVICE_ID_TI_1520,