2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/device.h>
22 #include <device/pci_def.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <console/console.h>
28 * The following should be set in the mainboard-specific Kconfig file.
30 #if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \
31 !defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \
32 !defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION))
33 #error "you must supply these values in your mainboard-specific Kconfig file"
36 /* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */
37 /* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */
38 /* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
41 * This driver take the values from Kconfig and load them in the registers
43 static void dec_21143_enable( device_t dev )
45 printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n");
46 // Command and Status Configuration Register (Offset 0x04)
47 pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION );
48 printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) );
49 // Cache Line Size Register (Offset 0x0C)
50 pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE );
51 printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) );
52 // Expansion ROM Base Address Register (Offset 0x30)
53 pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS );
54 printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) );
58 static struct device_operations dec_21143_ops = {
59 .read_resources = pci_dev_read_resources,
60 .set_resources = pci_dev_set_resources,
61 .enable_resources = pci_dev_enable_resources,
62 .init = dec_21143_enable,
66 static const struct pci_driver dec_21143_driver __pci_driver = {
67 .ops = &dec_21143_ops,
68 .vendor = PCI_VENDOR_ID_DEC,
69 .device = PCI_DEVICE_ID_DEC_21142,