2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Tyan Computer
5 * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
6 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <arch/romcc_io.h>
25 #include <console/console.h>
26 #include <device/pci_ids.h>
27 #include <device/pci_def.h>
29 #include "i82801bx_smbus.h"
31 int smbus_read_byte(u8 device, u8 address);
33 void enable_smbus(void)
37 /* Set the SMBus device statically (D31:F3). */
38 dev = PCI_DEV(0x0, 0x1f, 0x3);
40 /* Set SMBus I/O base. */
41 pci_write_config32(dev, SMB_BASE,
42 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
44 /* Set SMBus enable. */
45 pci_write_config8(dev, HOSTC, HST_EN);
47 /* Set SMBus I/O space enable. */
48 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
50 /* Disable interrupt generation. */
51 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
53 /* Clear any lingering errors, so transactions can run. */
54 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
56 print_debug("SMBus controller enabled\n");
59 int smbus_read_byte(u8 device, u8 address)
61 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);