Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/Kconfig b/src/Kconfig
index a06b43b1573e041532e871b58f4cdfad405e4e8d..a70a773e27a23b2c5242f379b42f82b2854d4380 100644 (file)
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -134,9 +134,9 @@ config MMCONF_SUPPORT
        bool
        default n
 
-config LB_MEM_TOPK
+config RAMTOP
        hex
-       default 0x800
+       default 0x200000
 
 config COMPRESSED_PAYLOAD_LZMA
        bool

diff --git a/src/config/Options.lb b/src/config/Options.lb
index cd1dc767313c2f3f07a46d9cc85822618c44df91..d264c5985e0ad4da0f3b4e5e34fc92958d9651ae 100644 (file)
--- a/src/config/Options.lb
+++ b/src/config/Options.lb
@@ -360,11 +360,11 @@ define CONFIG_UNCOMPRESSED
        export always
        comment "Set for uncompressed image"
 end
-define CONFIG_LB_MEM_TOPK
+define CONFIG_RAMTOP
        format "%d"
-       default 2048
+       default 2048*1024
        export always
-       comment "Kilobytes of memory to initialized before executing code from RAM"
+       comment "Highest RAM that coreboot_ram will use"
 end
 define CONFIG_HAVE_OPTION_TABLE
        default 0

diff --git a/src/config/coreboot_ram.ld b/src/config/coreboot_ram.ld
index 5e988ffeafbdda35831e15d9a36db6fa23a25466..afdf8a5522285b17970bcdd35897ed423430a89e 100644 (file)
--- a/src/config/coreboot_ram.ld
+++ b/src/config/coreboot_ram.ld
@@ -103,8 +103,8 @@ SECTIONS
        _stack = .;
        .stack . : {
                /* Reserve a stack for each possible cpu */
-               /* the stack for ap will be put after pgtbl in 1M to CONFIG_LB_MEM_TOPK range when VGA and ROM_RUN and CONFIG_LB_MEM_TOPK>1024*/
-               . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
+               /* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/
+               . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
        }
        _estack = .;
         _heap = .;
@@ -120,9 +120,9 @@ SECTIONS
        _ram_seg = _text; 
        _eram_seg = _eheap;
 
-       _bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK");
+       _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "please increase CONFIG_RAMTOP");
 
-        _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set CONFIG_RAMBASE more than 1M");
+        _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE more than 1M");
 
        /DISCARD/ : {
                *(.comment)

diff --git a/src/console/usbdebug_direct_console.c b/src/console/usbdebug_direct_console.c
index 388715cff859a4c489556daaf5005fe0d30e44d2..d1006598b07adca030f25902e8dd96843c2695a5 100644 (file)
--- a/src/console/usbdebug_direct_console.c
+++ b/src/console/usbdebug_direct_console.c
@@ -53,7 +53,7 @@ static void dbgp_init(void)
         * debug_info data structure to our version defined above. */
 
        dbg_infox = (struct ehci_debug_info *)
-               ((CONFIG_LB_MEM_TOPK << 10) - sizeof(struct ehci_debug_info));
+               ((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
 
        memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info));
 }

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 5641682b3747446e05ffe7c7e264f74c3c57bd92..dcd357438dd3746e1d4cf2c222c3ca7edb8bfdb9 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -246,7 +246,7 @@ clear_fixed_var_mtrr_out:
        /* enable memory access for first MBs using top_mem */
        movl    $TOP_MEM, %ecx
        xorl    %edx, %edx
-       movl    $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
+       movl    $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
        wrmsr
 #endif /*  CONFIG_USE_FAILOVER_IMAGE == 1*/
 

diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c
index 0b50480142b0bb7ea8ef3766d94ce422665cce0d..624e0fea8335806c441314cd30bb8bd322ee5624 100644 (file)
--- a/src/cpu/amd/car/clear_init_ram.c
+++ b/src/cpu/amd/car/clear_init_ram.c
@@ -9,15 +9,15 @@ static void __attribute__((noinline)) clear_init_ram(void)
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
        /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
-       clear_memory( CONFIG_RAMBASE,  (CONFIG_LB_MEM_TOPK << 10) -  CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
+       clear_memory( CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
 #else
-        clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE));
+        clear_memory(0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
 #endif
 }
 
 /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
 static void set_init_ram_access(void)
 {
-       set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, MTRR_TYPE_WRBACK);
+       set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 }
 

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index c42e8339cb3764d2deaf64728eee4a5727bea86b..611f78d5eae2dac19d0f9db1379d3f03762e1177 100644 (file)
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -56,13 +56,13 @@ static void post_cache_as_ram(void)
        print_debug_pcar("testx = ", testx);
 
        /* copy data from cache as ram to 
-               ram need to set CONFIG_LB_MEM_TOPK to 2048 and use var mtrr instead.
+               ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
         */
-#if CONFIG_LB_MEM_TOPK <= 1024
-        #error "You need to set CONFIG_LB_MEM_TOPK greater than 1024"
+#if CONFIG_RAMTOP <= 0x100000
+        #error "You need to set CONFIG_RAMTOP greater than 1M"
 #endif
        
-       set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */
+       set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
        print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
@@ -76,14 +76,14 @@ static void post_cache_as_ram(void)
         );
 #endif
 
-        memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
-//        dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+        memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
+//        dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
         __asm__ volatile (
                 /* set new esp */ /* before CONFIG_RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
+                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
         ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
 #if 0
         __asm__ volatile (
@@ -102,10 +102,10 @@ static void post_cache_as_ram(void)
        disable_cache_as_ram_bsp();  
 
         print_debug("Clearing initial memory region: ");
-        clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
+        clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
         print_debug("Done\r\n");
 
-//     dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+//     dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
 #ifndef CONFIG_MEM_TRAIN_SEQ
 #define CONFIG_MEM_TRAIN_SEQ 0
@@ -113,7 +113,7 @@ static void post_cache_as_ram(void)
         set_sysinfo_in_ram(1); // So other core0 could start to train mem
 
 #if CONFIG_MEM_TRAIN_SEQ == 1
-//     struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+//     struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         // wait for ap memory to trained
 //        wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c

diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index d183bf89bc75f13e8ad63991608a697e6e5a000b..8b680980192cf1f036fd54762736a65cfe1ea3f4 100644 (file)
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -33,7 +33,7 @@
 void cpus_ready_for_init(void)
 {
 #if CONFIG_MEM_TRAIN_SEQ == 1
-        struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
         // wait for ap memory to trained
         wait_all_core0_mem_trained(sysinfox);
 #endif
@@ -182,7 +182,7 @@ static void set_init_ecc_mtrrs(void)
        msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
        wrmsr(MTRRphysBase_MSR(0), msr);
        msr.hi = 0x000000ff;
-       msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
+       msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
        wrmsr(MTRRphysMask_MSR(0), msr);
 
        /* Set the default type to write combining */
@@ -308,8 +308,8 @@ static void init_ecc_memory(unsigned node_id)
 
        /* Don't start too early */
        begink = startk;
-       if (begink < CONFIG_LB_MEM_TOPK) { 
-               begink = CONFIG_LB_MEM_TOPK;
+       if (begink < (CONFIG_RAMTOP >> 10)) {
+               begink = (CONFIG_RAMTOP >>10);
        }
 
        printk_debug("Clearing memory %luK - %luK: ", begink, endk);

diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c
index c633c957f0fd14409178466bc99563d9b6161d5a..8b06b5efb3c989e3a9bad4bd9603efafe0a7a398 100644 (file)
--- a/src/cpu/amd/mtrr/amd_earlymtrr.c
+++ b/src/cpu/amd/mtrr/amd_earlymtrr.c
@@ -38,7 +38,7 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
 
         /* Enable memory access for 0 - 1MB using top_mem */
         msr.hi = 0;
-        msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
+        msr.lo = (((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
         wrmsr(TOP_MEM, msr);
 
 #if defined(CONFIG_XIP_ROM_SIZE)

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 7d071cd72dfa86a634697d12b8b62b930572fa72..4bf5468b45b8e65a51bbb8391aa7b06aace8b999 100644 (file)
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -246,17 +246,17 @@ int start_cpu(device_t cpu)
        index = ++last_cpu_index;
        
        /* Find end of the new processors stack */
-#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
+#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
        if(index<1) { // only keep bsp on low 
                stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
        } else {
                // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
                stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
-#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
-               #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
+#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP)
+               #warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
 #endif
-               if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
-                       printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
+               if(stack_end > (CONFIG_RAMTOP)) {
+                       printk_debug("start_cpu: Please increase the CONFIG_RAMTOP more than %luK\n", stack_end);
                        die("Can not go on\n");
                }
                stack_end -= sizeof(struct cpu_info);

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index cff99b8964e55a884455291f259e03b3222caafa..ff375219573ed321527183866a0cf312b15e03d4 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -11,8 +11,8 @@
 #if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
 # error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
 #endif
-#if !defined(CONFIG_LB_MEM_TOPK)
-# error "CONFIG_LB_MEM_TOPK not defined"
+#if !defined(CONFIG_RAMTOP)
+# error "CONFIG_RAMTOP not defined"
 #endif
 
 #if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
@@ -22,8 +22,8 @@
 # error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
 #endif
 
-#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
-# error "CONFIG_LB_MEM_TOPK must be a power of 2"
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
 static void disable_var_mtrr(unsigned reg)
@@ -75,7 +75,7 @@ static void cache_lbmem(int type)
 {
        /* Enable caching for 0 - 1MB using variable mtrr */
        disable_cache();
-       set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, type);
+       set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type);
        enable_cache();
 }
 

diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
index 95c2ad726cb076e2f894250e43de1eff7f232abc..8919f0e049f48dfe7d8bfa6c6f3ae4d33a37e1ae 100644 (file)
--- a/src/cpu/x86/pae/pgtbl.c
+++ b/src/cpu/x86/pae/pgtbl.c
@@ -54,19 +54,19 @@ void *map_2M_page(unsigned long page)
                struct pde pdp[512];
        } __attribute__ ((packed));
 
-#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
+#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
        /*
         pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, 
-        and that region need to be used as vga font buffer. Please make sure set CONFIG_LB_MEM_TOPK=2048 in MB Config
+        and that region need to be used as vga font buffer. Please make sure set CONFIG_RAMTOP=0x200000 in MB Config
        */
        struct pg_table *pgtbl = (struct pg_table*)0x100000; //1M
 
        unsigned x_end = 0x100000 + sizeof(struct pg_table) * CONFIG_MAX_CPUS;
-#if (0x100000+20480*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
-                #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n"
+#if (0x100000+20480*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP)
+                #warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n"
 #endif
-       if(x_end > (CONFIG_LB_MEM_TOPK<<10)) {
-                        printk_debug("map_2M_page: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", x_end>>10);
+       if(x_end > (CONFIG_RAMTOP)) {
+                        printk_debug("map_2M_page: Please increase the CONFIG_RAMTOP more than %dK\n", x_end);
                         die("Can not go on");
        }
 #else

diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb
index dc57febc814892a3e433451306bcc92d3ca3ba1b..a20289d7943a6074eb3bb9c34ac389908c85601d 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Options.lb
@@ -80,7 +80,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -107,7 +107,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/amd/serengeti_cheetah/apc_auto.c b/src/mainboard/amd/serengeti_cheetah/apc_auto.c
index 5a173e006ba5d2edb502f7b83aa5b641df060661..c8723e6fbf716b69d9d9c51ec114f1112b97ef32 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/apc_auto.c
+++ b/src/mainboard/amd/serengeti_cheetah/apc_auto.c
@@ -75,7 +75,7 @@ static inline unsigned get_nodes(void)
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
index df024f5c2b0acab9a7f1e44677cd96083b38816f..8d59b6ca11e935d318f50656a1ad90131dd20141 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
@@ -95,9 +95,9 @@ config AMD_UCODE_PATCH_FILE
        default "mc_patch_01000095.h"
        depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
 
-config LB_MEM_TOPK
+config RAMTOP
        hex
-       default 0x4000
+       default 0x1000000
        depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
 
 config HEAP_SIZE

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
index a5ba422069698f8d8b2c06efbc408cf694a87078..2d82dfde4e65b7f8f672d25c10abcc117784444d 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -98,7 +98,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_PCI_BUS_SEGN_BITS
 
@@ -135,7 +135,7 @@ default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
 #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
-default CONFIG_LB_MEM_TOPK=16384
+default CONFIG_RAMTOP=16384*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
index fbb8c14388f5e7e4cd309c0371d3523760abae3e..69e3ffbb9de2dfc828e43c51c95bf2c9ebaa58ec 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
@@ -74,7 +74,7 @@
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-       struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+       struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb
index 50a15848a8aff4d01398f96c271107719fa84162..02d440773998ebe45c3ff5511154fa79141b67f2 100644 (file)
--- a/src/mainboard/asus/a8n_e/Options.lb
+++ b/src/mainboard/asus/a8n_e/Options.lb
@@ -93,7 +93,6 @@ uses CONFIG_HT_CHAIN_UNITID_BASE
 uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_LB_MEM_TOPK
 uses CONFIG_USE_PRINTK_IN_CAR
 
 default CONFIG_ROM_SIZE = 512 * 1024

diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb
index bdf09726129831ea2b4a9116c2d97df9c8a8c390..92c51feb0c855fad90f603e1fef1babbc819f996 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/Options.lb
+++ b/src/mainboard/asus/a8v-e_se/Options.lb
@@ -41,7 +41,7 @@ uses CONFIG_XIP_ROM_BASE
 uses CONFIG_STACK_SIZE
 uses CONFIG_HEAP_SIZE
 # uses CONFIG_USE_OPTION_TABLE
-# uses CONFIG_LB_MEM_TOPK
+# uses CONFIG_RAMTOP
 uses CONFIG_GENERATE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
 uses CONFIG_LB_CKS_RANGE_START
@@ -147,7 +147,7 @@ default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 256 * 1024
 # More 1M for pgtbl.
-# default CONFIG_LB_MEM_TOPK = 2048
+# default CONFIG_RAMTOP = 2048*1024
 default CONFIG_RAMBASE = 0x00004000
 # default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 default CONFIG_ROM_PAYLOAD = 1

diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb
index 94e57f941b6b846051f3f85169a1363df2e9f2ab..eaa7168682163fdc5eab74c32301f1ac3992609d 100644 (file)
--- a/src/mainboard/asus/m2v-mx_se/Options.lb
+++ b/src/mainboard/asus/m2v-mx_se/Options.lb
@@ -41,7 +41,7 @@ uses CONFIG_XIP_ROM_BASE
 uses CONFIG_STACK_SIZE
 uses CONFIG_HEAP_SIZE
 uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_GENERATE_ACPI_TABLES
 uses CONFIG_HAVE_MAINBOARD_RESOURCES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -151,7 +151,7 @@ default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 256 * 1024
 # More 1M for pgtbl.
-default CONFIG_LB_MEM_TOPK = 32768
+default CONFIG_RAMTOP = 32768*1024
 # to 1MB
 default CONFIG_RAMBASE = 0x1F00000
 default CONFIG_USE_OPTION_TABLE = 0

diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c
index d25a8edf0481c010e67128441f6cae005d8c9ed2..fd8103c7292687a15c9cda856a4c321bc54701f6 100644 (file)
--- a/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ b/src/mainboard/asus/m2v-mx_se/mainboard.c
@@ -40,7 +40,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
        lb_add_memory_range(mem, LB_MEM_RESERVED,
-               CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE));
+               CONFIG_RAMBASE, ((CONFIG_RAMTOP) - CONFIG_RAMBASE));
        lb_add_memory_range(mem, LB_MEM_RESERVED,
                CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE);
 #endif

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
index 2c18f9da2aa3bba3bf98a26e0d8734f5f0a7f7be..97a8a4ccc21716150228ced8af6d0936c41cdfdc 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
@@ -105,7 +105,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -135,7 +135,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
index 6fb051e7c8e7671a8f5515fef9dfb7229164625a..90546b45a2762e1f169f827d183763907d96d579 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
@@ -89,7 +89,7 @@ static void post_code(uint8_t value) {
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb
index 73b46894f55cc0e691e2a18358d5cd56b6cb6e93..0a0d29246a9e53a939f6e405661ae5450817e3d1 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/Options.lb
+++ b/src/mainboard/gigabyte/m57sli/Options.lb
@@ -105,7 +105,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -136,7 +136,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Set-up automatic fan control

diff --git a/src/mainboard/gigabyte/m57sli/apc_auto.c b/src/mainboard/gigabyte/m57sli/apc_auto.c
index d0730b935a35069add9e6ba95a0866dd4e07b00f..176e6b41adcda52731ac7a7626eea4ee3d854e7d 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/apc_auto.c
+++ b/src/mainboard/gigabyte/m57sli/apc_auto.c
@@ -87,7 +87,7 @@ static void post_code(uint8_t value) {
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/hp/dl145_g3/Options.lb b/src/mainboard/hp/dl145_g3/Options.lb
index 2a598c35eae502c25072cc32f86cdaa30c6bf584..5ae7fb27c572f23dffd12743c02931e74b14ac82 100644 (file)
--- a/src/mainboard/hp/dl145_g3/Options.lb
+++ b/src/mainboard/hp/dl145_g3/Options.lb
@@ -102,7 +102,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -121,7 +121,7 @@ default CONFIG_ROM_SIZE=524288
 default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb
index 3815885005f9af59587fd640dd70e8e6ff1f025b..dab3f45b779194d16e448da88638205c33ad15cb 100644 (file)
--- a/src/mainboard/intel/truxton/Options.lb
+++ b/src/mainboard/intel/truxton/Options.lb
@@ -35,7 +35,7 @@ uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE
@@ -157,9 +157,9 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_RAMBASE=0x00100000
 
 ##
-## in order to have coreboot running at 0x100000, TOPK has to be set
+## in order to have coreboot running at 0x100000, RAMTOP has to be set
 ##
-default CONFIG_LB_MEM_TOPK = 2*1024*1024
+default CONFIG_RAMTOP = 2*1024*1024
 
 ##
 ## Load the payload from the ROM

diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb
index 1e5484a81a9d2b5e5e7a65f705e6062a0f9d5a55..f35afb4f816e7f2c0c1c8c5a1e5a243969e6f06e 100644 (file)
--- a/src/mainboard/iwill/dk8_htx/Options.lb
+++ b/src/mainboard/iwill/dk8_htx/Options.lb
@@ -80,7 +80,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -109,7 +109,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb
index 2d09cd026b5beb10a4e9ae904c6a622c368aca67..23377342d0e599f9f004c906c73db0da37911362 100644 (file)
--- a/src/mainboard/msi/ms7135/Options.lb
+++ b/src/mainboard/msi/ms7135/Options.lb
@@ -99,9 +99,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
-
-
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ## ---> 512 Kbytes 
 default CONFIG_ROM_SIZE=(512*1024)

diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb
index 8e52def02a6709368068b635050fd2f410287b52..54b62c1d01d8b7192472c790dfce3801af7f4e4f 100644 (file)
--- a/src/mainboard/msi/ms7260/Options.lb
+++ b/src/mainboard/msi/ms7260/Options.lb
@@ -91,7 +91,7 @@ uses CONFIG_ENABLE_APIC_EXT_ID
 uses CONFIG_APIC_ID_OFFSET
 uses CONFIG_LIFT_BSP_APIC_ID
 uses CONFIG_PCI_64BIT_PREF_MEM
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_AP_CODE_IN_CAR
 uses CONFIG_MEM_TRAIN_SEQ
 uses CONFIG_WAIT_BEFORE_CPUS_INIT
@@ -100,7 +100,7 @@ uses CONFIG_USE_PRINTK_IN_CAR
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE = 4 * 1024
-default CONFIG_LB_MEM_TOPK = 2048      # 1MB more for pgtbl.
+default CONFIG_RAMTOP = 2048*1024      # 1MB more for pgtbl.
 default CONFIG_HAVE_FALLBACK_BOOT = 1
 default CONFIG_HAVE_FAILOVER_BOOT = 1
 default CONFIG_HAVE_HARD_RESET = 1

diff --git a/src/mainboard/msi/ms7260/apc_auto.c b/src/mainboard/msi/ms7260/apc_auto.c
index 880952b267a899bc1cef32f495d037611cd25956..6f01fad1f8140d0edf25616729576c881a40817d 100644 (file)
--- a/src/mainboard/msi/ms7260/apc_auto.c
+++ b/src/mainboard/msi/ms7260/apc_auto.c
@@ -63,7 +63,7 @@ void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
                                    CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */
-       struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) -
+       struct sys_info *sysinfox = ((CONFIG_RAMTOP) -
                                     CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */
        struct node_core_id id;
 

diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb
index 41bbc995aa77ecb2e83ae3a4908e7facd79fcb21..d3423f59e17d13028f933fa3914a0fae9c342cee 100644 (file)
--- a/src/mainboard/msi/ms9185/Options.lb
+++ b/src/mainboard/msi/ms9185/Options.lb
@@ -101,7 +101,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_USE_PRINTK_IN_CAR
 
 ###
@@ -118,7 +118,7 @@ default CONFIG_ROM_SIZE=524288
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb
index a3d8f8e3ee6004ca0cc47ed0bea44488b734108d..b7b445af36b81c0f6fd1f928f54f2d6e283a71bc 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Options.lb
@@ -103,7 +103,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -133,7 +133,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/nvidia/l1_2pvv/apc_auto.c b/src/mainboard/nvidia/l1_2pvv/apc_auto.c
index 525e940776dbc80f4da2af343c265e349a2e1991..7528b84ed452b409685dce7c3599f1f77c191396 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/apc_auto.c
+++ b/src/mainboard/nvidia/l1_2pvv/apc_auto.c
@@ -87,7 +87,7 @@ static void post_code(uint8_t value) {
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-       struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+       struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb
index 9f7095c43c3dd7f6055b93505c2eb7445aa2c727..5a361350bc92f2db19b084dd31644d33aa3140ad 100644 (file)
--- a/src/mainboard/supermicro/h8dme/Options.lb
+++ b/src/mainboard/supermicro/h8dme/Options.lb
@@ -104,7 +104,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -137,7 +137,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/supermicro/h8dme/apc_auto.c b/src/mainboard/supermicro/h8dme/apc_auto.c
index 442945e9f2cb225be9b6f0a9fb74eeda463e7750..f4bedfe0f09021d53173e8856dceb18e0c7486f3 100644 (file)
--- a/src/mainboard/supermicro/h8dme/apc_auto.c
+++ b/src/mainboard/supermicro/h8dme/apc_auto.c
@@ -95,7 +95,7 @@ static inline unsigned get_nodes(void)
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb
index f95c63c4ba6e8010d68146a61d2de5078e4a6126..5e457d03aadf1514663436483f8c8f4c9c728073 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/Options.lb
+++ b/src/mainboard/supermicro/h8dmr/Options.lb
@@ -102,7 +102,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -130,7 +130,7 @@ default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/supermicro/h8dmr/apc_auto.c b/src/mainboard/supermicro/h8dmr/apc_auto.c
index 442945e9f2cb225be9b6f0a9fb74eeda463e7750..f4bedfe0f09021d53173e8856dceb18e0c7486f3 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/apc_auto.c
+++ b/src/mainboard/supermicro/h8dmr/apc_auto.c
@@ -95,7 +95,7 @@ static inline unsigned get_nodes(void)
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/supermicro/h8dmr_fam10/Options.lb b/src/mainboard/supermicro/h8dmr_fam10/Options.lb
index 2ad708a813c714a878adcc10cc4549ea8c85ec86..1342e4381a4da7483e747cc604becdb7a676e916 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/Options.lb
+++ b/src/mainboard/supermicro/h8dmr_fam10/Options.lb
@@ -99,7 +99,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_UNCOMPRESSED
 
@@ -132,7 +132,7 @@ default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=16384
+default CONFIG_RAMTOP=16384*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c b/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
index 099b6abd173af8f7918f54c33abc5e38ebec70aa..f55b80f826aacbecc92a14d7891109aedea8f038 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
@@ -95,7 +95,7 @@ static inline unsigned get_nodes(void)
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb
index df76f5c93c1d6116f3bfab529c846b8c36b08c81..fc43fc834dc1f4a8e8d94f621f8e44dea2f41088 100644 (file)
--- a/src/mainboard/tyan/s2885/Options.lb
+++ b/src/mainboard/tyan/s2885/Options.lb
@@ -68,8 +68,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
-
 ###
 ### Build options
 ###

diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb
index 08a1a081f1050ece09aa011cd72f1c929b4b7533..63c5f935da35a5b1f7edfcafb2c4397b50ce1cac 100644 (file)
--- a/src/mainboard/tyan/s2891/Options.lb
+++ b/src/mainboard/tyan/s2891/Options.lb
@@ -77,8 +77,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
-
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=512*1024
 

diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb
index 4ec42e59327359634cb544e5e1bb4dee0045c68f..89a897bf96978571780a442823037316fa235b19 100644 (file)
--- a/src/mainboard/tyan/s2892/Options.lb
+++ b/src/mainboard/tyan/s2892/Options.lb
@@ -71,8 +71,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
-
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
 

diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb
index de9e136f2dede49ddf8cbf224e1a67db4b21d2b9..864fc30dc376aa1dbf7636938c024ee35e3e6da2 100644 (file)
--- a/src/mainboard/tyan/s2895/Options.lb
+++ b/src/mainboard/tyan/s2895/Options.lb
@@ -80,7 +80,7 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
@@ -95,7 +95,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb
index 439c6cf3eb8e9c27545c5f69539c3f57e0cbb1dd..a8de386fef34111d1e4121c000d147aba047a70b 100644 (file)
--- a/src/mainboard/tyan/s2912/Options.lb
+++ b/src/mainboard/tyan/s2912/Options.lb
@@ -103,7 +103,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -133,7 +133,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/tyan/s2912/apc_auto.c b/src/mainboard/tyan/s2912/apc_auto.c
index 8985b7affda2bec53d26b7f237d58a95be3cbcaa..2600dd3b6bc45889715faadb471b844f10f29acf 100644 (file)
--- a/src/mainboard/tyan/s2912/apc_auto.c
+++ b/src/mainboard/tyan/s2912/apc_auto.c
@@ -76,7 +76,7 @@
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-       struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+       struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb
index 61c647cb862245fc86eea638c6470c2ab6555eac..29e4f136e7a0516953f8a761b45dd7dcd0e25196 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/Options.lb
+++ b/src/mainboard/tyan/s2912_fam10/Options.lb
@@ -101,7 +101,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_PCI_BUS_SEGN_BITS
 
@@ -135,7 +135,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=16384
+default CONFIG_RAMTOP=16384*1024
 
 ##
 ## Build code for the fallback boot

diff --git a/src/mainboard/tyan/s2912_fam10/apc_auto.c b/src/mainboard/tyan/s2912_fam10/apc_auto.c
index 8985b7affda2bec53d26b7f237d58a95be3cbcaa..2600dd3b6bc45889715faadb471b844f10f29acf 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/apc_auto.c
+++ b/src/mainboard/tyan/s2912_fam10/apc_auto.c
@@ -76,7 +76,7 @@
 void hardwaremain(int ret_addr)
 {
        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-       struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+       struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
        struct node_core_id id;
 

diff --git a/src/mainboard/via/epia-n/Options.lb b/src/mainboard/via/epia-n/Options.lb
index e9dfad17cded0365f54600e016d98a32a1e938b8..7d229c5302899106c8d39d9f733f24c8059bd663 100644 (file)
--- a/src/mainboard/via/epia-n/Options.lb
+++ b/src/mainboard/via/epia-n/Options.lb
@@ -34,7 +34,7 @@ uses CONFIG_MAINBOARD_VENDOR
 uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
 uses CONFIG_ARCH
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_STACK_SIZE
 uses CONFIG_HEAP_SIZE
@@ -73,7 +73,7 @@ uses CONFIG_EPIA_VT8237R_INIT
 uses CONFIG_HAVE_MAINBOARD_RESOURCES
 
 default CONFIG_EPIA_VT8237R_INIT = 1
-#default CONFIG_LB_MEM_TOPK = 4 * 1024
+#default CONFIG_RAMTOP = 4 * 1024*1024
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_COMPRESS = 1
 default CONFIG_IOAPIC = 1

diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
index d0c9baf6fc70630e1bc605ec792eb98a5e9d8419..dcff71430638a3aa9c4bdc62ea4297775189f7d8 100644 (file)
--- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
@@ -134,7 +134,7 @@ unsigned long acpi_fill_slit(unsigned long current)
        /* fill the first 8 byte with that num */
        /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
 
-       struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        u8 *ln = sysinfox->ln;
 
 

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 52ec0194b92a4938b5a96171f969af405f297254..e7ac7efc11c800dce0cda147829180507cd59f57 100644 (file)
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -806,7 +806,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int i)
        u32 hole_sizek;
 
        u32 one_DCT;
-       struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+       struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
        struct mem_info *meminfo;
        meminfo = &sysinfox->meminfo[i];
 
@@ -1065,7 +1065,7 @@ static void pci_domain_set_resources(device_t dev)
                                #if CONFIG_AMDMCT == 0
                                #if CONFIG_HW_MEM_HOLE_SIZEK != 0
                                if(reset_memhole) {
-                                       struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+                                       struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
                                        struct mem_info *meminfo;
                                        meminfo = &sysinfox->meminfo[i];
                                        sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes);

diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 83ae83032a52fa0626f4f2661b1afa2f4f520df5..1b040aed6b1f60ab100cc3b7ad5b00deca897a4e 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -11,8 +11,8 @@
 #include "raminit.h"
 #include "amdk8.h"
 
-#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
-# error "CONFIG_LB_MEM_TOPK must be a power of 2"
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
 #ifndef QRANK_DIMM_SUPPORT

diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 3c96477cb35540175274dd3eff281ad4e6aa50e3..1acc04fb0bbd08534ebbdd3a246761789ba082ca 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -48,8 +48,8 @@
 #endif
 
 
-#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
-# error "CONFIG_LB_MEM_TOPK must be a power of 2"
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
 #include "amdk8_f_pci.c"

diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index d28e9422efe97fe7dcf9b59ed131e8e0ead35b6f..16faf489cff4f5256f74a2384ff8def7be924bd1 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -2096,7 +2096,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr);
 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
 {
        if(coreid) return; // only do it on core0
-       struct sys_info *sysinfox = (void*)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfox = (void*)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        wait_till_sysinfo_in_ram(); // use pci to get it
 
        if(sysinfox->mem_trained[nodeid] == 0x80) {

diff --git a/src/pc80/usbdebug_direct_serial.c b/src/pc80/usbdebug_direct_serial.c
index 8a8b8c6c1eea7f04386d96630575360c32b835e9..21f6109ce387ee1ee036bb85e6c5490a78c20413 100644 (file)
--- a/src/pc80/usbdebug_direct_serial.c
+++ b/src/pc80/usbdebug_direct_serial.c
@@ -45,7 +45,7 @@ void usbdebug_direct_ram_tx_byte(unsigned char data)
 
        /* "Find" dbg_info structure in RAM */
        dbg_info = (struct ehci_debug_info *)
-           ((CONFIG_LB_MEM_TOPK << 10) - sizeof(struct ehci_debug_info));
+           ((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
 
        if (dbg_info->ehci_debug) {
                dbgp_bulk_write_x(dbg_info, &data, 1);