- Bump the LinuxBIOS major version
authorEric Biederman <ebiederm@xmission.com>
Thu, 21 Oct 2004 10:44:08 +0000 (10:44 +0000)
committerEric Biederman <ebiederm@xmission.com>
Thu, 21 Oct 2004 10:44:08 +0000 (10:44 +0000)
commitdbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d
treee813d3f9dea80d35cbc29d6bf35995fec0a06ab9
parentf3aa4707d3bef9f529a70a204dbc648968cf7c20
- Bump the LinuxBIOS major version
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
107 files changed:
NEWS
src/config/Options.lb
src/cpu/intel/slot_2/chip.h
src/cpu/intel/slot_2/slot_2.c
src/cpu/intel/socket_mPGA603/chip.h
src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c
src/cpu/intel/socket_mPGA604_533Mhz/chip.h
src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c
src/cpu/intel/socket_mPGA604_800Mhz/chip.h
src/cpu/intel/socket_mPGA604_800Mhz/socket_mPGA604_800Mhz.c
src/devices/device.c
src/devices/pci_device.c
src/devices/pnp_device.c
src/devices/root_device.c
src/include/device/device.h
src/include/device/pci.h
src/include/pc80/isa-dma.h [new file with mode: 0644]
src/mainboard/Iwill/DK8S2/Config.lb
src/mainboard/Iwill/DK8S2/chip.h
src/mainboard/Iwill/DK8S2/mainboard.c
src/mainboard/Iwill/DK8X/Config.lb
src/mainboard/Iwill/DK8X/chip.h
src/mainboard/Iwill/DK8X/mainboard.c
src/mainboard/amd/quartet/Config.lb
src/mainboard/amd/quartet/chip.h
src/mainboard/amd/quartet/mainboard.c
src/mainboard/amd/serenade/Config.lb
src/mainboard/amd/serenade/chip.h
src/mainboard/amd/serenade/mainboard.c
src/mainboard/amd/solo/chip.h
src/mainboard/amd/solo/mainboard.c
src/mainboard/arima/hdama/Config.lb
src/mainboard/arima/hdama/Options.lb
src/mainboard/arima/hdama/mainboard.c
src/mainboard/densitron/dpx114/chip.h
src/mainboard/densitron/dpx114/mainboard.c
src/mainboard/digitallogic/adl855pc/chip.h
src/mainboard/digitallogic/adl855pc/mainboard.c
src/mainboard/emulation/qemu-i386/chip.h
src/mainboard/emulation/qemu-i386/mainboard.c
src/mainboard/ibm/e325/Config.lb
src/mainboard/ibm/e325/chip.h
src/mainboard/ibm/e325/mainboard.c
src/mainboard/newisys/khepri/Config.lb
src/mainboard/newisys/khepri/chip.h
src/mainboard/newisys/khepri/mainboard.c
src/mainboard/technologic/ts5300/Config.lb
src/mainboard/technologic/ts5300/chip.h
src/mainboard/technologic/ts5300/mainboard.c
src/mainboard/tyan/s2735/Config.lb
src/mainboard/tyan/s2735/chip.h
src/mainboard/tyan/s2735/mainboard.c
src/mainboard/via/epia-m/chip.h
src/mainboard/via/epia-m/mainboard.c
src/mainboard/via/epia/chip.h
src/mainboard/via/epia/mainboard.c
src/northbridge/amd/amdk8/northbridge.c
src/northbridge/emulation/qemu-i386/chip.h
src/northbridge/emulation/qemu-i386/northbridge.c
src/northbridge/intel/855pm/chip.h
src/northbridge/intel/855pm/northbridge.c
src/northbridge/intel/e7501/chip.h
src/northbridge/intel/e7501/northbridge.c
src/northbridge/intel/i855pm/chip.h
src/northbridge/intel/i855pm/northbridge.c
src/northbridge/transmeta/tm5800/chip.h
src/northbridge/transmeta/tm5800/northbridge.c
src/northbridge/via/vt8601/chip.h
src/northbridge/via/vt8601/northbridge.c
src/northbridge/via/vt8623/chip.h
src/northbridge/via/vt8623/northbridge.c
src/pc80/isa-dma.c
src/pc80/vgachip.h
src/southbridge/amd/amd8111/amd8111.c
src/southbridge/amd/amd8111/amd8111_ac97.c
src/southbridge/amd/amd8111/amd8111_acpi.c
src/southbridge/amd/amd8111/amd8111_early_smbus.c
src/southbridge/amd/amd8111/amd8111_enable_rom.c
src/southbridge/amd/amd8111/amd8111_ide.c
src/southbridge/amd/amd8111/amd8111_lpc.c
src/southbridge/amd/amd8111/amd8111_nic.c
src/southbridge/amd/amd8111/amd8111_pci.c
src/southbridge/amd/amd8111/amd8111_smbus.c
src/southbridge/amd/amd8111/amd8111_smbus.h [new file with mode: 0644]
src/southbridge/amd/amd8111/amd8111_usb.c
src/southbridge/amd/amd8111/amd8111_usb2.c
src/southbridge/amd/amd8111/chip.h
src/southbridge/amd/amd8131/amd8131_bridge.c
src/southbridge/intel/i82801dbm/i82801dbm.c
src/southbridge/intel/i82801er/i82801er.c
src/southbridge/ricoh/rl5c476/chip.h
src/southbridge/ricoh/rl5c476/rl5c476.c
src/southbridge/via/vt8231/chip.h
src/southbridge/via/vt8231/vt8231.c
src/southbridge/via/vt8235/chip.h
src/southbridge/via/vt8235/vt8235.c
src/southbridge/winbond/w83c553/chip.h
src/superio/NSC/pc87366/chip.h
src/superio/NSC/pc87366/superio.c
src/superio/NSC/pc97307/chip.h
src/superio/NSC/pc97307/pc97307.h [new file with mode: 0644]
src/superio/NSC/pc97307/superio.c
src/superio/via/vt1211/chip.h
src/superio/via/vt1211/vt1211.c
src/superio/winbond/w83627thf/chip.h
src/superio/winbond/w83627thf/superio.c
util/newconfig/config.g