3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
8 uses HARD_RESET_FUNCTION
10 uses HAVE_OPTION_TABLE
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_STREAM
21 uses CONFIG_ROM_STREAM_START
30 ## ROM_SIZE is the size of boot ROM that this board will use.
31 default ROM_SIZE=524288
38 ## Build code for the fallback boot
40 default HAVE_FALLBACK_BOOT=1
43 ## Build code to reset the motherboard from linuxBIOS
45 default HAVE_HARD_RESET=1
47 default HARD_RESET_BUS=1
48 default HARD_RESET_DEVICE=4
49 default HARD_RESET_FUNCTION=0
52 ## Build code to export a programmable irq routing table
54 default HAVE_PIRQ_TABLE=1
55 default IRQ_SLOT_COUNT=9
58 ## Build code to export an x86 MP table
59 ## Useful for specifying IRQ routing values
61 default HAVE_MP_TABLE=1
64 ## Build code to export a CMOS option table
66 default HAVE_OPTION_TABLE=1
69 ## Build code for SMP support
70 ## Only worry about 2 micro processors
73 default CONFIG_MAX_CPUS=2
76 ## Build code to setup a generic IOAPIC
78 default CONFIG_IOAPIC=1
81 ## Clean up the motherboard id strings
83 #default MAINBOARD_PART_NUMBER="HDAMA"
84 #default MAINBOARD_VENDOR="ARIMA"
87 ### LinuxBIOS layout values
90 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
91 default ROM_IMAGE_SIZE = 65536
94 ## Use a small 8K stack
96 default STACK_SIZE=0x2000
99 ## Use a small 16K heap
101 default HEAP_SIZE=0x4000
104 ## Only use the option table in a normal image
106 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
109 ## Compute the location and size of where this firmware image
110 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
112 if USE_FALLBACK_IMAGE
113 default ROM_SECTION_SIZE = FALLBACK_SIZE
114 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
116 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
117 default ROM_SECTION_OFFSET = 0
121 ## Compute the start location and size size of
122 ## The linuxBIOS bootloader.
124 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
125 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
126 default CONFIG_ROM_STREAM = 1
129 ## Compute where this copy of linuxBIOS will start in the boot rom
131 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
134 ## Compute a range of ROM that can cached to speed up linuxBIOS,
137 ## XIP_ROM_SIZE must be a power of 2.
138 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
140 default XIP_ROM_SIZE=65536
141 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
144 ## Set all of the defaults for an x86 architecture
151 ## Build the objects we have code for in this directory.
156 #object static_devices.o
157 if HAVE_MP_TABLE object mptable.o end
158 if HAVE_PIRQ_TABLE object irq_tables.o end
160 ## ATI Rage XL framebuffering graphics driver
161 dir /drivers/ati/ragexl
166 makerule ./failover.E
167 depends "$(MAINBOARD)/failover.c"
168 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
171 makerule ./failover.inc
172 depends "./failover.E ./romcc"
173 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
177 depends "$(MAINBOARD)/auto.c option_table.h"
178 action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
181 depends "./auto.E ./romcc"
182 action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
186 ## Build our 16 bit and 32 bit linuxBIOS entry code
188 mainboardinit cpu/i386/entry16.inc
189 mainboardinit cpu/i386/entry32.inc
190 ldscript /cpu/i386/entry16.lds
191 ldscript /cpu/i386/entry32.lds
194 ## Build our reset vector (This is where linuxBIOS is entered)
196 if USE_FALLBACK_IMAGE
197 mainboardinit cpu/i386/reset16.inc
198 ldscript /cpu/i386/reset16.lds
200 mainboardinit cpu/i386/reset32.inc
201 ldscript /cpu/i386/reset32.lds
204 ### Should this be in the northbridge code?
205 mainboardinit arch/i386/lib/cpu_reset.inc
208 ## Include an id string (For safe flashing)
210 mainboardinit arch/i386/lib/id.inc
211 ldscript /arch/i386/lib/id.lds
216 mainboardinit cpu/k8/earlymtrr.inc
219 ### This is the early phase of linuxBIOS startup
220 ### Things are delicate and we test to see if we should
221 ### failover to another image.
223 if USE_FALLBACK_IMAGE
224 ldscript /arch/i386/lib/failover.lds
225 mainboardinit ./failover.inc
229 ### O.k. We aren't just an intermediary anymore!
235 mainboardinit cpu/k8/enable_mmx_sse.inc
236 mainboardinit ./auto.inc
237 mainboardinit cpu/k8/disable_mmx_sse.inc
240 ## Include the secondary Configuration files
245 chip northbridge/amd/amdk8
246 device pci_domain 0 on
247 device pci 18.0 on # LDT 0
248 chip southbridge/amd/amd8131
249 device pci 0.0 on end
250 device pci 0.1 on end
251 device pci 1.0 on end
252 device pci 1.1 on end
254 chip southbridge/amd/amd8111
255 # this "device pci 0.0" is the parent the next one
258 device pci 0.0 on end
259 device pci 0.1 on end
260 device pci 0.2 on end
261 device pci 1.0 off end
264 chip superio/winbond/w83627hf
265 device pnp 2e.0 on # Floppy
270 device pnp 2e.1 off # Parallel Port
274 device pnp 2e.2 on # Com1
278 device pnp 2e.3 off # Com2
282 device pnp 2e.5 on # Keyboard
288 device pnp 2e.6 off end # CIR
289 device pnp 2e.7 off end # GAME_MIDI_GIPO1
290 device pnp 2e.8 off end # GPIO2
291 device pnp 2e.9 off end # GPIO3
292 device pnp 2e.a off end # ACPI
293 device pnp 2e.b on # HW Monitor
296 register "com1" = "{1}"
297 # register "com1" = "{1, 0, 0x3f8, 4}"
298 # register "lpt" = "{1}"
301 device pci 1.1 on end
302 device pci 1.2 on end
303 device pci 1.3 on end
304 device pci 1.5 off end
305 device pci 1.6 off end
308 device pci 18.0 on end # LDT1
309 device pci 18.0 on end # LDT2
310 device pci 18.1 on end
311 device pci 18.2 on end
312 device pci 18.3 on end
314 chip northbridge/amd/amdk8
315 device pci 19.0 on end
316 device pci 19.0 on end
317 device pci 19.0 on end
318 device pci 19.1 on end
319 device pci 19.2 on end
320 device pci 19.3 on end
323 device apic_cluster 0 on
324 chip cpu/amd/socket_940
327 chip cpu/amd/socket_940
334 ## Include the old serial code for those few places that still need it.
336 mainboardinit pc80/serial.inc
337 mainboardinit arch/i386/lib/console.inc