3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
8 uses HARD_RESET_FUNCTION
10 uses HAVE_OPTION_TABLE
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_STREAM
21 uses CONFIG_ROM_STREAM_START
29 uses LB_CKS_RANGE_START
32 uses MAINBOARD_PART_NUMBER
36 ## ROM_SIZE is the size of boot ROM that this board will use.
37 default ROM_SIZE=524288
44 ## Build code for the fallback boot
46 default HAVE_FALLBACK_BOOT=1
49 ## Build code to reset the motherboard from linuxBIOS
51 default HAVE_HARD_RESET=1
53 default HARD_RESET_BUS=1
54 default HARD_RESET_DEVICE=4
55 default HARD_RESET_FUNCTION=0
58 ## Build code to export a programmable irq routing table
60 default HAVE_PIRQ_TABLE=1
61 default IRQ_SLOT_COUNT=9
64 ## Build code to export an x86 MP table
65 ## Useful for specifying IRQ routing values
67 default HAVE_MP_TABLE=1
70 ## Build code to export a CMOS option table
72 default HAVE_OPTION_TABLE=1
75 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
77 default LB_CKS_RANGE_START=49
78 default LB_CKS_RANGE_END=122
79 default LB_CKS_LOC=123
82 ## Build code for SMP support
83 ## Only worry about 2 micro processors
86 default CONFIG_MAX_CPUS=4
89 ## Build code to setup a generic IOAPIC
91 default CONFIG_IOAPIC=1
94 ## Clean up the motherboard id strings
96 default MAINBOARD_PART_NUMBER="QUARTET"
97 default MAINBOARD_VENDOR="AMD"
100 ### LinuxBIOS layout values
103 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
104 default ROM_IMAGE_SIZE = 65536
107 ## Use a small 8K stack
109 default STACK_SIZE=0x2000
112 ## Use a small 16K heap
114 default HEAP_SIZE=0x4000
117 ## Only use the option table in a normal image
119 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
122 ## Compute the location and size of where this firmware image
123 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
125 if USE_FALLBACK_IMAGE
126 default ROM_SECTION_SIZE = FALLBACK_SIZE
127 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
129 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
130 default ROM_SECTION_OFFSET = 0
134 ## Compute the start location and size size of
135 ## The linuxBIOS bootloader.
137 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
138 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
139 default CONFIG_ROM_STREAM = 1
142 ## Compute where this copy of linuxBIOS will start in the boot rom
144 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
147 ## Compute a range of ROM that can cached to speed up linuxBIOS,
150 ## XIP_ROM_SIZE must be a power of 2.
151 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
153 default XIP_ROM_SIZE=65536
154 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
157 ## Set all of the defaults for an x86 architecture
164 ## Build the objects we have code for in this directory.
168 if HAVE_MP_TABLE object mptable.o end
169 if HAVE_PIRQ_TABLE object irq_tables.o end
174 makerule ./failover.E
175 depends "$(MAINBOARD)/failover.c"
176 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
179 makerule ./failover.inc
180 depends "./failover.E ./romcc"
181 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
185 depends "$(MAINBOARD)/auto.c option_table.h"
186 action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
189 depends "./auto.E ./romcc"
190 action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
194 ## Build our 16 bit and 32 bit linuxBIOS entry code
196 mainboardinit cpu/i386/entry16.inc
197 mainboardinit cpu/i386/entry32.inc
198 mainboardinit cpu/i386/bist32.inc
199 ldscript /cpu/i386/entry16.lds
200 ldscript /cpu/i386/entry32.lds
203 ## Build our reset vector (This is where linuxBIOS is entered)
205 if USE_FALLBACK_IMAGE
206 mainboardinit cpu/i386/reset16.inc
207 ldscript /cpu/i386/reset16.lds
209 mainboardinit cpu/i386/reset32.inc
210 ldscript /cpu/i386/reset32.lds
213 ### Should this be in the northbridge code?
214 mainboardinit arch/i386/lib/cpu_reset.inc
217 ## Include an id string (For safe flashing)
219 mainboardinit arch/i386/lib/id.inc
220 ldscript /arch/i386/lib/id.lds
225 mainboardinit cpu/k8/earlymtrr.inc
228 ### This is the early phase of linuxBIOS startup
229 ### Things are delicate and we test to see if we should
230 ### failover to another image.
232 if USE_FALLBACK_IMAGE
233 ldscript /arch/i386/lib/failover.lds
234 mainboardinit ./failover.inc
238 ### O.k. We aren't just an intermediary anymore!
244 mainboardinit cpu/k8/enable_mmx_sse.inc
245 mainboardinit ./auto.inc
246 mainboardinit cpu/k8/disable_mmx_sse.inc
249 ## Include the secondary Configuration files
254 chip northbridge/amd/amdk8 # mc0
255 device pci_domain 0 on
256 device pci 18.0 on end
257 device pci 18.0 on end
259 chip southbridge amd/amd8111
261 device pci 0.0 on end
262 device pci 0.1 on end
263 device pci 0.2 on end
264 device pci 1.0 on end
267 chip superio/NSC/pc87360
268 device pnp 2e.0 off # Floppy
273 device pnp 2e.1 off # Parallel Port
277 device pnp 2e.2 off # Com 2
281 device pnp 2e.3 on # Com 1
285 device pnp 2e.4 off end # SWC
286 device pnp 2e.5 off end # Mouse
287 device pnp 2e.6 on # Keyboard
292 device pnp 2e.7 off end # GPIO
293 device pnp 2e.8 off end # ACB
294 device pnp 2e.9 off end # FSCM
295 device pnp 2e.a off end # WDT
298 device pci 1.1 on end
299 device pci 1.2 on end
300 device pci 1.3 on end
301 device pci 1.5 on end
302 device pci 1.6 on end
305 device pci 18.1 on end
306 device pci 18.2 on end
307 device pci 18.3 on end
309 chip northbridge/amd/amdk8 # mc1
310 device pci 19.0 on end
312 chip southbridge amd/amd8131 # amd8131_0
313 device pci 0.0 on end
314 device pci 0.1 on end
315 device pci 1.0 on end
316 device pci 1.1 on end
318 chip southbridge amd/amd8131 # amd8131_1
319 device pci 0.0 on end
320 device pci 0.1 on end
321 device pci 1.0 on end
322 device pci 1.1 on end
325 device pci 19.0 on end
326 device pci 19.1 on end
327 device pci 19.2 on end
328 device pci 19.3 on end
331 chip northbridge/amd/amdk8 # mc2
332 device pci 1a.0 on end
333 device pci 1a.0 on end
334 device pci 1a.0 on end
335 device pci 1a.1 on end
336 device pci 1a.2 on end
337 device pci 1a.3 on end
340 chip northbridge/amd/amdk8 # mc3
341 device pci 1b.0 on end
342 device pci 1b.0 on end
343 device pci 1b.0 on end
344 device pci 1b.1 on end
345 device pci 1b.2 on end
346 device pci 1b.3 on end
349 device apic_cluster 0 on
350 chip cpu/amd/socket_940
353 chip cpu/amd/socket_940
356 chip cpu/amd/socket_940
359 chip cpu/amd/socket_940
366 ## Include the old serial code for those few places that still need it.
368 mainboardinit pc80/serial.inc
369 mainboardinit arch/i386/lib/console.inc
370 mainboardinit cpu/i386/bist32_fail.inc