2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <cpu/x86/tsc.h>
23 #include <cpu/x86/msr.h>
26 * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
32 tsc_t tsc, tsc1, tscd;
35 u32 d; /* ticks per us */
36 u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */
39 switch (msr.lo & 0x07) {
64 divisor = (msr.hi >> 8) & 0x1f;
69 tscd.lo = (us - tscd.hi * dn) * d;
72 dword = tsc1.lo + tscd.lo;
73 if ((dword < tsc1.lo) || (dword < tscd.lo)) {
81 } while ((tsc.hi < tsc1.hi)
82 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));