\r
alu_state : in alu_result_rec;\r
pval : in gp_register_t;\r
+ pval_nxt : in gp_register_t;\r
\r
alu_result : out alu_result_rec;\r
addr : out word_t; --memaddr\r
shift_inst : entity work.exec_op(shift_op)\r
port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);\r
\r
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval, pval_nxt)\r
variable result_v : alu_result_rec;\r
variable res_prod : std_logic;\r
variable cond_met : std_logic;\r
\r
addr <= pval;\r
data <= prog_cnt_nxt;\r
- -- if(op_detail(RET_OPT) = '1' then\r
- -- null;\r
- -- end if;\r
+ if op_detail(RET_OPT) = '1' then\r
+ addr <= pval_nxt;\r
+ mem_en := '0';\r
+ pinc_v := '0';\r
+ res_prod := '0';\r
+ end if;\r
\r
end case;\r
\r
alu_state : in alu_result_rec;
pval : in gp_register_t;
+ pval_nxt : in gp_register_t;
alu_result : out alu_result_rec;
addr : out word_t; --memaddr
signal ext_gpmp : extmod_rec;
signal data_out : gp_register_t;
-signal pval : gp_register_t;
+signal pval, pval_nxt : gp_register_t;
signal paddr : paddr_t;
signal pinc, pwr_en : std_logic;
alu_inst : alu
port map(clk, reset, condition, op_group,
- left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, alu_nxt,addr,data, pinc, pwr_en, paddr);
+ left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, pval_nxt, alu_nxt,addr,data, pinc, pwr_en, paddr);
pinc,
pwr_en,
psw,
- pval
+ pval,
+ pval_nxt
);
pwr_en : in std_logic;
-- Ouput
psw : out status_rec;
- pval : out gp_register_t
+ pval : out gp_register_t;
+ pval_nxt : out gp_register_t
);
end extension_gpm;
asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr)
variable reg_nxt_v : gpm_internal;
variable incb : ext_addr_t;
- variable sel_pval : ext_addr_t;
+ variable sel_pval, sel_pval_nxt : ext_addr_t;
variable data_out_v : gp_register_t;
variable data_v : gp_register_t;
variable tmp_data : gp_register_t;
+
begin
reg_nxt_v := reg;
data_v := ext_reg.data;
end if;
sel_pval:= reg_nxt_v.preg(to_integer(unsigned(paddr)));
-
+ sel_pval_nxt := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
if pwr_en = '1' then
- reg_nxt_v.preg(to_integer(unsigned(paddr))) := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
+ reg_nxt_v.preg(to_integer(unsigned(paddr))) := sel_pval_nxt;
end if;
reg_nxt_v.status := psw_nxt;
pval <= (others =>'0');
pval(pval'high downto BYTEADDR) <= sel_pval;
+ pval_nxt <= (others =>'0');
+ pval_nxt(pval'high downto BYTEADDR) <= sel_pval_nxt;
end process asyn;
end behav;
pwr_en : in std_logic;
-- Ouput
psw : out status_rec;
- pval : out gp_register_t
+ pval : out gp_register_t;
+ pval_nxt : out gp_register_t
);
end component extension_gpm;