3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
10 constant WORD_WIDTH : INTEGER := 32;
11 constant HWORD_WIDTH : INTEGER := 16;
12 constant BYTE_WIDTH : INTEGER := 8;
13 constant OPCODE_WIDTH : INTEGER := 5;
14 constant DISPL_WIDTH : INTEGER := 15;
16 subtype byte_t is std_logic_vector(BYTE_WIDTH-1 downto 0);
17 subtype hword_t is std_logic_vector(HWORD_WIDTH-1 downto 0);
18 subtype word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
20 subtype gp_register_t is word_t;
23 constant REG_ZERO : gp_register_t := (others => '0');
25 constant INSTR_ADDR_WIDTH : INTEGER := 32;
26 constant PHYS_INSTR_ADDR_WIDTH : INTEGER := 11;
27 constant REG_ADDR_WIDTH : INTEGER := 4;
28 constant DATA_ADDR_WIDTH : INTEGER := 32;
29 constant PHYS_DATA_ADDR_WIDTH : INTEGER := 32;
31 constant NUM_OP_OPT_WIDTH : INTEGER := 5;
32 constant COND_WIDTH : INTEGER := 4;
35 subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
36 subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
38 subtype gp_addr_t is unsigned(REG_ADDR_WIDTH-1 downto 0);
39 subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
40 subtype data_ram_addr_t is std_logic_vector(DATA_ADDR_WIDTH-1 downto 0);
42 subtype opcode_t is std_logic_vector(OPCODE_WIDTH-1 downto 0);
43 subtype condition_t is std_logic_vector(COND_WIDTH-1 downto 0);
45 --Opcode consits of decoded group information type and option bits
46 --currently not complete, might need option increase too.
47 --IMMEDIATE always in right_operand (src2)
49 constant IMM_OPT : integer := 0;
51 constant SUB_OPT : integer := 1;
52 constant LOG_SHIFT : integer := 1;
54 constant CARRY_OPT : integer := 2;
56 constant LEFT_SHIFT : integer := 3;
58 constant PSW_DISABLE : integer := 4;
60 type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP);
61 subtype op_opt_rec is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
64 type instruction_rec is record
66 predicates : std_logic_vector(3 downto 0);
70 reg_dest_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
71 reg_src1_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
72 reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
74 immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
75 displacement : std_logic_vector(DISPL_WIDTH-1 downto 0);
77 jmptype : std_logic_vector(1 downto 0);
79 carry, sreg_update, high_low, fill, signext, bp, arith, left_right : std_logic;
84 type read_through_write_rec is record
86 rtw_reg : gp_register_t;
93 condition : condition_t;
95 op_detail : op_opt_rec;
111 function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector;
112 function log2c(constant value : in integer range 0 to integer'high) return integer;
113 end package common_pkg;
115 package body common_pkg is
117 function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector is
119 return std_logic_vector(UNSIGNED(value)+by);
122 function log2c(constant value : in integer range 0 to integer'high) return integer is
123 variable ret_value : integer;
124 variable cur_value : integer;
129 while cur_value < value loop
130 ret_value := ret_value + 1;
131 cur_value := cur_value * 2;
136 end package body common_pkg;