stw alu

diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd
index 7950c6c4ef8cd713bd8c8a06dfe9b0fe6fc92192..9883530306d497326980cf5405754c2d5a42289f 100755 (executable)
--- a/cpu/src/alu.vhd
+++ b/cpu/src/alu.vhd
@@ -16,7 +16,8 @@ entity alu is
                        cond : in condition_t;\r
                        op_group : in op_info_t;\r
                        left_operand : in gp_register_t;\r
-                       right_operand : in gp_register_t;\r
+                       right_operand : in gp_register_t;
+                        displacement : in gp_register_t;\r
                        op_detail : in op_opt_t;\r
                        alu_state  : in alu_result_rec;\r
                        alu_result : out alu_result_rec;

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 634c7d1605504d5127b136c82c8828fc3fbcdb9a..9f29b0be5afa1605631ac38c0b7e8156c9c05984 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -21,37 +21,42 @@ architecture behaviour of alu is
        );                      \r
        end component exec_op;\r
        \r
-       signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
+       signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
+        signal left, right : gp_register_t;\r
        \r
 begin\r
 \r
        add_inst : entity work.exec_op(add_op)\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result);\r
+       port map(clk,reset,left, right, op_detail, alu_state, add_result);\r
        \r
        and_inst : entity work.exec_op(and_op)\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
+       port map(clk,reset,left, right, op_detail, alu_state, and_result);\r
 \r
        or_inst : entity work.exec_op(or_op)\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
+       port map(clk,reset,left, right, op_detail, alu_state, or_result);\r
 \r
        xor_inst : entity work.exec_op(xor_op)\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
+       port map(clk,reset,left, right, op_detail, alu_state, xor_result);\r
        \r
        shift_inst : entity work.exec_op(shift_op)\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
+       port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
 \r
-calc: process(left_operand, right_operand, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
        variable result_v : alu_result_rec;\r
        variable res_prod : std_logic;\r
        variable cond_met : std_logic;\r
-       variable mem_en : std_logic;\r
+       variable mem_en : std_logic;
+        variable mem_op : std_logic;\r
 begin\r
        result_v := alu_state;\r
        \r
        result_v.result := add_result.result;\r
        res_prod := '1';\r
-       mem_en := '0';\r
-        addr <= add_result.result;\r
+       mem_en := '0';
+        mem_op := '0';\r
+        addr <= add_result.result;
+        left <= left_operand;
+        right <= right_operand;\r
        \r
        case cond is\r
        when COND_NZERO =>\r
@@ -101,8 +106,16 @@ begin
        when SHIFT_OP =>\r
                result_v := shift_result;
         when LDST_OP =>
+                res_prod := '0';
+                mem_op := '1';
                 if op_detail(IMM_OPT) = '1' then
                         result_v.result := right_operand;
+                        res_prod := '1';
+                        mem_op := '0';
+                end if;
+                if op_detail(ST_OPT) = '1' then
+                        right <= displacement;
+                        mem_en := '1';
                 end if;\r
        end case;\r
        \r
@@ -119,10 +132,9 @@ begin
        end if;\r
        \r
        result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
-       result_v.mem_en := mem_en and cond_met;\r
+       result_v.mem_en := mem_en and cond_met;
+        result_v.mem_op := mem_op and cond_met;\r
 \r
-        \r
-       data <= add_result.result;\r
        alu_result <= result_v;\r
        \r
 end process calc; \r

diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd
index 13285d9eb3e461f2463018c83a39a030f6ff986d..7e1562d5d161da0331bb8daccf0b20090f64b9c3 100755 (executable)
--- a/cpu/src/alu_pkg.vhd
+++ b/cpu/src/alu_pkg.vhd
@@ -84,11 +84,10 @@ package alu_pkg is
                        op_group : in op_info_t;
                        left_operand : in gp_register_t;
                        right_operand : in gp_register_t;
+                        displacement : in gp_register_t;
                        op_detail : in op_opt_t;
                        alu_state  : in alu_result_rec;
-                       alu_result : out alu_result_rec;
-                        addr : out gp_register_t;
-                        data : out gp_register_t
+                       alu_result : out alu_result_rec
                );
         end component alu;
        

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 8d3ac51d545c5283e9d5a6c935c21785f3f67d92..dd6350c8a020a5508e153033b99ed10aa185ed41 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -52,7 +52,8 @@ package common_pkg is
        constant ARITH_OPT : integer := 1;
        
        constant CARRY_OPT : integer := 2;
-       
+       constant ST_OPT  : integer := 2;
+
        constant RIGHT_OPT : integer := 3;
        
        constant NO_PSW_OPT : integer := 4;--no sharing

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index 8f97d9fdfdc49aff7fb0e292eaa86d2ddc03c5c4..87fb473a80d4ce750f7e502957cc0cbed81b416d 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -264,6 +264,7 @@ begin
                instr_s.reg_src1_addr := instruction(18 downto 15);     -- mem addr
                instr_s.displacement(14 downto 0) := instruction(14 downto 0);
                instr_s.op_detail(NO_PSW_OPT) := '1';
+                instr_s.op_detail(ST_OPT) := '1';
                instr_s.op_group := LDST_OP;
        end if;
 

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 73c7bf27e638d8cc0a063306cf22117f82f80d5f..79a36614762a2e5286f35e7be6c25ec683753c22 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -29,7 +29,7 @@ begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-         left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
+         left_operand, right_operand, dec_instr.displacement, op_detail, alu_state, alu_nxt);
 
 gpm_inst : gpm
         generic map(RESET_VALUE)
@@ -105,6 +105,9 @@ dmem_write_en <= alu_nxt.mem_en;
 hword <= alu_nxt.hw_op;
 --hword <= reg.result(1);
 byte_s <= alu_nxt.byte_op;
+
+addr <= alu_nxt.result;
+data <= right_operand;
 --byte_s <= reg.result(2);
 end behav;
 

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 6db0659bae58fa5baa8f7ac2a2f20d9db6ddf7ac..1093b1b479a4fa2921e13d4eb150265591cd49f4 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -17,6 +17,8 @@ architecture behaviour of r_w_ram is
                                    2 => "11101101000110000000000000100000", -- r3 = 4
                                    3 => "11100000001000010001100000000000", -- r4 = r2 + r3
                                    4 => "11100010001010100000100000000000", -- r5 = r4 and r1
+                                    5 => "11100111101010100000000000000001", -- stw r5,r4,1
+
                                  others => x"F0000000");
 
 --     signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1