cpu/src/execute_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.alu_pkg.all;
   7 use work.gpm_pkg.all;
   8
   9 architecture behav of execute_stage is
  10
  11 signal condition : condition_t;
  12 signal op_group : op_info_t;
  13 signal op_detail : op_opt_t;
  14 signal left_operand, right_operand : gp_register_t;
  15 signal alu_state, alu_nxt : alu_result_rec;
  16 signal psw : status_rec;
  17
  18 type exec_internal is record
  19         result : gp_register_t;
  20         res_addr : gp_addr_t;
  21         alu_jump : std_logic;
  22         brpr    : std_logic;
  23         wr_en   : std_logic;
  24 end record;
  25
  26 signal reg, reg_nxt : exec_internal;
  27
  28 begin
  29
  30 alu_inst : alu
  31 port map(clk, reset, condition, op_group,
  32          left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
  33
  34 gpm_inst : gpm
  35         generic map(RESET_VALUE)
  36         port map(clk,reset,alu_nxt,psw);
  37
  38 syn: process(clk, reset)
  39
  40 begin
  41
  42         if reset = RESET_VALUE then
  43                 reg.alu_jump <= '0';
  44                 reg.brpr <= '0';
  45                 reg.wr_en <= '0';
  46                 reg.result <= (others =>'0');
  47                 reg.res_addr <= (others => '0');
  48         elsif rising_edge(clk) then
  49                 reg <= reg_nxt;
  50         end if;
  51
  52 end process;
  53
  54 asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
  55 begin
  56
  57         condition <= dec_instr.condition;
  58         op_group <= dec_instr.op_group;
  59         op_detail <= dec_instr.op_detail;
  60
  61
  62
  63         alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0');
  64
  65
  66         if reset = RESET_VALUE then
  67                 condition <= COND_NEVER;
  68         else
  69
  70         end if;
  71
  72         reg_nxt.brpr <= alu_nxt.brpr;
  73         reg_nxt.alu_jump <= alu_nxt.alu_jump;
  74         reg_nxt.wr_en <= alu_nxt.reg_op;
  75         reg_nxt.result <= alu_nxt.result;
  76         reg_nxt.res_addr <= alu_nxt.result_addr;
  77
  78 end process asyn;
  79
  80 forward: process(regfile_val, reg_we, reg_addr, dec_instr)
  81 begin
  82         left_operand <= dec_instr.src1;
  83         right_operand <= dec_instr.src2;
  84
  85         if reg_we = '1' then
  86                 if dec_instr.saddr1 = reg_addr then
  87                         left_operand <= regfile_val;
  88                 end if;
  89                 if (dec_instr.saddr2 = reg_addr)  and  (dec_instr.op_detail(IMM_OPT) = '0') then
  90                         right_operand <= regfile_val;
  91                 end if;
  92         end if;
  93 end process forward;
  94
  95 result <= reg.result;
  96 result_addr <= reg.res_addr;
  97 alu_jump <= reg.alu_jump;
  98 brpr <= reg.brpr;
  99 wr_en <= reg.wr_en;
 100 dmem <= alu_nxt.mem_op;
 101 --dmem <= reg.result(4);
 102 dmem_write_en <= alu_nxt.mem_en;
 103 --dmem_write_en <= reg.result(0);
 104 --dmem_write_en <= '1';
 105 hword <= alu_nxt.hw_op;
 106 --hword <= reg.result(1);
 107 byte_s <= alu_nxt.byte_op;
 108 --byte_s <= reg.result(2);
 109 end behav;
 110