3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
8 use work.common_pkg.all;
11 architecture behav of decode_stage is
13 signal instr_spl : instruction_rec;
15 signal rtw_rec, rtw_rec_nxt : read_through_write_rec;
16 signal reg1_mem_data, reg2_mem_data, reg1_rd_data, reg2_rd_data : gp_register_t;
17 signal dec_op_inst, dec_op_inst_nxt : dec_op;
23 register_ram : r2_w_ram
32 instr_spl.reg_src1_addr,
33 instr_spl.reg_src2_addr,
41 decoder_inst : decoder
48 -- sync process for read through write registers
49 syn: process(clk, reset)
53 if (reset = RESET_VALUE) then
54 rtw_rec.rtw_reg <= (others => '0');
55 rtw_rec.rtw_reg1 <= '0';
56 rtw_rec.rtw_reg2 <= '0';
57 rtw_rec.immediate <= (others => '0');
58 rtw_rec.imm_set <= '0';
60 dec_op_inst.condition <= (others => '1');
61 dec_op_inst.op_detail <= (others => '0');
62 dec_op_inst.op_group <= ADDSUB_OP;
63 dec_op_inst.brpr <= '0'; --branch_prediction_bit;
64 dec_op_inst.src1 <= (others => '0');
65 dec_op_inst.src2 <= (others => '0');
66 dec_op_inst.saddr1 <= (others => '0');
67 dec_op_inst.saddr2 <= (others => '0');
68 dec_op_inst.daddr <= (others => '0');
71 elsif rising_edge(clk) then
72 rtw_rec <= rtw_rec_nxt;
73 dec_op_inst <= dec_op_inst_nxt;
78 -- type dec_op is record
79 -- condition : condition_t;
80 -- op_group : op_info_t;
81 -- op_detail : op_opt_t;
84 -- src1 : gp_register_t;
85 -- src2 : gp_register_t;
87 -- saddr1 : gp_addr_t;
88 -- saddr2 : gp_addr_t;
94 -- output logic incl. bypassing reg-file
95 output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
99 to_next_stage <= dec_op_inst;
100 to_next_stage.src1 <= reg1_rd_data;
101 to_next_stage.src2 <= reg2_rd_data;
106 -- fills output register
107 to_next: process(instr_spl)
110 dec_op_inst_nxt.condition <= instr_spl.predicates;
111 dec_op_inst_nxt.op_detail <= instr_spl.op_detail;
112 dec_op_inst_nxt.brpr <= instr_spl.bp; --branch_prediction_bit;
113 dec_op_inst_nxt.src1 <= (others => '0');
114 dec_op_inst_nxt.src2 <= (others => '0');
115 dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr;
116 dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
117 dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
118 dec_op_inst_nxt.op_group <= instr_spl.op_group;
122 -- async process: decides between memory and read-through-write buffer on output
123 output: process(rtw_rec, rtw_rec_nxt, reg1_mem_data, reg2_mem_data)
126 if ((rtw_rec.rtw_reg1) = '1') then
127 reg1_rd_data <= rtw_rec.rtw_reg;
129 reg1_rd_data <= reg1_mem_data;
132 if ((rtw_rec.rtw_reg2) = '1') then
133 reg2_rd_data <= rtw_rec.rtw_reg;
135 reg2_rd_data <= reg2_mem_data;
138 if (rtw_rec.imm_set = '1') then
139 reg2_rd_data <= rtw_rec.immediate;
145 -- async process: checks forward condition
146 forward: process(instr_spl, reg_w_addr, reg_wr_data, reg_we)
150 rtw_rec_nxt.rtw_reg <= reg_wr_data;
151 rtw_rec_nxt.rtw_reg1 <= '0';
152 rtw_rec_nxt.rtw_reg2 <= '0';
153 rtw_rec_nxt.immediate <= (others => '0');
154 rtw_rec_nxt.imm_set <= '0';
155 rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
156 rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
158 if (instr_spl.op_detail(IMM_OPT) = '1') then
159 rtw_rec_nxt.immediate <= instr_spl.immediate;
160 rtw_rec_nxt.imm_set <= '1';
163 if (reg_w_addr = instr_spl.reg_src1_addr) then
164 rtw_rec_nxt.rtw_reg1 <= ('1' and reg_we);
167 if (reg_w_addr = instr_spl.reg_src1_addr) then
168 rtw_rec_nxt.rtw_reg2 <= ('1' and reg_we);
174 -- async process: calculates branch prediction
175 br_pred: process(instr_spl)
179 branch_prediction_res <= (others => '0');
180 branch_prediction_bit <= '0';
182 if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
183 branch_prediction_res <= instr_spl.immediate; --both 32 bit
184 branch_prediction_bit <= '1';