test pipe 2
[calu.git] / cpu / sim / testcore.do
1 vlib work
2 vmap work work
3
4 vcom -work work ../src/mem_pkg.vhd
5 vcom -work work ../src/r_w_ram.vhd
6 vcom -work work ../src/r_w_ram_b.vhd
7 vcom -work work ../src/r2_w_ram.vhd
8 vcom -work work ../src/r2_w_ram_b.vhd
9 vcom -work work ../src/common_pkg.vhd
10 vcom -work work ../src/core_pkg.vhd
11 vcom -work work ../src/decoder.vhd
12 vcom -work work ../src/decoder_b.vhd
13 vcom -work work ../src/fetch_stage.vhd
14 vcom -work work ../src/fetch_stage_b.vhd
15 vcom -work work ../src/decode_stage.vhd
16 vcom -work work ../src/decode_stage_b.vhd
17
18 vcom -work work ../src/alu_pkg.vhd
19 vcom -work work ../src/extension_pkg.vhd
20 vcom -work work ../src/gpm_pkg.vhd
21
22 vcom -work work ../src/exec_op.vhd
23 vcom -work work ../src/exec_op/add_op_b.vhd
24 vcom -work work ../src/exec_op/and_op_b.vhd
25 vcom -work work ../src/exec_op/or_op_b.vhd
26 vcom -work work ../src/exec_op/xor_op_b.vhd
27 vcom -work work ../src/exec_op/shift_op_b.vhd
28
29 vcom -work work ../src/alu.vhd
30 vcom -work work ../src/alu_b.vhd
31
32 vcom -work work ../src/gpm.vhd
33 vcom -work work ../src/gpm_b.vhd
34
35 vcom -work work ../src/execute_stage.vhd
36 vcom -work work ../src/execute_stage_b.vhd
37
38
39 vcom -work work ../src/writeback_stage.vhd
40 vcom -work work ../src/writeback_stage_b.vhd
41
42 vcom -work work ../src/pipeline_tb.vhd
43
44 vsim work.pipeline_conf_beh -t ns
45
46 add wave  -format logic /pipeline_tb/sys_clk_pin
47 add wave  -format logic /pipeline_tb/sys_res_n_pin
48 add wave  -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
49 add wave  -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
50 add wave  -format logic /pipeline_tb/fetch_st/branch_prediction_bit
51 add wave  -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
52
53 add wave  -radix hexadecimal /pipeline_tb/decode_st/instruction
54 add wave  -radix hexadecimal /pipeline_tb/decode_st/instr_spl
55 add wave  -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
56 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
57 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
58 add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
59 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
60 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
61 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_we
62
63 add wave  -radix hexadecimal /pipeline_tb/exec_st/gpm_inst/psw
64
65 run 5000 ns