From 6878fe10bd720f714760a7e446c5a415828a1c2b Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Mon, 15 Nov 2010 19:55:31 +0100 Subject: [PATCH] test pipe 2 --- cpu/sim/testcore.do | 2 ++ cpu/src/alu_b.vhd | 33 +++++++-------------------------- cpu/src/alu_pkg.vhd | 12 ++++++------ cpu/src/decode_stage_b.vhd | 4 +++- cpu/src/exec_op/add_op_b.vhd | 7 +++---- cpu/src/r2_w_ram_b.vhd | 2 +- cpu/src/r_w_ram_b.vhd | 11 ++++++----- 7 files changed, 28 insertions(+), 43 deletions(-) diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do index 4f66a62..d0b5b33 100644 --- a/cpu/sim/testcore.do +++ b/cpu/sim/testcore.do @@ -60,4 +60,6 @@ add wave -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr add wave -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data add wave -radix hexadecimal /pipeline_tb/decode_st/reg_we +add wave -radix hexadecimal /pipeline_tb/exec_st/gpm_inst/psw + run 5000 ns diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index f3a25ee..a24ade8 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -25,17 +25,19 @@ architecture behaviour of alu is begin - add_inst : exec_op + add_inst : entity work.exec_op(add_op) port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result); - and_inst : exec_op + and_inst : entity work.exec_op(and_op) port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result); - or_inst : exec_op + + or_inst : entity work.exec_op(or_op) port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result); - xor_inst : exec_op + + xor_inst : entity work.exec_op(xor_op) port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result); - shift_inst : exec_op + shift_inst : entity work.exec_op(shift_op) port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result); calc: process(left_operand, right_operand, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result) @@ -121,24 +123,3 @@ end process calc; end architecture behaviour; -configuration alu_cfg of alu is - - for behaviour - for add_inst : exec_op - use entity work.exec_op(add_op); - end for; - for and_inst : exec_op - use entity work.exec_op(and_op); - end for; - for or_inst : exec_op - use entity work.exec_op(or_op); - end for; - for xor_inst : exec_op - use entity work.exec_op(xor_op); - end for; - for shift_inst : exec_op - use entity work.exec_op(shift_op); - end for; - end for; - -end configuration alu_cfg; diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd index ead1ac6..cc085c7 100755 --- a/cpu/src/alu_pkg.vhd +++ b/cpu/src/alu_pkg.vhd @@ -42,7 +42,7 @@ package alu_pkg is end record alu_result_rec; - constant SHIFT_WIDTH : integer := 1;--log2c(gp_register_t'length); + constant SHIFT_WIDTH : integer := log2c(gp_register_t'length); constant COND_ZERO : condition_t := "0001"; constant COND_NZERO : condition_t := "0000"; @@ -71,8 +71,8 @@ package alu_pkg is -- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec; -- function shift_op(left_operand, right_operand : gp_register_t; arith,sleft,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec; - - component alu is + + component alu is --some modules won't need all inputs port( --System inputs @@ -86,10 +86,10 @@ package alu_pkg is right_operand : in gp_register_t; op_detail : in op_opt_t; alu_state : in alu_result_rec; - alu_result : out alu_result_rec; - addr : out gp_register_t; + alu_result : out alu_result_rec; + addr : out gp_register_t; data : out gp_register_t - ); + ); end component alu; end package alu_pkg; diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd index fbaf010..d5ea647 100644 --- a/cpu/src/decode_stage_b.vhd +++ b/cpu/src/decode_stage_b.vhd @@ -57,8 +57,9 @@ begin rtw_rec.immediate <= (others => '0'); rtw_rec.imm_set <= '0'; - dec_op_inst.condition <= (others => '0'); + dec_op_inst.condition <= (others => '1'); dec_op_inst.op_detail <= (others => '0'); + dec_op_inst.op_group <= ADDSUB_OP; dec_op_inst.brpr <= '0'; --branch_prediction_bit; dec_op_inst.src1 <= (others => '0'); dec_op_inst.src2 <= (others => '0'); @@ -114,6 +115,7 @@ begin dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr; dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr; dec_op_inst_nxt.daddr <= (others => '0'); + dec_op_inst_nxt.op_group <= instr_spl.op_group; end process; diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd index 0e28af8..77cd901 100644 --- a/cpu/src/exec_op/add_op_b.vhd +++ b/cpu/src/exec_op/add_op_b.vhd @@ -30,8 +30,7 @@ begin complement := inc(not(right_operand)); l_neg := left_operand(gp_register_t'high); - --carry_res := unsigned('0' & left_operand)+addcarry; - carry_res := unsigned('0' & left_operand); + carry_res := unsigned('0' & left_operand)+addcarry; oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high)); if sub = '1' then @@ -49,9 +48,9 @@ begin alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range)); alu_result_v.status.carry := carry_res(carry_res'high); + -- alu_result_v.result := (0 => '1', others => '0'); - - alu_result_v.status.carry := oflo1 or oflo2; + alu_result_v.status.oflo := oflo1 or oflo2; --sign will be set globally. --zero will be set globally. diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd index d067ad3..a0b1639 100644 --- a/cpu/src/r2_w_ram_b.vhd +++ b/cpu/src/r2_w_ram_b.vhd @@ -13,7 +13,7 @@ architecture behaviour of r2_w_ram is signal ram : RAM_TYPE := ( 0 => x"00000000", 1 => x"00000001", - 2 => x"00000002", + 2 => x"FFFFFFFF", 3 => x"00000003", others=> x"00000000"); diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index c9de81a..3664ea1 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -10,11 +10,12 @@ architecture behaviour of r_w_ram is subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0); type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; - signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", - 1 => "11110000000000001001000000000000", - 2 => "11100000000010001001000000000000", - 3 => "11100001000110010111011001101100", - others => x"00000000"); + signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", -- r0 = r3 + r2 (always) + 1 => "11100101000000001000100000000010", -- r0 = r1 << 0 (always) + 2 => "11100000000010000001100000000000", -- r1 = r0 + r3 (always) + 3 => "11100000101000000001000000000000", + 4 => "11100001000110010111011001101100", + others => x"E0000000"); begin process(clk) -- 2.25.1