2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
10 use work.extension_uart_pkg.all;
12 architecture behav of extension_uart is
14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
15 signal new_bus_rx,new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
16 signal bd_rate : baud_rate_l;
17 signal rx_data : std_logic_vector(7 downto 0);
21 rs232_tx_inst : rs232_tx
35 w3_uart_send(byte_t'range),
41 rs232_rx_inst : rs232_rx
63 syn : process (clk, reset)
65 if (reset = RESET_VALUE) then
66 w1_st_co <= (others=>'0');
67 w2_uart_config(31 downto 16) <= (others=>'0');
68 -- todo mit einer konstante versehen
69 w2_uart_config(15 downto 0) <= x"01B2";
70 w3_uart_send <= (others=>'0');
71 w4_uart_receive <= (others=>'0');
75 elsif rising_edge(clk) then
76 w1_st_co <= w1_st_co_nxt;
77 w2_uart_config <= w2_uart_config_nxt;
78 w3_uart_send <= w3_uart_send_nxt;
79 w4_uart_receive <= w4_uart_receive_nxt;
80 new_tx_data <= new_tx_data_nxt;
85 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
87 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx)
89 variable tmp_data : gp_register_t;
93 w1_st_co_nxt <= w1_st_co;
94 w2_uart_config_nxt <= w2_uart_config;
95 w3_uart_send_nxt <= w3_uart_send;
96 w4_uart_receive_nxt <= w4_uart_receive;
98 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
99 tmp_data := (others =>'0');
100 if ext_reg.byte_en(0) = '1' then
101 tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
103 if ext_reg.byte_en(1) = '1' then
104 tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
106 if ext_reg.byte_en(2) = '1' then
107 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
109 if ext_reg.byte_en(3) = '1' then
110 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
113 case ext_reg.addr(1 downto 0) is
115 w1_st_co_nxt <= tmp_data;
117 w2_uart_config_nxt <= tmp_data;
119 w1_st_co_nxt(16) <= '1'; -- busy flag set
120 w3_uart_send_nxt <= tmp_data;
122 --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
127 if tx_rdy = '1' and tx_rdy_int = '0' then
128 w1_st_co_nxt(16) <= '0'; -- busy flag reset
131 if new_bus_rx = '1' then
132 w4_uart_receive_nxt(7 downto 0) <= rx_data;
133 w1_st_co_nxt(17) <= '1';
139 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
141 variable tmp_data : gp_register_t;
144 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
145 case ext_reg.addr(1 downto 0) is
147 tmp_data := (others =>'0');
148 if ext_reg.byte_en(0) = '1' then
149 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
151 if ext_reg.byte_en(1) = '1' then
152 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
154 if ext_reg.byte_en(2) = '1' then
155 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
157 if ext_reg.byte_en(3) = '1' then
158 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
160 data_out <= tmp_data;
162 tmp_data := (others =>'0');
163 if ext_reg.byte_en(0) = '1' then
164 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
166 if ext_reg.byte_en(1) = '1' then
167 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
169 if ext_reg.byte_en(2) = '1' then
170 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
172 if ext_reg.byte_en(3) = '1' then
173 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
175 data_out <= tmp_data;
177 tmp_data := (others =>'0');
178 if ext_reg.byte_en(0) = '1' then
179 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
181 if ext_reg.byte_en(1) = '1' then
182 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
184 if ext_reg.byte_en(2) = '1' then
185 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
187 if ext_reg.byte_en(3) = '1' then
188 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
190 data_out <= tmp_data;
192 tmp_data := (others =>'0');
193 if ext_reg.byte_en(0) = '1' then
194 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
196 if ext_reg.byte_en(1) = '1' then
197 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
199 if ext_reg.byte_en(2) = '1' then
200 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
202 if ext_reg.byte_en(3) = '1' then
203 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
205 data_out <= tmp_data;
209 data_out <= (others=>'0');
214 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
216 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
218 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
223 new_tx_data_nxt <= '0';
224 bd_rate <= w2_uart_config(15 downto 0);
226 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
227 case ext_reg.addr(1 downto 0) is
233 new_tx_data_nxt <= '1';
240 end process dataprocess;
244 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------