-+----------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-; bus_tx ; Output ; -- ; -- ; -- ; -- ;
-; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
-; sys_res ; Input ; OFF ; ON ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-; sys_clk ; ; ;
-; sys_res ; ; ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[26] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0 ; 1 ; ON ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr_nxt[6]~3 ; 1 ; ON ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X39_Y14_N6 ; 57 ; Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X38_Y18_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X36_Y12_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
-; execute_stage:exec_st|reg.result[1]~9 ; LC_X32_Y12_N1 ; 12 ; Sync. load ; no ; -- ; -- ;
-; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK3 ;
-; writeback_stage:writeback_st|Mux9~0 ; LC_X37_Y15_N8 ; 7 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X32_Y9_N2 ; 5 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X31_Y8_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X36_Y15_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|reg_we~0 ; LC_X35_Y14_N9 ; 8 ; Write enable ; no ; -- ; -- ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
++-----------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++----------+----------+---------------+---------------+-----------------------+-----+
+; bus_tx ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[0] ; Output ; -- ; -- ; -- ; -- ;
+; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
+; sys_res ; Input ; OFF ; ON ; -- ; -- ;
+; bus_rx ; Input ; ON ; ON ; -- ; -- ;
++----------+----------+---------------+---------------+-----------------------+-----+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+; sys_clk ; ; ;
+; sys_res ; ; ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[17] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[18] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[20] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[28] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[29] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[30] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.sel ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.condition[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
+; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1 ; 1 ; ON ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[8] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[9] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[10] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[12] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[15] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[17] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[16] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[21] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[0] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr_nxt[0]~1 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|tx_rdy_int ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6]~0 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5]~2 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7]~4 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4]~6 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2]~8 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1]~10 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3]~12 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0]~14 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[4] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.wr_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; 1 ; ON ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; bus_rx ; ; ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 1 ; ON ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; decode_stage:decode_st|decoder:decoder_inst|instr_s~10 ; LC_X36_Y12_N6 ; 10 ; Sync. load ; no ; -- ; -- ;
+; decode_stage:decode_st|rtw_rec_nxt.immediate[16]~28 ; LC_X36_Y12_N1 ; 9 ; Sync. clear ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X25_Y16_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X32_Y18_N0 ; 30 ; Clock enable ; no ; -- ; -- ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; LC_X21_Y16_N1 ; 31 ; Sync. clear ; no ; -- ; -- ;
+; sys_clk ; PIN_152 ; 538 ; Clock ; yes ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 504 ; Async. clear, Async. load, Clock enable ; yes ; Global Clock ; GCLK3 ;
+; writeback_stage:writeback_st|dmem_we~0 ; LC_X22_Y14_N4 ; 16 ; Write enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6]~0 ; LC_X21_Y11_N3 ; 28 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4]~33 ; LC_X22_Y18_N2 ; 16 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; LC_X22_Y18_N9 ; 9 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[7]~0 ; LC_X22_Y18_N9 ; 9 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; LC_X21_Y19_N3 ; 51 ; Sync. load ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X29_Y8_N2 ; 6 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0]~0 ; LC_X35_Y13_N0 ; 31 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15]~0 ; LC_X30_Y13_N6 ; 32 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0]~1 ; LC_X35_Y13_N9 ; 32 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|reg_we~11 ; LC_X29_Y17_N6 ; 7 ; Write enable ; no ; -- ; -- ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+