cpu/src/r_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r_w_ram is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13                                                                         -- r0 = 0, r1 = 1, r2 = 3, r3 = A
  14
  15         signal ram : RAM_TYPE := (
  16                         --8 => "11100111100010000000000000000000", --stw
  17 --      0 => "11101101000000000000000000000000",        --ldi
  18 --      1 => "11101101001000000000000000000000",        --ldi
  19 --      2 => "11100111101000000000000000000000",        --stw
  20 --      3 => "11100001000000000000000000100001",
  21 --      4 => "11101100100000000000001100000000",
  22 --      5 => "00001011011111111111111010000011",
  23 --      6 => "11101101000000000000000000001000",
  24 --      7 => "11100111100000000000000000001111",
  25 --      8 => "11100111100000000000000000010011",
  26
  27 --      9 => x"ed080048",       --;ldi r1, 9;;
  28 --      10 => x"ed500080",      --;ldil r10, list@lo ;; global pointer
  29 --      11 => x"fd500002",      --;ldih r10, list@hi;;
  30 --      12 => x"eb000107",      --;call+ fibcall;;
  31         --13 => x"eb7ffe03",    --;br+ main;;
  32 --      13 => "11101011000000000000000000000010",       -- endless loop --2; fib(n) {
  33                         --2;   if (list[n] > 0) {
  34                         --2;    return list[n]
  35                         --2;   }
  36                         --2;   a = fib(n-1)
  37                         --2;   list[n] = a + list[n-2]
  38                         --2;   return list[n]
  39                         --2; }
  40                         --3;fibcall;
  41                         --2;update counter for aligned access
  42 --      14 => x"e5088800",      --;lls r1, r1, 2 ;; *4
  43                         --2;calculate adress of top element
  44 --      15 => x"e0150800",      --;add r2, r10, r1;;
  45                         --3;fibmem;
  46                         --2;load top element
  47 --      16 => x"e7010000",      --;ldw r0, 0(r2);;
  48                         --2;compare if set
  49 --      17 => x"ec800000",      --;cmpi r0, 0;;
  50                         --2;return if set
  51 --      18 => x"0b000008",      --;retnz-;;
  52                         --2;decrement adress for next lopp
  53 --      19 => x"e1910020",      --;subi r2, r2, 4;;
  54                         --2;iterative call for n-1 element
  55 --      20 => x"eb7ffe07",      --;call+ fibmem;;
  56                         --2;load n-2 element
  57 --      21 => x"e7197ffc",      --;ldw r3, 0-4(r2);;
  58                         --2;add n-1 and n-2 element
  59 --      22 => x"e0018000",      --;add r0, r3, r0;;
  60                         --2;increment address for n element
  61                         --2;is needed because after return
  62                         --2;we need r2 to be set to the address
  63                         --2;of element n
  64 --      23 => x"e1110020",      --;addi r2, r2, 4;;
  65                         --2;store fib n
  66 --      24 => x"e7810000",      --;stw r0, 0(r2);;
  67 --      25 => x"eb00000a",      --;ret+;;
  68
  69 -- 1 1 2 3 5 8 13 21 34 55
  70
  71
  72                                   others => x"F0000000");
  73
  74 --      signal ram : RAM_TYPE := (  0 => "11101101000000000000000000000000", -- r0 = 0
  75 --
  76 --                                  1 => "11101101000010000000000000111000", -- r1 = 7
  77 --                                  2 => "11101101000100000000000000101000", -- r2 = 5
  78 --                                  3 => "11101101000110000000000000100000", -- r3 = 4
  79 --                                  4 => "11100000001000010001100000000000", -- r4 = r2 + r3
  80 --                                  5 => "11100010001010100000100000000000", -- r5 = r4 and r1
  81 --
  82 --                                  6 => "11100001000000000000000000001000", -- r0 = r0 + 1
  83 --                                  7 => "11101100100000000000000000011000", -- cmpi r0 , 2
  84 --
  85 --                                  8 => "00001011011111111111110010000111", -- jump -7
  86 --                                  9 => "11101011000000000000000010000010", -- jump +1
  87 --                                 --10 => "11101011000000000000000010000010", -- jump +1
  88 --
  89   --                                 10 => "11100111101010100000000000000001", -- stw r5,r4,1
  90         --                         11 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
  91 --
  92 --                                 12 => "11101011000000000000000000000010", -- jump +0
  93
  94
  95
  96
  97 --                                others => x"F0000000");
  98
  99 --      signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
 100 --                                  1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
 101 --                                  2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
 102 --                                  3 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
 103 --                                  4 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
 104 --                                  5 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
 105 --                                  6 => "11101100000000001000000000000000", --cmp r0 , r1       => 0-1 => 0100
 106 --                                  7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
 107 --                                  8 => "00000000001010101010000000000000", --addnq r5, r5, r4  => r5 = 4
 108 --                                  9 => "11101100001000100000000000000000", --cmp r4 , r4       => 2-2 => 1001
 109 --                                 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
 110 --                                 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
 111 --                                 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
 112 --                                 13 => "11100000000100001000000000000000", --add r2, r1, r0     => r2 = 1
 113 --                                 14 => "11100010000100001000000000000000", --and r2, r1, r0     => r2 = 0
 114 --                                 15 => "11101100000000001000000000000000", --cmp r0 , r1        => 0-1 => 0100
 115 --                                 16 => "10000000001010101010000000000001", --addabd r5, r5, r4  => r5 = 6
 116 --                                 17 => "10110011101110001000010000110001", --orxltd r7, 1086    => r7 = 1086
 117 --                                 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
 118 --                                 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
 119 --                                others => x"F0000000");
 120
 121
 122 begin
 123         process(clk)
 124         begin
 125                 if rising_edge(clk) then
 126                         -- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
 127                         case rd_addr is
 128                                 when "00000000000" => data_out <= x"ed2802d0"; -- ldi r5, 0x5a;;
 129                                 when "00000000100" => data_out <= x"ed008058"; -- ldi r0, 0x100b;;
 130                                 when "00000001000" => data_out <= x"e7a80000"; -- stw r5, 0(r0);;
 131                                 when others => data_out <= x"07a80000";
 132                         end case;
 133
 134                         if wr_en = '1' then
 135                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
 136                         end if;
 137                 end if;
 138         end process;
 139 end architecture behaviour;