added instruction rom/ram switch, added new data signaling bit in uart.

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 43603d29a9638626502ee2c9640678e2f3ed711c..d111b7da6241b9698ef15d7cb092fa51364f44b3 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -25,6 +25,7 @@ package common_pkg is
 
        constant INSTR_ADDR_WIDTH       : INTEGER := 32;
        constant PHYS_INSTR_ADDR_WIDTH  : INTEGER := 11;
+       constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
        constant REG_ADDR_WIDTH         : INTEGER := 4;
        constant DATA_ADDR_WIDTH        : INTEGER := 11;
        constant PHYS_DATA_ADDR_WIDTH   : INTEGER := 32;
@@ -33,6 +34,8 @@ package common_pkg is
        constant COND_WIDTH : INTEGER := 4;
        constant DATA_END_ADDR          : integer := ((2**DATA_ADDR_WIDTH)-1);
 
+       constant ROM_USE : std_logic := '1';
+       constant RAM_USE : std_logic := '0';
        
        subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
        subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 45150df71a87a78286eb50fdb4e716f9cc27a23f..2eda02bcd7b6a8390d20386d14c472b0d4c67a82 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -15,6 +15,9 @@ signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send,
 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
 signal         bd_rate : baud_rate_l;
 signal rx_data : std_logic_vector(7 downto 0);
+
+signal uart_data_read, uart_data_read_nxt : std_logic;
+
 begin
 
 
@@ -62,29 +65,31 @@ port map(
 
 syn : process (clk, reset)
 begin
-        if (reset = RESET_VALUE) then
-               w1_st_co <= (others=>'0');
-               w2_uart_config(31 downto 16) <= (others=>'0');
-               -- todo mit einer konstante versehen
-               w2_uart_config(15 downto 0) <= x"01B2";
-               w3_uart_send <= (others=>'0');
-               w4_uart_receive <= (others=>'0');
-               tx_rdy_int <= '0';
-               new_tx_data <= '0';
-
-        elsif rising_edge(clk) then            
-               w1_st_co <= w1_st_co_nxt;
-               w2_uart_config <= w2_uart_config_nxt;
-               w3_uart_send <= w3_uart_send_nxt;
-               w4_uart_receive <= w4_uart_receive_nxt;
-               new_tx_data <= new_tx_data_nxt;
-               tx_rdy_int <= tx_rdy;
-        end if;
+   if (reset = RESET_VALUE) then
+                       w1_st_co <= (others=>'0');
+                       w2_uart_config(31 downto 16) <= (others=>'0');
+                       -- todo mit einer konstante versehen
+                       w2_uart_config(15 downto 0) <= x"01B2";
+                       w3_uart_send <= (others=>'0');
+                       w4_uart_receive <= (others=>'0');
+                       tx_rdy_int <= '0';
+                       new_tx_data <= '0';
+                       uart_data_read <= '0';
+
+       elsif rising_edge(clk) then            
+                       w1_st_co <= w1_st_co_nxt;
+                       w2_uart_config <= w2_uart_config_nxt;
+                       w3_uart_send <= w3_uart_send_nxt;
+                       w4_uart_receive <= w4_uart_receive_nxt;
+                       new_tx_data <= new_tx_data_nxt;
+                       tx_rdy_int <= tx_rdy;
+                       uart_data_read <= uart_data_read_nxt;
+   end if;
 end process syn;
 
 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
 
-gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx)
+gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
 
 variable tmp_data  : gp_register_t;
 
@@ -133,7 +138,10 @@ begin
                w1_st_co_nxt(17) <= '1';
        end if;
        
-
+       if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then
+               w1_st_co_nxt(17) <= '0';
+       end if;
+       
 end process gwriten;
 
 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
@@ -141,6 +149,9 @@ gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receiv
 variable tmp_data  : gp_register_t;
 
 begin
+
+       uart_data_read_nxt <= '0';
+
        if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
                case ext_reg.addr(1 downto 0) is
                when "00" => 
@@ -189,7 +200,8 @@ begin
                        end if;
                        data_out <= tmp_data;
                when "11" =>
-                       tmp_data := (others =>'0');                     
+                       tmp_data := (others =>'0');     
+                       uart_data_read_nxt <= '1';
                        if ext_reg.byte_en(0) = '1' then
                                tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
                        end if;

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index e1faf1fd819cd8680904b1a097bfd217e61250e0..1ff0fad814872a115dcfba8b1fd80baa0a1bdb4d 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -13,7 +13,8 @@ signal instr_r_addr    : instruction_addr_t;
 signal instr_r_addr_nxt  : instruction_addr_t;
 signal instr_we         : std_logic;
 signal instr_wr_data    : instruction_word_t;
-signal instr_rd_data    : instruction_word_t;
+signal instr_rd_data_rom, instr_rd_data         : instruction_word_t;
+signal rom_ram, rom_ram_nxt : std_logic;
 
 begin
 
@@ -31,6 +32,19 @@ begin
                        instr_wr_data,
                        instr_rd_data
                );
+               
+       instruction_rom : rom
+               generic map (
+                       ROM_INSTR_ADDR_WIDTH,
+                       WORD_WIDTH
+               )
+               
+               port map (
+                       clk,
+                       instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
+                       instr_rd_data_rom
+               );
+               
 
 syn: process(clk, reset)
 
@@ -38,20 +52,36 @@ begin
 
        if (reset = RESET_VALUE) then
                instr_r_addr <= (others => '0');
+               rom_ram <= ROM_USE;
        elsif rising_edge(clk) then
                instr_r_addr <= instr_r_addr_nxt;               
+               rom_ram <= rom_ram_nxt;
        end if;
        
 end process; 
 
 
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
+asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom)
 
 begin
 
-       instruction <= instr_rd_data;
+       rom_ram_nxt <= rom_ram;
+
+       case rom_ram is
+               when ROM_USE =>
+                       instruction <= instr_rd_data_rom;
+               when RAM_USE =>
+                       instruction <= instr_rd_data;
+               when others => 
+                       instruction <= x"F0000000";
+       end case;
        instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
 
+       if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1') then
+               rom_ram_nxt <= RAM_USE;
+               instr_r_addr_nxt <= (others => '0');
+       end if;
+       
        if (reset = RESET_VALUE) then
                instr_r_addr_nxt <= (others => '0');
        end if;

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
index 2c66fb34d5b60d52f9e9888ea8e63186dd757f43..906f175f8ca9d552899f45225cd24042a05a48fe 100644 (file)
--- a/cpu/src/mem_pkg.vhd
+++ b/cpu/src/mem_pkg.vhd
@@ -52,13 +52,9 @@ package mem_pkg is
                --System inputs
                        clk : in std_logic;
                --Input
-                       wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-                       
-                       wr_en : in std_logic;
-                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
-                       
+                       rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);                   
                --Output
-                       data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
+                       data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
        end component rom;
        

diff --git a/cpu/src/rom.vhd b/cpu/src/rom.vhd
index 7de1beb5b7b3150b1606bad6b746e95a060175ac..65e639410b7660ccfdd6f46587afabfb1f8a5d6a 100644 (file)
--- a/cpu/src/rom.vhd
+++ b/cpu/src/rom.vhd
@@ -11,11 +11,7 @@ entity rom is
                --System inputs
                        clk : in std_logic;
                --Input
-                       wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-                       
-                       wr_en : in std_logic;
-                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
-                       
+                       rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);                   
                --Output
                        data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
                );

diff --git a/cpu/src/rom_b.vhd b/cpu/src/rom_b.vhd
index 140b76c2981f12e0f649cfa41db1d5cad1222e49..df24abcb72c5cf3cd9fccd6ef29068f462cbc37c 100644 (file)
--- a/cpu/src/rom_b.vhd
+++ b/cpu/src/rom_b.vhd
@@ -7,12 +7,7 @@ use work.mem_pkg.all;
 
 architecture behaviour of rom is
 
-       subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
-       type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
-       
-                                                                       -- r0 = 0, r1 = 1, r2 = 3, r3 = A
-
-       signal rrrr_addr : std_logic_vector(31 downto 0);
+       signal vsim_bug : std_logic_vector(31 downto 0);
        
 begin
        process(clk)
@@ -21,8 +16,8 @@ begin
 --              data_out <= ram(to_integer(UNSIGNED(rd_addr)));
 
 
-       case rrrr_addr(10 downto 0) is
-
+       --case rrrr_addr(10 downto 0) is
+                       case vsim_bug(6 downto 0) is
        -- fibonacci
 --                             when "00000000000" => data_out <= "11101101000000000000000000000000"; -- 
 --                             when "00000000001" => data_out <= "11101101001000000000000000000000"; -- 
@@ -79,17 +74,41 @@ begin
 --1;00000020;e1218000;addi r4, r3, 0;;
 --1;00000024;eb7ffb81;br 0;;
                        
-                               when "00000000000" => data_out <= x"ed010058";
-                               when "00000000001" => data_out <= x"ed090060";
-                               when "00000000010" => data_out <= x"ed110080"; --x"e7188000";  f
-                               when "00000000011" => data_out <= x"e7188000"; --x"ec1a0000";
-                               when "00000000100" => data_out <= x"ec1a0000";
-                               when "00000000101" => data_out <= x"1b7ffe01";
-                               when "00000000110" => data_out <= x"e7990000"; -- f
-                               when "00000000111" => data_out <= x"e7980000";
-                               when "00000001000" => data_out <= x"e1218000";
-                               when "00000001001" => data_out <= x"eb7ffb81";
+--                             when "0000000" => data_out <= x"ed010058";
+--                             when "0000001" => data_out <= x"ed090060";
+--                             when "0000010" => data_out <= x"ed110080"; --x"e7188000";  f
+--                             when "0000011" => data_out <= x"e7188000"; --x"ec1a0000";
+--                             when "0000100" => data_out <= x"ec1a0000";
+--                             when "0000101" => data_out <= x"1b7ffe01";
+--                             when "0000110" => data_out <= x"e7990000"; -- f
+--                             when "0000111" => data_out <= x"e7980000";
+--                             when "0001000" => data_out <= x"e1218000";
+--                             when "0001001" => data_out <= x"eb7ffb81";
 
+--1;00000000;ed010058;ldi r0, 0x200B;;;
+--1;00000004;ed090060;ldi r1, 0x200C;;;
+--1;00000008;ed110080;ldi r2, 0x2010;;;
+--1;0000000c;ed390078;ldi r7, 0x200F;;;
+--1;00000010;ed480012;ldih r9, 0x0002;;;
+--1;00000014;e7438000;ldw r8, 0(r7);;;
+--1;00000018;e254c000;and r10, r9, r8;;;
+--1;0000001c;07188000;ldwnz r3, 0(r1);;;
+--1;00000020;07980000;stwnz r3, 0(r0);;;
+--1;00000024;07990000;stwnz r3, 0(r2);;;
+--1;00000028;eb7ffb01;br 0;;;
+
+
+                               when "0000000" => data_out <= x"ed010058";
+                               when "0000001" => data_out <= x"ed090060";
+                               when "0000010" => data_out <= x"ed110080"; --x"e7188000";  f
+                               when "0000011" => data_out <= x"ed390000"; --x"ec1a0000";
+                               when "0000100" => data_out <= x"ed480012";
+                               when "0000101" => data_out <= x"e7438000";
+                               when "0000110" => data_out <= x"e254c000"; -- f
+                               when "0000111" => data_out <= x"07188000";
+                               when "0001000" => data_out <= x"07980000";
+                               when "0001001" => data_out <= x"07990000";
+                               when "0001010" => data_out <= x"eb7ffb81";
                                
                                                        
 --                             when "00000000000" => data_out <= x"ed000000";
@@ -107,12 +126,9 @@ begin
                                when others => data_out <= "11101011000000000000000000000010";
 
                        end case;
-                       
-                       if wr_en = '1' then
-                       end if;
                end if;
        end process;
        
-       rrrr_addr(10 downto 0) <= rd_addr;
-       rrrr_addr(31 downto 11) <= (others => '0');
+       vsim_bug(6 downto 0) <= rd_addr;
+       vsim_bug(31 downto 7) <= (others => '0');
 end architecture behaviour;