cpu/src/fetch_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.core_pkg.all;
   6 use work.common_pkg.all;
   7 use work.mem_pkg.all;
   8
   9 architecture behav of fetch_stage is
  10
  11 signal instr_w_addr      : instruction_addr_t;
  12 signal instr_r_addr      : instruction_addr_t;
  13 signal instr_r_addr_nxt  : instruction_addr_t;
  14 signal instr_we          : std_logic;
  15 signal instr_wr_data     : instruction_word_t;
  16 signal instr_rd_data_rom, instr_rd_data          : instruction_word_t;
  17 signal rom_ram, rom_ram_nxt : std_logic;
  18
  19 begin
  20
  21         instruction_ram : r_w_ram --rom
  22                 generic map (
  23                         PHYS_INSTR_ADDR_WIDTH,
  24                         WORD_WIDTH
  25                 )
  26
  27                 port map (
  28                         clk,
  29                         instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  30                         instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  31                         instr_we,
  32                         instr_wr_data,
  33                         instr_rd_data
  34                 );
  35
  36         instruction_rom : rom
  37                 generic map (
  38                         ROM_INSTR_ADDR_WIDTH,
  39                         WORD_WIDTH
  40                 )
  41
  42                 port map (
  43                         clk,
  44                         instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
  45                         instr_rd_data_rom
  46                 );
  47
  48
  49 syn: process(clk, reset)
  50
  51 begin
  52
  53         if (reset = RESET_VALUE) then
  54                 instr_r_addr <= (others => '0');
  55                 rom_ram <= ROM_USE;
  56         elsif rising_edge(clk) then
  57                 instr_r_addr <= instr_r_addr_nxt;
  58                 rom_ram <= rom_ram_nxt;
  59         end if;
  60
  61 end process;
  62
  63
  64 asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom)
  65
  66 begin
  67
  68         rom_ram_nxt <= rom_ram;
  69
  70         case rom_ram is
  71                 when ROM_USE =>
  72                         instruction <= instr_rd_data_rom;
  73                 when RAM_USE =>
  74                         instruction <= instr_rd_data;
  75                 when others =>
  76                         instruction <= x"F0000000";
  77         end case;
  78         instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
  79
  80         if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1') then
  81                 rom_ram_nxt <= RAM_USE;
  82                 instr_r_addr_nxt <= (others => '0');
  83         end if;
  84
  85         if (reset = RESET_VALUE) then
  86                 instr_r_addr_nxt <= (others => '0');
  87         end if;
  88
  89         if (alu_jump_bit = LOGIC_ACT) then
  90                 instr_r_addr_nxt <= jump_result;
  91                 instruction(31 downto 28) <= "1111";
  92         elsif (branch_prediction_bit = LOGIC_ACT) then
  93                 instr_r_addr_nxt <= prediction_result;
  94         end if;
  95
  96 end process;
  97
  98 prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
  99 prog_cnt(31 downto 11) <= (others => '0');
 100
 101 end behav;
 102