library ieee;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.mem_pkg.all;

architecture behaviour of r_w_ram is

	subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
	type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
	
	signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
				  1 => "11100101000000001000100000000010",  -- r0 = r1 << 0 (always)
				  2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
				  3 => "11100000101000000001000000000000",
				  4 => "11100001000110010111011001101100", 
				  others => x"F0000000");

begin
	process(clk)
	begin
		if rising_edge(clk) then
			data_out <= ram(to_integer(UNSIGNED(rd_addr)));
			
			if wr_en = '1' then
				ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
			end if;
		end if;
	end process;
end architecture behaviour;