removed 7seg from DT

[calu.git] / cpu / src / extension_b.vhd

diff --git a/cpu/src/extension_b.vhd b/cpu/src/extension_b.vhd
index a035511b1284e489e2d14ee37d95175ace76c738..bff38e9a11c80fa38e1044e0c1560f932ebde021 100644 (file)
--- a/cpu/src/extension_b.vhd
+++ b/cpu/src/extension_b.vhd
@@ -9,28 +9,68 @@ use work.mem_pkg.all;
 use work.extension_pkg.all;
 
 architecture behav of extension_gpm is
+
+type pointers_t is array( 0 to ((2**(paddr_t'length))-1)) of ext_addr_t;
+
 type gpm_internal is record
-        status : status_rec;
+    status : status_rec;
+       preg : pointers_t;
 end record gpm_internal;
 
 signal reg, reg_nxt : gpm_internal;
 
+
 begin
 syn : process (clk, reset)
 begin
         if (reset = RESET_VALUE) then
-                reg.status <= ('0','0','0','0');
+                reg.status <= (others=>'0');
+               reg.preg <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,reg.preg(0)'length))));
         elsif rising_edge(clk) then
                 reg <= reg_nxt;
         end if;
 end process syn;
 
-asyn : process (clk, reset, alu_nxt)
+asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr)
+       variable reg_nxt_v : gpm_internal;
+       variable incb : ext_addr_t;
+       variable sel_pval, sel_pval_nxt : ext_addr_t;
+       
+       variable data_out_v : gp_register_t;
+       variable data_v : gp_register_t;
+       variable tmp_data  : gp_register_t;
+       
 begin
-        reg_nxt.status <= alu_nxt.status;
-end process asyn;
+       reg_nxt_v := reg;
+       data_v  := ext_reg.data;
 
-psw <= reg.status;
+       psw <= reg.status;
+       
+       data_out_v := (others => '0');
+
+       incb(0) := '1';
+       if pinc = '1' then
+               incb(incb'high downto 1) := (others => '1');
+       else
+               incb(incb'high downto 1) := (others => '0');
+       end if;
+
+       sel_pval:= reg_nxt_v.preg(0);
+       sel_pval_nxt := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
+       if pwr_en = '1' then
+               reg_nxt_v.preg(0) := sel_pval_nxt;
+       end if;
+
+       reg_nxt_v.status := psw_nxt;
+       
+       reg_nxt <= reg_nxt_v;
+       data_out <= data_out_v;
+       
+       pval <= (others =>'0');
+       pval(pval'high downto BYTEADDR) <= sel_pval;
+       pval_nxt <= (others =>'0');
+       pval_nxt(pval'high downto BYTEADDR) <= sel_pval_nxt;
+end process asyn;
 
 end behav;