2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
11 architecture behav of extension_gpm is
13 type pointers_t is array( 0 to ((2**(paddr_t'length))-1)) of ext_addr_t;
15 type gpm_internal is record
18 end record gpm_internal;
20 signal reg, reg_nxt : gpm_internal;
24 syn : process (clk, reset)
26 if (reset = RESET_VALUE) then
27 reg.status <= (others=>'0');
28 reg.preg <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,reg.preg(0)'length))));
29 elsif rising_edge(clk) then
34 asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr)
35 variable reg_nxt_v : gpm_internal;
36 variable incb : ext_addr_t;
37 variable sel_pval, sel_pval_nxt : ext_addr_t;
39 variable data_out_v : gp_register_t;
40 variable data_v : gp_register_t;
41 variable tmp_data : gp_register_t;
45 data_v := ext_reg.data;
49 data_out_v := (others => '0');
53 incb(incb'high downto 1) := (others => '1');
55 incb(incb'high downto 1) := (others => '0');
58 sel_pval:= reg_nxt_v.preg(0);
59 sel_pval_nxt := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
61 reg_nxt_v.preg(0) := sel_pval_nxt;
64 reg_nxt_v.status := psw_nxt;
67 data_out <= data_out_v;
69 pval <= (others =>'0');
70 pval(pval'high downto BYTEADDR) <= sel_pval;
71 pval_nxt <= (others =>'0');
72 pval_nxt(pval'high downto BYTEADDR) <= sel_pval_nxt;