removed 7seg from DT
[calu.git] / cpu / src / extension_b.vhd
index 0c18a7de2da98d6ab9b8a0348d769442436130f1..bff38e9a11c80fa38e1044e0c1560f932ebde021 100644 (file)
@@ -9,8 +9,11 @@ use work.mem_pkg.all;
 use work.extension_pkg.all;
 
 architecture behav of extension_gpm is
+
+type pointers_t is array( 0 to ((2**(paddr_t'length))-1)) of ext_addr_t;
+
 type gpm_internal is record
-        status : status_rec;
+    status : status_rec;
        preg : pointers_t;
 end record gpm_internal;
 
@@ -21,94 +24,52 @@ begin
 syn : process (clk, reset)
 begin
         if (reset = RESET_VALUE) then
-                reg.status <= ('0','0','0','0');
-               reg.pointers <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,DATA_ADDR_WIDTH)));
+                reg.status <= (others=>'0');
+               reg.preg <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,reg.preg(0)'length))));
         elsif rising_edge(clk) then
                 reg <= reg_nxt;
         end if;
 end process syn;
 
-asyn : process (clk, reset, reg, alu_nxt, ext_reg, pval, pwr_en, pinc, paddr)
+asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr)
        variable reg_nxt_v : gpm_internal;
-       variable incb : gp_register_t;
-       variable sel_pval : gp_register_t;
+       variable incb : ext_addr_t;
+       variable sel_pval, sel_pval_nxt : ext_addr_t;
+       
+       variable data_out_v : gp_register_t;
+       variable data_v : gp_register_t;
+       variable tmp_data  : gp_register_t;
+       
 begin
        reg_nxt_v := reg;
+       data_v  := ext_reg.data;
 
        psw <= reg.status;
-       data_out <= (others => '0');
+       
+       data_out_v := (others => '0');
 
-       incb := (others => '0');
        incb(0) := '1';
        if pinc = '1' then
-               incb := (others => '1');
-       end if;
-
-       if (ext_reg.sel = '1') and ext_reg.wr_en = '1' then
-               case ext_reg.addr(1 downto 0) is
-               when "00" => 
-                       if ext_reg.byte_en(0) = '1' then
-                               reg_nxt_v.psw := (ext_reg.data(0),ext_reg.data(1),ext_reg.data(3),ext_reg.data(2));
-                               psw <= reg_nxt_v.psw;
-                       end if;
-               when "01" =>
-                       --STACK_POINTER
-                       if ext_reg.byte_en(0) = '1' then
-                               reg_next_v.preg(0)(byte_t'range) := ext_reg.data(byte_t'range);
-                       end if;
-                       if ext_reg.byte_en(1) = '1' then
-                               reg_next_v.preg(0)((byte_t'length*2)-1 downto byte_t'length) :=
-                                       ext_reg.data((byte_t'length*2)-1 downto byte_t'length) ;
-                       end if;
-                       if ext_reg.byte_en(2) = '1' then
-                               reg_next_v.preg(0)((byte_t'length*3)-1 downto byte_t'length*2) :=
-                                       ext_reg.data((byte_t'length*3)-1 downto byte_t'length*2) ;
-                       end if;
-                       if ext_reg.byte_en(3) = '1' then
-                               reg_next_v.preg(0)((byte_t'length*4)-1 downto byte_t'length*3) :=
-                                       ext_reg.data((byte_t'length*4)-1 downto byte_t'length*3) ;
-                       end if;
-               when others => null;
-               end case;
+               incb(incb'high downto 1) := (others => '1');
+       else
+               incb(incb'high downto 1) := (others => '0');
        end if;
 
-       if (ext_reg.sel = '1') and wr_en = '0' then
-               case ext_reg.addr(1 downto 0) is
-               when "00" => 
-                       if ext_reg.byte_en(0) = '1' then
-                               data_out(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero);
-                       end if;
-               when "01" =>
-                       --STACK_POINTER
-                       if ext_reg.byte_en(0) = '1' then
-                               data_out(byte_t'range) <= reg.preg(0)(byte_t'range);
-                       end if;
-                       if ext_reg.byte_en(1) = '1' then
-                               data_out((byte_t'length*2)-1 downto byte_t'length) <=
-                                       reg_preg(0)((byte_t'length*2)-1 downto byte_t'length) ;
-                       end if;
-                       if ext_reg.byte_en(2) = '1' then
-                               data_out((byte_t'length*3)-1 downto 2*byte_t'length) <=
-                                       reg_preg(0)((byte_t'length*3)-1 downto 2*byte_t'length) ;
-                       end if;
-                       if ext_reg.byte_en(3) = '1' then
-                               data_out((byte_t'length*4)-1 downto 3*byte_t'length) <=
-                                       reg_preg(0)((byte_t'length*4)-1 downto 3*byte_t'length) ;
-                       end if;
-               when others => null;
-               end case;
-       end if;
-
-
-       sel_pval := reg_nxt_v.preg(unsigned(paddr));
-       pval <= sel_pval;
+       sel_pval:= reg_nxt_v.preg(0);
+       sel_pval_nxt := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
        if pwr_en = '1' then
-               reg_nxt_v.preg(to_integer(unsigned(paddr))) := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
+               reg_nxt_v.preg(0) := sel_pval_nxt;
        end if;
 
-       reg_nxt_v.status := alu_nxt.status;
+       reg_nxt_v.status := psw_nxt;
        
        reg_nxt <= reg_nxt_v;
+       data_out <= data_out_v;
+       
+       pval <= (others =>'0');
+       pval(pval'high downto BYTEADDR) <= sel_pval;
+       pval_nxt <= (others =>'0');
+       pval_nxt(pval'high downto BYTEADDR) <= sel_pval_nxt;
 end process asyn;
 
 end behav;