set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
+ #warning fix fuer pll
+ set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
+ lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
compensate_clock => "CLK0",
inclk0_input_frequency => 30003,
intended_device_family => "Stratix",
+ lpm_hint => "CBX_MODULE_PREFIX=vpll2",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON