); \r
end component exec_op;\r
\r
- signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
+ signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
+ signal left, right : gp_register_t;\r
\r
begin\r
\r
add_inst : entity work.exec_op(add_op)\r
- port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result);\r
+ port map(clk,reset,left, right, op_detail, alu_state, add_result);\r
\r
and_inst : entity work.exec_op(and_op)\r
- port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
+ port map(clk,reset,left, right, op_detail, alu_state, and_result);\r
\r
or_inst : entity work.exec_op(or_op)\r
- port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
+ port map(clk,reset,left, right, op_detail, alu_state, or_result);\r
\r
xor_inst : entity work.exec_op(xor_op)\r
- port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
+ port map(clk,reset,left, right, op_detail, alu_state, xor_result);\r
\r
shift_inst : entity work.exec_op(shift_op)\r
- port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
+ port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
\r
-calc: process(left_operand, right_operand, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
variable result_v : alu_result_rec;\r
variable res_prod : std_logic;\r
variable cond_met : std_logic;\r
- variable mem_en : std_logic;\r
+ variable mem_en : std_logic;
+ variable mem_op : std_logic;\r
begin\r
result_v := alu_state;\r
\r
result_v.result := add_result.result;\r
res_prod := '1';\r
- mem_en := '0';\r
- addr <= add_result.result;\r
+ mem_en := '0';
+ mem_op := '0';\r
+ addr <= add_result.result;
+ left <= left_operand;
+ right <= right_operand;\r
\r
case cond is\r
when COND_NZERO =>\r
when SHIFT_OP =>\r
result_v := shift_result;
when LDST_OP =>
+ res_prod := '0';
+ mem_op := '1';
if op_detail(IMM_OPT) = '1' then
result_v.result := right_operand;
+ res_prod := '1';
+ mem_op := '0';
+ end if;
+ if op_detail(ST_OPT) = '1' then
+ right <= displacement;
+ mem_en := '1';
end if;\r
end case;\r
\r
end if;\r
\r
result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
- result_v.mem_en := mem_en and cond_met;\r
+ result_v.mem_en := mem_en and cond_met;
+ result_v.mem_op := mem_op and cond_met;\r
\r
- \r
- data <= add_result.result;\r
alu_result <= result_v;\r
\r
end process calc; \r