dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
+ if (GET_GLOBAL(HaveRunInit))
+ return 0;
+
u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
int bdf = GET_GLOBAL(VgaBDF);
if (CONFIG_VGA_PCI && bdf >= 0) {
return -1;
dprintf(1, "cirrus init 2\n");
+ // memory setup
+ stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
+ // set vga mode
+ stdvga_sequ_write(0x07, 0x00);
+ // reset bitblt
+ stdvga_grdc_write(0x31, 0x04);
+ stdvga_grdc_write(0x31, 0x00);
+
+ if (GET_GLOBAL(HaveRunInit))
+ return 0;
+
u32 lfb_addr = 0;
int bdf = GET_GLOBAL(VgaBDF);
if (CONFIG_VGA_PCI && bdf >= 0)
SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
SET_VGA(VBE_win_granularity, 16);
- // memory setup
- stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
- // set vga mode
- stdvga_sequ_write(0x07, 0x00);
- // reset bitblt
- stdvga_grdc_write(0x31, 0x04);
- stdvga_grdc_write(0x31, 0x00);
-
return 0;
}
}
int VgaBDF VAR16 = -1;
+int HaveRunInit VAR16;
void VISIBLE16
vga_post(struct bregs *regs)
{
debug_enter(regs, DEBUG_VGA_POST);
- if (CONFIG_VGA_PCI) {
+ if (CONFIG_VGA_PCI && !GET_GLOBAL(HaveRunInit)) {
u16 bdf = regs->ax;
if ((pci_config_readw(bdf, PCI_VENDOR_ID)
== GET_GLOBAL(rom_pci_data.vendor))
return;
}
+ if (GET_GLOBAL(HaveRunInit))
+ return;
+
init_bios_area();
SET_VGA(video_save_pointer_table.videoparam
// XXX - clear screen and display info
+ SET_VGA(HaveRunInit, 1);
+
// Fixup checksum
extern u8 _rom_header_size, _rom_header_checksum;
SET_VGA(_rom_header_checksum, 0);
// vgabios.c
extern int VgaBDF;
+extern int HaveRunInit;
#define SET_VGA(var, val) SET_FARVAR(get_global_seg(), (var), (val))
struct carattr {
u8 car, attr, use_attr;