} while (status & ATA_CB_STAT_BSY);
success = (0x00 == (status & (ATA_CB_STAT_BSY | ATA_CB_STAT_DF |
- ATA_CB_STAT_DRQ | ATA_CB_STAT_ERR)) &&
+ ATA_CB_STAT_ERR)) &&
ATA_CB_STAT_RDY == (status & (ATA_CB_STAT_RDY)));
if (success) {
dprintf(2, "AHCI/%d: ... finished, status 0x%x, OK\n", pnr,
u32 val, count = 0;
val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
- while (val & ((1 << 7) /* BSY */ |
- (1 << 3) /* DRQ */)) {
+ while (val & ATA_CB_STAT_BSY) {
ndelay(500);
val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
count++;