1 // Low level AHCI disk access
3 // Copyright (C) 2010 Gerd Hoffmann <kraxel@redhat.com>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "types.h" // u8
8 #include "ioport.h" // inb
9 #include "util.h" // dprintf
10 #include "biosvar.h" // GET_EBDA
11 #include "pci.h" // foreachpci
12 #include "pci_ids.h" // PCI_CLASS_STORAGE_OTHER
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
14 #include "boot.h" // add_bcv_hd
15 #include "disk.h" // struct ata_s
16 #include "ata.h" // ATA_CB_STAT
17 #include "ahci.h" // CDB_CMD_READ_10
18 #include "blockcmd.h" // CDB_CMD_READ_10
20 #define AHCI_MAX_RETRIES 5
22 /****************************************************************
23 * these bits must run in both 16bit and 32bit modes
24 ****************************************************************/
25 u8 *ahci_buf_fl VAR16VISIBLE;
27 // prepare sata command fis
28 static void sata_prep_simple(struct sata_cmd_fis *fis, u8 command)
30 memset_fl(fis, 0, sizeof(*fis));
31 SET_FLATPTR(fis->command, command);
34 static void sata_prep_readwrite(struct sata_cmd_fis *fis,
35 struct disk_op_s *op, int iswrite)
40 memset_fl(fis, 0, sizeof(*fis));
42 if (op->count >= (1<<8) || lba + op->count >= (1<<28)) {
43 SET_FLATPTR(fis->sector_count2, op->count >> 8);
44 SET_FLATPTR(fis->lba_low2, lba >> 24);
45 SET_FLATPTR(fis->lba_mid2, lba >> 32);
46 SET_FLATPTR(fis->lba_high2, lba >> 40);
48 command = (iswrite ? ATA_CMD_WRITE_DMA_EXT
49 : ATA_CMD_READ_DMA_EXT);
51 command = (iswrite ? ATA_CMD_WRITE_DMA
54 SET_FLATPTR(fis->feature, 1); /* dma */
55 SET_FLATPTR(fis->command, command);
56 SET_FLATPTR(fis->sector_count, op->count);
57 SET_FLATPTR(fis->lba_low, lba);
58 SET_FLATPTR(fis->lba_mid, lba >> 8);
59 SET_FLATPTR(fis->lba_high, lba >> 16);
60 SET_FLATPTR(fis->device, ((lba >> 24) & 0xf) | ATA_CB_DH_LBA);
63 static void sata_prep_atapi(struct sata_cmd_fis *fis, u16 blocksize)
65 memset_fl(fis, 0, sizeof(*fis));
66 SET_FLATPTR(fis->command, ATA_CMD_PACKET);
67 SET_FLATPTR(fis->feature, 1); /* dma */
68 SET_FLATPTR(fis->lba_mid, blocksize);
69 SET_FLATPTR(fis->lba_high, blocksize >> 8);
72 // ahci register access helpers
73 static u32 ahci_ctrl_readl(struct ahci_ctrl_s *ctrl, u32 reg)
75 u32 addr = GET_GLOBALFLAT(ctrl->iobase) + reg;
76 return pci_readl(addr);
79 static void ahci_ctrl_writel(struct ahci_ctrl_s *ctrl, u32 reg, u32 val)
81 u32 addr = GET_GLOBALFLAT(ctrl->iobase) + reg;
82 pci_writel(addr, val);
85 static u32 ahci_port_to_ctrl(u32 pnr, u32 port_reg)
88 ctrl_reg += pnr * 0x80;
93 static u32 ahci_port_readl(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg)
95 u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
96 return ahci_ctrl_readl(ctrl, ctrl_reg);
99 static void ahci_port_writel(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg, u32 val)
101 u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
102 ahci_ctrl_writel(ctrl, ctrl_reg, val);
105 // submit ahci command + wait for result
106 static int ahci_command(struct ahci_port_s *port, int iswrite, int isatapi,
107 void *buffer, u32 bsize)
109 u32 val, status, success, flags, intbits, error;
110 struct ahci_ctrl_s *ctrl = GET_GLOBAL(port->ctrl);
111 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
112 struct ahci_fis_s *fis = GET_GLOBAL(port->fis);
113 struct ahci_list_s *list = GET_GLOBAL(port->list);
114 u32 pnr = GET_GLOBAL(port->pnr);
116 SET_FLATPTR(cmd->fis.reg, 0x27);
117 SET_FLATPTR(cmd->fis.pmp_type, (1 << 7)); /* cmd fis */
118 SET_FLATPTR(cmd->prdt[0].base, ((u32)buffer));
119 SET_FLATPTR(cmd->prdt[0].baseu, 0);
120 SET_FLATPTR(cmd->prdt[0].flags, bsize-1);
122 flags = ((1 << 16) | /* one prd entry */
123 (iswrite ? (1 << 6) : 0) |
124 (isatapi ? (1 << 5) : 0) |
125 (5 << 0)); /* fis length (dwords) */
126 SET_FLATPTR(list[0].flags, flags);
127 SET_FLATPTR(list[0].bytes, 0);
128 SET_FLATPTR(list[0].base, ((u32)(cmd)));
129 SET_FLATPTR(list[0].baseu, 0);
131 dprintf(2, "AHCI/%d: send cmd ...\n", pnr);
132 intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
134 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
135 ahci_port_writel(ctrl, pnr, PORT_SCR_ACT, 1);
136 ahci_port_writel(ctrl, pnr, PORT_CMD_ISSUE, 1);
140 intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
142 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
143 if (intbits & 0x02) {
144 status = GET_FLATPTR(fis->psfis[2]);
145 error = GET_FLATPTR(fis->psfis[3]);
148 if (intbits & 0x01) {
149 status = GET_FLATPTR(fis->rfis[2]);
150 error = GET_FLATPTR(fis->rfis[3]);
156 dprintf(2, "AHCI/%d: ... intbits 0x%x, status 0x%x ...\n",
157 pnr, intbits, status);
158 } while (status & ATA_CB_STAT_BSY);
160 success = (0x00 == (status & (ATA_CB_STAT_BSY | ATA_CB_STAT_DF |
162 ATA_CB_STAT_RDY == (status & (ATA_CB_STAT_RDY)));
164 dprintf(2, "AHCI/%d: ... finished, status 0x%x, OK\n", pnr,
167 dprintf(2, "AHCI/%d: ... finished, status 0x%x, ERROR 0x%x\n", pnr,
170 // non-queued error recovery (AHCI 1.3 section 6.2.2.1)
171 // Clears PxCMD.ST to 0 to reset the PxCI register
172 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
173 ahci_port_writel(ctrl, pnr, PORT_CMD, val & ~PORT_CMD_START);
175 // waits for PxCMD.CR to clear to 0
177 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
178 if ((val & PORT_CMD_LIST_ON) == 0)
183 // Clears any error bits in PxSERR to enable capturing new errors
184 val = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
185 ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, val);
187 // Clears status bits in PxIS as appropriate
188 val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
189 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
191 // If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to 1, issue
192 // a COMRESET to the device to put it in an idle state
193 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
194 if (val & (ATA_CB_STAT_BSY | ATA_CB_STAT_DRQ)) {
195 dprintf(2, "AHCI/%d: issue comreset\n", pnr);
196 val = ahci_port_readl(ctrl, pnr, PORT_SCR_CTL);
197 // set Device Detection Initialization (DET) to 1 for 1 ms for comreset
198 ahci_port_writel(ctrl, pnr, PORT_SCR_CTL, val | 1);
200 ahci_port_writel(ctrl, pnr, PORT_SCR_CTL, val);
203 // Sets PxCMD.ST to 1 to enable issuing new commands
204 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
205 ahci_port_writel(ctrl, pnr, PORT_CMD, val | PORT_CMD_START);
207 return success ? 0 : -1;
210 #define CDROM_CDB_SIZE 12
212 int ahci_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize)
217 struct ahci_port_s *port = container_of(
218 op->drive_g, struct ahci_port_s, drive);
219 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
223 sata_prep_atapi(&cmd->fis, blocksize);
224 for (i = 0; i < CDROM_CDB_SIZE; i++) {
225 SET_FLATPTR(cmd->atapi[i], atapi[i]);
227 rc = ahci_command(port, 0, 1, op->buf_fl,
228 op->count * blocksize);
230 return DISK_RET_EBADTRACK;
231 return DISK_RET_SUCCESS;
234 // read/write count blocks from a harddrive, op->buf_fl must be word aligned
236 ahci_disk_readwrite_aligned(struct disk_op_s *op, int iswrite)
238 struct ahci_port_s *port = container_of(
239 op->drive_g, struct ahci_port_s, drive);
240 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
243 sata_prep_readwrite(&cmd->fis, op, iswrite);
244 rc = ahci_command(port, iswrite, 0, op->buf_fl,
245 op->count * DISK_SECTOR_SIZE);
246 dprintf(2, "ahci disk %s, lba %6x, count %3x, buf %p, rc %d\n",
247 iswrite ? "write" : "read", (u32)op->lba, op->count, op->buf_fl, rc);
249 return DISK_RET_EBADTRACK;
250 return DISK_RET_SUCCESS;
253 // read/write count blocks from a harddrive.
255 ahci_disk_readwrite(struct disk_op_s *op, int iswrite)
257 // if caller's buffer is word aligned, use it directly
258 if (((u32) op->buf_fl & 1) == 0)
259 return ahci_disk_readwrite_aligned(op, iswrite);
261 // Use a word aligned buffer for AHCI I/O
263 struct disk_op_s localop = *op;
264 u8 *alignedbuf_fl = GET_GLOBAL(ahci_buf_fl);
265 u8 *position = op->buf_fl;
267 localop.buf_fl = alignedbuf_fl;
272 for (block = 0; block < op->count; block++) {
273 memcpy_fl (alignedbuf_fl, position, DISK_SECTOR_SIZE);
274 rc = ahci_disk_readwrite_aligned (&localop, 1);
277 position += DISK_SECTOR_SIZE;
282 for (block = 0; block < op->count; block++) {
283 rc = ahci_disk_readwrite_aligned (&localop, 0);
286 memcpy_fl (position, alignedbuf_fl, DISK_SECTOR_SIZE);
287 position += DISK_SECTOR_SIZE;
291 return DISK_RET_SUCCESS;
295 int process_ahci_op(struct disk_op_s *op)
297 struct ahci_port_s *port;
303 port = container_of(op->drive_g, struct ahci_port_s, drive);
304 atapi = GET_GLOBAL(port->atapi);
307 switch (op->command) {
312 return DISK_RET_EWRITEPROTECT;
314 /* FIXME: what should we do here? */
317 return DISK_RET_SUCCESS;
319 dprintf(1, "AHCI: unknown cdrom command %d\n", op->command);
321 return DISK_RET_EPARAM;
324 switch (op->command) {
326 return ahci_disk_readwrite(op, 0);
328 return ahci_disk_readwrite(op, 1);
330 /* FIXME: what should we do here? */
334 return DISK_RET_SUCCESS;
336 dprintf(1, "AHCI: unknown disk command %d\n", op->command);
338 return DISK_RET_EPARAM;
343 /****************************************************************
344 * everything below is pure 32bit code
345 ****************************************************************/
348 ahci_port_reset(struct ahci_ctrl_s *ctrl, u32 pnr)
352 /* disable FIS + CMD */
353 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
354 while (val & (PORT_CMD_FIS_RX | PORT_CMD_START |
355 PORT_CMD_FIS_ON | PORT_CMD_LIST_ON) &&
356 count < AHCI_MAX_RETRIES) {
357 val &= ~(PORT_CMD_FIS_RX | PORT_CMD_START);
358 ahci_port_writel(ctrl, pnr, PORT_CMD, val);
360 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
365 val = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
367 ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, val);
369 /* disable + clear IRQs */
370 ahci_port_writel(ctrl, pnr, PORT_IRQ_MASK, val);
371 val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
373 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
377 ahci_port_probe(struct ahci_ctrl_s *ctrl, u32 pnr)
381 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
382 while (val & ATA_CB_STAT_BSY) {
384 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
386 if (count >= AHCI_MAX_RETRIES)
390 val = ahci_port_readl(ctrl, pnr, PORT_SCR_STAT);
391 if ((val & 0x07) != 0x03)
398 static struct ahci_port_s*
399 ahci_port_init(struct ahci_ctrl_s *ctrl, u32 pnr)
401 struct ahci_port_s *port = malloc_fseg(sizeof(*port));
402 char model[MAXMODEL+1];
413 port->list = memalign_low(1024, 1024);
414 port->fis = memalign_low(256, 256);
415 port->cmd = memalign_low(256, 256);
416 if (port->list == NULL || port->fis == NULL || port->cmd == NULL) {
420 memset(port->list, 0, 1024);
421 memset(port->fis, 0, 256);
422 memset(port->cmd, 0, 256);
424 ahci_port_writel(ctrl, pnr, PORT_LST_ADDR, (u32)port->list);
425 ahci_port_writel(ctrl, pnr, PORT_FIS_ADDR, (u32)port->fis);
426 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
427 val |= PORT_CMD_FIS_RX;
428 ahci_port_writel(ctrl, pnr, PORT_CMD, val);
429 val |= PORT_CMD_START;
430 ahci_port_writel(ctrl, pnr, PORT_CMD, val);
432 sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_PACKET_DEVICE);
433 rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
438 sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_DEVICE);
439 rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
444 port->drive.type = DTYPE_AHCI;
445 port->drive.cntl_id = pnr;
446 port->drive.removable = (buffer[0] & 0x80) ? 1 : 0;
450 port->drive.blksize = DISK_SECTOR_SIZE;
451 port->drive.pchs.cylinders = buffer[1];
452 port->drive.pchs.heads = buffer[3];
453 port->drive.pchs.spt = buffer[6];
456 if (buffer[83] & (1 << 10)) // word 83 - lba48 support
457 sectors = *(u64*)&buffer[100]; // word 100-103
459 sectors = *(u32*)&buffer[60]; // word 60 and word 61
460 port->drive.sectors = sectors;
461 u64 adjsize = sectors >> 11;
462 char adjprefix = 'M';
463 if (adjsize >= (1 << 16)) {
467 char *desc = znprintf(MAXDESCSIZE
468 , "AHCI/%d: %s ATA-%d Hard-Disk (%u %ciBytes)"
470 , ata_extract_model(model, MAXMODEL, buffer)
471 , ata_extract_version(buffer)
472 , (u32)adjsize, adjprefix);
473 dprintf(1, "%s\n", desc);
475 // Register with bcv system.
476 boot_add_hd(&port->drive, desc, -1);
478 // found cdrom (atapi)
479 port->drive.blksize = CDROM_SECTOR_SIZE;
480 port->drive.sectors = (u64)-1;
481 u8 iscd = ((buffer[0] >> 8) & 0x1f) == 0x05;
482 char *desc = znprintf(MAXDESCSIZE
483 , "DVD/CD [AHCI/%d: %s ATAPI-%d %s]"
485 , ata_extract_model(model, MAXMODEL, buffer)
486 , ata_extract_version(buffer)
487 , (iscd ? "DVD/CD" : "Device"));
488 dprintf(1, "%s\n", desc);
492 boot_add_cd(&port->drive, desc, -1);
498 dprintf(1, "AHCI/%d: init failure, reset\n", port->pnr);
499 ahci_port_reset(ctrl, pnr);
503 // Detect any drives attached to a given controller.
505 ahci_detect(void *data)
507 struct ahci_ctrl_s *ctrl = data;
508 struct ahci_port_s *port;
512 max = ctrl->caps & 0x1f;
513 for (pnr = 0; pnr <= max; pnr++) {
514 if (!(ctrl->ports & (1 << pnr)))
516 dprintf(2, "AHCI/%d: probing\n", pnr);
517 ahci_port_reset(ctrl, pnr);
518 rc = ahci_port_probe(ctrl, pnr);
519 dprintf(1, "AHCI/%d: link %s\n", pnr, rc == 0 ? "up" : "down");
522 port = ahci_port_init(ctrl, pnr);
526 // Initialize an ata controller and detect its drives.
528 ahci_init_controller(int bdf)
530 struct ahci_ctrl_s *ctrl = malloc_fseg(sizeof(*ctrl));
538 ahci_buf_fl = malloc_low(DISK_SECTOR_SIZE);
545 ctrl->iobase = pci_config_readl(bdf, PCI_BASE_ADDRESS_5);
546 ctrl->irq = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
547 dprintf(1, "AHCI controller at %02x.%x, iobase %x, irq %d\n",
548 bdf >> 3, bdf & 7, ctrl->iobase, ctrl->irq);
550 pci_config_maskw(bdf, PCI_COMMAND, 0,
551 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
553 val = ahci_ctrl_readl(ctrl, HOST_CTL);
554 ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN);
556 ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP);
557 ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL);
558 dprintf(2, "AHCI: cap 0x%x, ports_impl 0x%x\n",
559 ctrl->caps, ctrl->ports);
561 run_thread(ahci_detect, ctrl);
564 // Locate and init ahci controllers.
568 // Scan PCI bus for ATA adapters
569 struct pci_device *pci;
571 if (pci->class != PCI_CLASS_STORAGE_SATA)
573 if (pci->prog_if != 1 /* AHCI rev 1 */)
575 ahci_init_controller(pci->bdf);
586 dprintf(3, "init ahci\n");