SRC16=$(SRCBOTH) system.c disk.c font.c
SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \
acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \
- lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c \
+ lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c \
pci_region.c biostables.c xen.c
SRC32SEG=util.c output.c pci.c pcibios.c apm.c stacks.c
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "pci_regs.h" // PCI_INTERRUPT_LINE
#include "paravirt.h"
-#include "dev-i440fx.h" // piix4_fadt_init
/****************************************************/
/* ACPI tables init */
h->checksum -= checksum(h, len);
}
+#define PIIX4_ACPI_ENABLE 0xf1
+#define PIIX4_ACPI_DISABLE 0xf0
+#define PIIX4_GPE0_BLK 0xafe0
+#define PIIX4_GPE0_BLK_LEN 4
+
+static void piix4_fadt_init(u16 bdf, void *arg)
+{
+ struct fadt_descriptor_rev1 *fadt = arg;
+ fadt->acpi_enable = PIIX4_ACPI_ENABLE;
+ fadt->acpi_disable = PIIX4_ACPI_DISABLE;
+ fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
+ fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;
+}
+
static const struct pci_device_id fadt_init_tbl[] = {
/* PIIX4 Power Management device (for ACPI) */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
+++ /dev/null
-// initialization function which are specific to i440fx chipset
-//
-// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
-// Copyright (C) 2006 Fabrice Bellard
-//
-// Copyright (C) 2010 Isaku Yamahata <yamahata at valinux co jp>
-// Split out from pciinit.c
-//
-// This file may be distributed under the terms of the GNU LGPLv3 license.
-//
-
-#include "config.h" // CONFIG_DEBUG_LEVEL
-#include "util.h" // dprintf
-#include "ioport.h" // outb
-#include "pci.h" // pci_config_writeb
-#include "pci_ids.h"
-#include "pci_regs.h" // PCI_INTERRUPT_LINE
-#include "acpi.h"
-#include "dev-i440fx.h"
-
-#define I440FX_PAM0 0x59
-
-void i440fx_bios_make_writable(u16 bdf, void *arg)
-{
- make_bios_writable_intel(bdf, I440FX_PAM0);
-}
-
-void i440fx_bios_make_readonly(u16 bdf, void *arg)
-{
- make_bios_readonly_intel(bdf, I440FX_PAM0);
-}
-
-/* PIIX3/PIIX4 PCI to ISA bridge */
-void piix_isa_bridge_init(u16 bdf, void *arg)
-{
- int i, irq;
- u8 elcr[2];
-
- elcr[0] = 0x00;
- elcr[1] = 0x00;
- for (i = 0; i < 4; i++) {
- irq = pci_irqs[i];
- /* set to trigger level */
- elcr[irq >> 3] |= (1 << (irq & 7));
- /* activate irq remapping in PIIX */
- pci_config_writeb(bdf, 0x60 + i, irq);
- }
- outb(elcr[0], 0x4d0);
- outb(elcr[1], 0x4d1);
- dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
-}
-
-/* PIIX3/PIIX4 IDE */
-void piix_ide_init(u16 bdf, void *arg)
-{
- pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
- pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
- pci_bios_allocate_regions(bdf, NULL);
-}
-
-/* PIIX4 Power Management device (for ACPI) */
-void piix4_pm_init(u16 bdf, void *arg)
-{
- // acpi sci is hardwired to 9
- pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
-
- pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
- pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
- pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
- pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
-}
-
-#define PIIX4_ACPI_ENABLE 0xf1
-#define PIIX4_ACPI_DISABLE 0xf0
-#define PIIX4_GPE0_BLK 0xafe0
-#define PIIX4_GPE0_BLK_LEN 4
-
-void piix4_fadt_init(u16 bdf, void *arg)
-{
- struct fadt_descriptor_rev1 *fadt = arg;
- fadt->acpi_enable = PIIX4_ACPI_ENABLE;
- fadt->acpi_disable = PIIX4_ACPI_DISABLE;
- fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
- fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;
-}
-
-#define I440FX_SMRAM 0x72
-#define PIIX_DEVACTB 0x58
-#define PIIX_APMC_EN (1 << 25)
-
-// This code is hardcoded for PIIX4 Power Management device.
-void piix4_apmc_smm_init(u16 bdf, void *arg)
-{
- int i440_bdf = pci_find_device(PCI_VENDOR_ID_INTEL
- , PCI_DEVICE_ID_INTEL_82441);
- if (i440_bdf < 0)
- return;
-
- /* check if SMM init is already done */
- u32 value = pci_config_readl(bdf, PIIX_DEVACTB);
- if (value & PIIX_APMC_EN)
- return;
-
- /* enable the SMM memory window */
- pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x48);
-
- smm_save_and_copy();
-
- /* enable SMI generation when writing to the APMC register */
- pci_config_writel(bdf, PIIX_DEVACTB, value | PIIX_APMC_EN);
-
- smm_relocate_and_restore();
-
- /* close the SMM memory window and enable normal SMM */
- pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x08);
-}
+++ /dev/null
-#ifndef __I440FX_H
-#define __I440FX_H
-
-#include "types.h" // u16
-
-void i440fx_bios_make_writable(u16 bdf, void *arg);
-void i440fx_bios_make_readonly(u16 bdf, void *arg);
-void piix_isa_bridge_init(u16 bdf, void *arg);
-void piix_ide_init(u16 bdf, void *arg);
-void piix4_pm_init(u16 bdf, void *arg);
-void piix4_fadt_init(u16 bdf, void *arg);
-void piix4_apmc_smm_init(u16 bdf, void *arg);
-
-#endif // __I440FX_H
#include "biosvar.h" // GET_EBDA
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "pci_regs.h" // PCI_COMMAND
-#include "dev-i440fx.h"
#include "xen.h" // usingXen
#define PCI_ROM_SLOT 6
return is_64bit;
}
-void pci_bios_allocate_regions(u16 bdf, void *arg)
+static void pci_bios_allocate_regions(u16 bdf, void *arg)
{
int i;
for (i = 0; i < PCI_NUM_REGIONS; i++) {
return (irq_num + slot_addend) & 3;
}
+/* PIIX3/PIIX4 PCI to ISA bridge */
+static void piix_isa_bridge_init(u16 bdf, void *arg)
+{
+ int i, irq;
+ u8 elcr[2];
+
+ elcr[0] = 0x00;
+ elcr[1] = 0x00;
+ for (i = 0; i < 4; i++) {
+ irq = pci_irqs[i];
+ /* set to trigger level */
+ elcr[irq >> 3] |= (1 << (irq & 7));
+ /* activate irq remapping in PIIX */
+ pci_config_writeb(bdf, 0x60 + i, irq);
+ }
+ outb(elcr[0], 0x4d0);
+ outb(elcr[1], 0x4d1);
+ dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
+}
+
static const struct pci_device_id pci_isa_bridge_tbl[] = {
/* PIIX3/PIIX4 PCI to ISA bridge */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
}
+/* PIIX3/PIIX4 IDE */
+static void piix_ide_init(u16 bdf, void *arg)
+{
+ pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
+ pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
+ pci_bios_allocate_regions(bdf, NULL);
+}
+
static void pic_ibm_init(u16 bdf, void *arg)
{
/* PIC, IBM, MPIC & MPIC2 */
PCI_DEVICE_END,
};
+/* PIIX4 Power Management device (for ACPI) */
+static void piix4_pm_init(u16 bdf, void *arg)
+{
+ // acpi sci is hardwired to 9
+ pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
+
+ pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
+ pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
+ pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
+ pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
+}
+
static const struct pci_device_id pci_device_tbl[] = {
/* PIIX4 Power Management device (for ACPI) */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
#include "pci.h" // pci_config_writeb
#include "config.h" // CONFIG_*
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
-#include "dev-i440fx.h"
#include "xen.h" // usingXen
// On the emulators, the bios at 0xf0000 is also at 0xffff0000
#define BIOS_SRC_OFFSET 0xfff00000
+#define I440FX_PAM0 0x59
+
// Enable shadowing and copy bios.
static void
__make_bios_writable_intel(u16 bdf, u32 pam0)
, code32flat_end - code32flat_start);
}
-void
+static void
make_bios_writable_intel(u16 bdf, u32 pam0)
{
int reg = pci_config_readb(bdf, pam0);
__make_bios_writable_intel(bdf, pam0);
}
-void
+static void
make_bios_readonly_intel(u16 bdf, u32 pam0)
{
// Flush any pending writes before locking memory.
pci_config_writeb(bdf, pam0, 0x10);
}
+static void i440fx_bios_make_writable(u16 bdf, void *arg)
+{
+ make_bios_writable_intel(bdf, I440FX_PAM0);
+}
+
+static void i440fx_bios_make_readonly(u16 bdf, void *arg)
+{
+ make_bios_readonly_intel(bdf, I440FX_PAM0);
+}
+
static const struct pci_device_id dram_controller_make_writable_tbl[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
i440fx_bios_make_writable),
PCI_DEVICE_END
};
+static const struct pci_device_id dram_controller_make_readonly_tbl[] = {
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
+ i440fx_bios_make_readonly),
+ PCI_DEVICE_END
+};
+
// Make the 0xc0000-0x100000 area read/writable.
void
make_bios_writable(void)
}
}
-static const struct pci_device_id dram_controller_make_readonly_tbl[] = {
- PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
- i440fx_bios_make_readonly),
- PCI_DEVICE_END
-};
-
// Make the BIOS code segment area (0xf0000) read-only.
void
make_bios_readonly(void)
#include "config.h" // CONFIG_*
#include "ioport.h" // outb
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
-#include "dev-i440fx.h"
ASM32FLAT(
".global smm_relocation_start\n"
extern u8 smm_relocation_start, smm_relocation_end;
extern u8 smm_code_start, smm_code_end;
-void
+static void
smm_save_and_copy(void)
{
/* save original memory content */
&smm_relocation_end - &smm_relocation_start);
}
-void
+static void
smm_relocate_and_restore(void)
{
/* init APM status port */
wbinvd();
}
+#define I440FX_SMRAM 0x72
+#define PIIX_DEVACTB 0x58
+#define PIIX_APMC_EN (1 << 25)
+
+// This code is hardcoded for PIIX4 Power Management device.
+static void piix4_apmc_smm_init(u16 bdf, void *arg)
+{
+ int i440_bdf = pci_find_device(PCI_VENDOR_ID_INTEL
+ , PCI_DEVICE_ID_INTEL_82441);
+ if (i440_bdf < 0)
+ return;
+
+ /* check if SMM init is already done */
+ u32 value = pci_config_readl(bdf, PIIX_DEVACTB);
+ if (value & PIIX_APMC_EN)
+ return;
+
+ /* enable the SMM memory window */
+ pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x48);
+
+ smm_save_and_copy();
+
+ /* enable SMI generation when writing to the APMC register */
+ pci_config_writel(bdf, PIIX_DEVACTB, value | PIIX_APMC_EN);
+
+ smm_relocate_and_restore();
+
+ /* close the SMM memory window and enable normal SMM */
+ pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x08);
+}
+
static const struct pci_device_id smm_init_tbl[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
piix4_apmc_smm_init),
// shadow.c
void make_bios_writable(void);
void make_bios_readonly(void);
-void make_bios_writable_intel(u16 bdf, u32 pam0);
-void make_bios_readonly_intel(u16 bdf, u32 pam0);
void qemu_prep_reset(void);
-// smm.c
-void smm_save_and_copy(void);
-void smm_relocate_and_restore(void);
-
// pci_region.c
// region allocator. pci region allocates the requested region
// sequentially with overflow check.
// pciinit.c
extern const u8 pci_irqs[4];
-void pci_bios_allocate_regions(u16 bdf, void *arg);
void pci_setup(void);
// smm.c
projects / seabios.git / commitdiff