1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "dev-i440fx.h"
14 #include "xen.h" // usingXen
16 #define PCI_ROM_SLOT 6
17 #define PCI_NUM_REGIONS 7
19 static void pci_bios_init_device_in_bus(int bus);
21 static struct pci_region pci_bios_io_region;
22 static struct pci_region pci_bios_mem_region;
23 static struct pci_region pci_bios_prefmem_region;
25 /* host irqs corresponding to PCI irqs A-D */
26 const u8 pci_irqs[4] = {
30 static u32 pci_bar(u16 bdf, int region_num)
32 if (region_num != PCI_ROM_SLOT) {
33 return PCI_BASE_ADDRESS_0 + region_num * 4;
36 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
37 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
38 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
39 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
42 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
46 ofs = pci_bar(bdf, region_num);
48 pci_config_writel(bdf, ofs, addr);
49 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
57 static int pci_bios_allocate_region(u16 bdf, int region_num)
60 u32 ofs = pci_bar(bdf, region_num);
62 u32 old = pci_config_readl(bdf, ofs);
64 if (region_num == PCI_ROM_SLOT) {
65 mask = PCI_ROM_ADDRESS_MASK;
66 pci_config_writel(bdf, ofs, mask);
68 if (old & PCI_BASE_ADDRESS_SPACE_IO)
69 mask = PCI_BASE_ADDRESS_IO_MASK;
71 mask = PCI_BASE_ADDRESS_MEM_MASK;
72 pci_config_writel(bdf, ofs, ~0);
74 u32 val = pci_config_readl(bdf, ofs);
75 pci_config_writel(bdf, ofs, old);
77 u32 size = (~(val & mask)) + 1;
81 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
82 r = &pci_bios_io_region;
85 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
86 /* keep behaviour on bus = 0 */
87 pci_bdf_to_bus(bdf) != 0 &&
88 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
89 pci_region_addr(&pci_bios_prefmem_region) != 0) {
90 r = &pci_bios_prefmem_region;
92 msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x";
94 r = &pci_bios_mem_region;
96 msg = "increase BUILD_PCIMEM_SIZE and recompile.";
98 u32 addr = pci_region_alloc(r, size);
100 pci_set_io_region_addr(bdf, region_num, addr);
104 "%s region of (bdf 0x%x bar %d) can't be mapped. "
106 type, bdf, region_num, msg, pci_region_size(r));
110 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
111 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
112 if (is_64bit && size > 0) {
113 pci_config_writel(bdf, ofs + 4, 0);
118 void pci_bios_allocate_regions(u16 bdf, void *arg)
121 for (i = 0; i < PCI_NUM_REGIONS; i++) {
122 int is_64bit = pci_bios_allocate_region(bdf, i);
129 /* return the global irq number corresponding to a given device irq
130 pin. We could also use the bus number to have a more precise
132 static int pci_slot_get_pirq(u16 bdf, int irq_num)
134 int slot_addend = pci_bdf_to_dev(bdf) - 1;
135 return (irq_num + slot_addend) & 3;
138 static const struct pci_device_id pci_isa_bridge_tbl[] = {
139 /* PIIX3/PIIX4 PCI to ISA bridge */
140 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
141 piix_isa_bridge_init),
142 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
143 piix_isa_bridge_init),
148 #define PCI_IO_ALIGN 4096
149 #define PCI_IO_SHIFT 8
150 #define PCI_MEMORY_ALIGN (1UL << 20)
151 #define PCI_MEMORY_SHIFT 16
152 #define PCI_PREF_MEMORY_ALIGN (1UL << 20)
153 #define PCI_PREF_MEMORY_SHIFT 16
155 static void pci_bios_init_device_bridge(u16 bdf, void *arg)
157 pci_bios_allocate_region(bdf, 0);
158 pci_bios_allocate_region(bdf, 1);
159 pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
161 u32 io_old = pci_region_addr(&pci_bios_io_region);
162 u32 mem_old = pci_region_addr(&pci_bios_mem_region);
163 u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region);
165 /* IO BASE is assumed to be 16 bit */
166 if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) {
167 pci_region_disable(&pci_bios_io_region);
169 if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) {
170 pci_region_disable(&pci_bios_mem_region);
172 if (pci_region_align(&pci_bios_prefmem_region,
173 PCI_PREF_MEMORY_ALIGN) == 0) {
174 pci_region_disable(&pci_bios_prefmem_region);
177 u32 io_base = pci_region_addr(&pci_bios_io_region);
178 u32 mem_base = pci_region_addr(&pci_bios_mem_region);
179 u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region);
181 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
183 pci_bios_init_device_in_bus(secbus);
186 u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN);
188 pci_region_revert(&pci_bios_io_region, io_old);
192 pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT);
193 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
194 pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
195 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
197 u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN);
199 pci_region_revert(&pci_bios_mem_region, mem_old);
200 mem_base = 0xffffffff;
203 pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
204 pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
206 u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region,
207 PCI_PREF_MEMORY_ALIGN);
208 if (prefmem_end == 0) {
209 pci_region_revert(&pci_bios_prefmem_region, prefmem_old);
210 prefmem_base = 0xffffffff;
213 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE,
214 prefmem_base >> PCI_PREF_MEMORY_SHIFT);
215 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT,
216 (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
217 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
218 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
220 dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end);
221 dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end);
222 dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end);
224 u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
225 cmd &= ~PCI_COMMAND_IO;
226 if (io_end > io_base) {
227 cmd |= PCI_COMMAND_IO;
229 cmd &= ~PCI_COMMAND_MEMORY;
230 if (mem_end > mem_base || prefmem_end > prefmem_base) {
231 cmd |= PCI_COMMAND_MEMORY;
233 cmd |= PCI_COMMAND_MASTER;
234 pci_config_writew(bdf, PCI_COMMAND, cmd);
236 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
239 static void storage_ide_init(u16 bdf, void *arg)
241 /* IDE: we map it as in ISA mode */
242 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
243 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
244 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
245 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
248 static void pic_ibm_init(u16 bdf, void *arg)
250 /* PIC, IBM, MPIC & MPIC2 */
251 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
254 static void apple_macio_init(u16 bdf, void *arg)
257 pci_set_io_region_addr(bdf, 0, 0x80800000);
260 static const struct pci_device_id pci_class_tbl[] = {
262 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
263 PCI_CLASS_STORAGE_IDE, piix_ide_init),
264 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
265 PCI_CLASS_STORAGE_IDE, piix_ide_init),
266 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
269 /* PIC, IBM, MIPC & MPIC2 */
270 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
272 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
276 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
277 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
280 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
281 pci_bios_init_device_bridge),
284 PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
289 static const struct pci_device_id pci_device_tbl[] = {
290 /* PIIX4 Power Management device (for ACPI) */
291 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
297 static void pci_bios_init_device(u16 bdf)
299 int pin, pic_irq, vendor_id, device_id;
301 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
302 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
303 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
304 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
305 pci_init_device(pci_class_tbl, bdf, NULL);
307 /* enable memory mappings */
308 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
310 /* map the interrupt */
311 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
313 pin = pci_slot_get_pirq(bdf, pin - 1);
314 pic_irq = pci_irqs[pin];
315 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
318 pci_init_device(pci_device_tbl, bdf, NULL);
321 static void pci_bios_init_device_in_bus(int bus)
324 foreachpci_in_bus(bdf, max, bus) {
325 pci_bios_init_device(bdf);
330 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
335 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
337 /* prevent accidental access to unintended devices */
338 foreachpci_in_bus(bdf, max, bus) {
339 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
340 if (class == PCI_CLASS_BRIDGE_PCI) {
341 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
342 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
346 foreachpci_in_bus(bdf, max, bus) {
347 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
348 if (class != PCI_CLASS_BRIDGE_PCI) {
351 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
353 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
355 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
356 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
358 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
361 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
363 if (*pci_bus != secbus) {
364 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
367 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
369 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
372 /* set to max for access to all subordinate buses.
373 later set it to accurate value */
374 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
375 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
377 pci_bios_init_bus_rec(secbus, pci_bus);
379 if (subbus != *pci_bus) {
380 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
384 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
386 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
391 pci_bios_init_bus(void)
394 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
400 if (CONFIG_COREBOOT || usingXen())
401 // Already done by coreboot or Xen.
404 dprintf(3, "pci setup\n");
406 pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1);
407 pci_region_init(&pci_bios_mem_region,
408 BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1);
409 pci_region_init(&pci_bios_prefmem_region,
410 BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1);
415 foreachpci(bdf, max) {
416 pci_init_device(pci_isa_bridge_tbl, bdf, NULL);
418 pci_bios_init_device_in_bus(0 /* host bus */);