1 // Support for generating ACPI tables (on emulators)
3 // Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "acpi.h" // struct rsdp_descriptor
9 #include "util.h" // memcpy
10 #include "pci.h" // pci_find_device
11 #include "biosvar.h" // GET_EBDA
12 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
16 /****************************************************/
17 /* ACPI tables init */
19 /* Table structure from Linux kernel (the ACPI tables are under the
22 struct acpi_table_header /* ACPI common table header */
28 * ACPI 1.0 Root System Description Table (RSDT)
30 #define RSDT_SIGNATURE 0x54445352 // RSDT
31 struct rsdt_descriptor_rev1
33 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
34 u32 table_offset_entry[0]; /* Array of pointers to other */
39 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
41 #define FACS_SIGNATURE 0x53434146 // FACS
42 struct facs_descriptor_rev1
44 u32 signature; /* ACPI Signature */
45 u32 length; /* Length of structure, in bytes */
46 u32 hardware_signature; /* Hardware configuration signature */
47 u32 firmware_waking_vector; /* ACPI OS waking vector */
48 u32 global_lock; /* Global Lock */
49 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
50 u32 reserved1 : 31; /* Must be 0 */
51 u8 resverved3 [40]; /* Reserved - must be zero */
56 * MADT values and structures
59 /* Values for MADT PCATCompat */
62 #define MULTIPLE_APIC 1
67 #define APIC_SIGNATURE 0x43495041 // APIC
68 struct multiple_apic_table
70 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
71 u32 local_apic_address; /* Physical address of local APIC */
73 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
81 /* Values for Type in APIC sub-headers */
83 #define APIC_PROCESSOR 0
85 #define APIC_XRUPT_OVERRIDE 2
87 #define APIC_LOCAL_NMI 4
88 #define APIC_ADDRESS_OVERRIDE 5
89 #define APIC_IO_SAPIC 6
90 #define APIC_LOCAL_SAPIC 7
91 #define APIC_XRUPT_SOURCE 8
92 #define APIC_RESERVED 9 /* 9 and greater are reserved */
95 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
97 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
101 /* Sub-structures for MADT */
103 struct madt_processor_apic
106 u8 processor_id; /* ACPI processor id */
107 u8 local_apic_id; /* Processor's local APIC id */
109 u32 processor_enabled: 1; /* Processor is usable if set */
110 u32 reserved2 : 31; /* Reserved, must be zero */
119 u8 io_apic_id; /* I/O APIC ID */
120 u8 reserved; /* Reserved - must be zero */
121 u32 address; /* APIC physical address */
122 u32 interrupt; /* Global system interrupt where INTI
127 #define PCI_ISA_IRQ_MASK 0x0e20
129 struct madt_intsrcovr {
138 * ACPI 2.0 Generic Address Space definition.
140 struct acpi_20_generic_address {
142 u8 register_bit_width;
143 u8 register_bit_offset;
149 * HPET Description Table
151 struct acpi_20_hpet {
152 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
154 struct acpi_20_generic_address addr;
159 #define ACPI_HPET_ADDRESS 0xFED00000UL
162 * SRAT (NUMA topology description) table
165 #define SRAT_PROCESSOR 0
166 #define SRAT_MEMORY 1
168 struct system_resource_affinity_table
170 ACPI_TABLE_HEADER_DEF
175 struct srat_processor_affinity
186 struct srat_memory_affinity
191 u32 base_addr_low,base_addr_high;
192 u32 length_low,length_high;
198 #include "acpi-dsdt.hex"
201 build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
204 h->length = cpu_to_le32(len);
206 memcpy(h->oem_id, CONFIG_APPNAME6, 6);
207 memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
208 memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
209 memcpy(h->oem_table_id + 4, (void*)&sig, 4);
210 h->oem_revision = cpu_to_le32(1);
211 h->asl_compiler_revision = cpu_to_le32(1);
212 h->checksum -= checksum(h, len);
218 struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
219 struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
220 void *dsdt = malloc_high(sizeof(AmlCode));
222 if (!fadt || !facs || !dsdt) {
228 memset(facs, 0, sizeof(*facs));
229 facs->signature = FACS_SIGNATURE;
230 facs->length = cpu_to_le32(sizeof(*facs));
233 memcpy(dsdt, AmlCode, sizeof(AmlCode));
236 memset(fadt, 0, sizeof(*fadt));
237 fadt->firmware_ctrl = cpu_to_le32((u32)facs);
238 fadt->dsdt = cpu_to_le32((u32)dsdt);
241 int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
242 fadt->sci_int = cpu_to_le16(pm_sci_int);
243 fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
244 fadt->acpi_enable = 0xf1;
245 fadt->acpi_disable = 0xf0;
246 fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
247 fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
248 fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
249 fadt->pm1_evt_len = 4;
250 fadt->pm1_cnt_len = 2;
251 fadt->pm_tmr_len = 4;
252 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
253 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
254 fadt->gpe0_blk = cpu_to_le32(0xafe0);
255 fadt->gpe0_blk_len = 4;
256 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
257 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
259 build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
267 int madt_size = (sizeof(struct multiple_apic_table)
268 + sizeof(struct madt_processor_apic) * MaxCountCPUs
269 + sizeof(struct madt_io_apic)
270 + sizeof(struct madt_intsrcovr) * 16);
271 struct multiple_apic_table *madt = malloc_high(madt_size);
276 memset(madt, 0, madt_size);
277 madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
278 madt->flags = cpu_to_le32(1);
279 struct madt_processor_apic *apic = (void*)&madt[1];
281 for (i=0; i<MaxCountCPUs; i++) {
282 apic->type = APIC_PROCESSOR;
283 apic->length = sizeof(*apic);
284 apic->processor_id = i;
285 apic->local_apic_id = i;
287 apic->flags = cpu_to_le32(1);
289 apic->flags = cpu_to_le32(0);
292 struct madt_io_apic *io_apic = (void*)apic;
293 io_apic->type = APIC_IO;
294 io_apic->length = sizeof(*io_apic);
295 io_apic->io_apic_id = CountCPUs;
296 io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
297 io_apic->interrupt = cpu_to_le32(0);
299 struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
300 if (qemu_cfg_irq0_override()) {
301 memset(intsrcovr, 0, sizeof(*intsrcovr));
302 intsrcovr->type = APIC_XRUPT_OVERRIDE;
303 intsrcovr->length = sizeof(*intsrcovr);
304 intsrcovr->source = 0;
306 intsrcovr->flags = 0; /* conforms to bus specifications */
309 for (i = 1; i < 16; i++) {
310 if (!(PCI_ISA_IRQ_MASK & (1 << i)))
311 /* No need for a INT source override structure. */
313 memset(intsrcovr, 0, sizeof(*intsrcovr));
314 intsrcovr->type = APIC_XRUPT_OVERRIDE;
315 intsrcovr->length = sizeof(*intsrcovr);
316 intsrcovr->source = i;
318 intsrcovr->flags = 0xd; /* active high, level triggered */
322 build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt, 1);
326 #define SSDT_SIGNATURE 0x54445353 // SSDT
330 int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
331 // calculate the length of processor block and scope block
332 // excluding PkgLength
333 int cpu_length = 13 * acpi_cpus + 4;
335 int length = sizeof(struct acpi_table_header) + 3 + cpu_length;
336 u8 *ssdt = malloc_high(length);
343 ssdt_ptr[9] = 0; // checksum;
344 ssdt_ptr += sizeof(struct acpi_table_header);
346 // build processor scope header
347 *(ssdt_ptr++) = 0x10; // ScopeOp
348 if (cpu_length <= 0x3e) {
349 /* Handle 1-4 CPUs with one byte encoding */
350 *(ssdt_ptr++) = cpu_length + 1;
352 /* Handle 5-314 CPUs with two byte encoding */
353 *(ssdt_ptr++) = 0x40 | ((cpu_length + 2) & 0xf);
354 *(ssdt_ptr++) = (cpu_length + 2) >> 4;
356 *(ssdt_ptr++) = '_'; // Name
361 // build object for each processor
363 for (i=0; i<acpi_cpus; i++) {
364 *(ssdt_ptr++) = 0x5B; // ProcessorOp
365 *(ssdt_ptr++) = 0x83;
366 *(ssdt_ptr++) = 0x0B; // Length
367 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
370 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
373 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
375 *(ssdt_ptr++) = 0x10; // Processor block address
376 *(ssdt_ptr++) = 0xb0;
379 *(ssdt_ptr++) = 6; // Processor block length
382 build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
387 #define HPET_SIGNATURE 0x54455048 //HPET
391 struct acpi_20_hpet *hpet = malloc_high(sizeof(*hpet));
397 memset(hpet, 0, sizeof(*hpet));
398 /* Note timer_block_id value must be kept in sync with value advertised by
401 hpet->timer_block_id = cpu_to_le32(0x8086a201);
402 hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
403 build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
409 acpi_build_srat_memory(struct srat_memory_affinity *numamem,
410 u64 base, u64 len, int node, int enabled)
412 numamem->type = SRAT_MEMORY;
413 numamem->length = sizeof(*numamem);
414 memset (numamem->proximity, 0 ,4);
415 numamem->proximity[0] = node;
416 numamem->flags = cpu_to_le32(!!enabled);
417 numamem->base_addr_low = base & 0xFFFFFFFF;
418 numamem->base_addr_high = base >> 32;
419 numamem->length_low = len & 0xFFFFFFFF;
420 numamem->length_high = len >> 32;
423 #define SRAT_SIGNATURE 0x54415253 //HPET
427 int nb_numa_nodes = qemu_cfg_get_numa_nodes();
429 if (nb_numa_nodes == 0)
432 u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes));
438 qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes);
440 struct system_resource_affinity_table *srat;
441 int srat_size = sizeof(*srat) +
442 sizeof(struct srat_processor_affinity) * MaxCountCPUs +
443 sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
445 srat = malloc_high(srat_size);
452 memset(srat, 0, srat_size);
454 struct srat_processor_affinity *core = (void*)(srat + 1);
458 for (i = 0; i < MaxCountCPUs; ++i) {
459 core->type = SRAT_PROCESSOR;
460 core->length = sizeof(*core);
461 core->local_apic_id = i;
462 curnode = *numadata++;
463 core->proximity_lo = curnode;
464 memset(core->proximity_hi, 0, 3);
465 core->local_sapic_eid = 0;
467 core->flags = cpu_to_le32(1);
474 /* the memory map is a bit tricky, it contains at least one hole
475 * from 640k-1M and possibly another one from 3.5G-4G.
477 struct srat_memory_affinity *numamem = (void*)core;
479 u64 mem_len, mem_base, next_base = 0;
481 acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
482 next_base = 1024 * 1024;
485 for (i = 1; i < nb_numa_nodes + 1; ++i) {
486 mem_base = next_base;
487 mem_len = *numadata++;
489 mem_len -= 1024 * 1024;
490 next_base = mem_base + mem_len;
492 /* Cut out the PCI hole */
493 if (mem_base <= RamSize && next_base > RamSize) {
494 mem_len -= next_base - RamSize;
496 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
500 mem_base = 1ULL << 32;
501 mem_len = next_base - RamSize;
502 next_base += (1ULL << 32) - RamSize;
504 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
508 for (; slots < nb_numa_nodes + 2; slots++) {
509 acpi_build_srat_memory(numamem, 0, 0, 0, 0);
513 build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1);
519 struct rsdp_descriptor *RsdpAddr;
521 #define MAX_ACPI_TABLES 20
528 dprintf(3, "init ACPI tables\n");
530 // This code is hardcoded for PIIX4 Power Management device.
531 int bdf = pci_find_device(PCI_VENDOR_ID_INTEL
532 , PCI_DEVICE_ID_INTEL_82371AB_3);
537 // Create initial rsdt table
538 struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
544 u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
546 #define ACPI_INIT_TABLE(X) \
548 tables[tbl_idx] = (u32)(X); \
549 if (tables[tbl_idx]) \
554 ACPI_INIT_TABLE(build_fadt(bdf));
555 ACPI_INIT_TABLE(build_ssdt());
556 ACPI_INIT_TABLE(build_madt());
557 ACPI_INIT_TABLE(build_hpet());
558 ACPI_INIT_TABLE(build_srat());
560 u16 i, external_tables = qemu_cfg_acpi_additional_tables();
562 for(i = 0; i < external_tables; i++) {
563 u16 len = qemu_cfg_next_acpi_table_len();
564 void *addr = malloc_high(len);
569 ACPI_INIT_TABLE(qemu_cfg_next_acpi_table_load(addr, len));
570 if (tbl_idx == MAX_ACPI_TABLES) {
576 struct rsdt_descriptor_rev1 *rsdt;
577 size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
578 rsdt = malloc_high(rsdt_len);
584 memset(rsdt, 0, rsdt_len);
585 memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
587 build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
589 // Build rsdp pointer table
590 memset(rsdp, 0, sizeof(*rsdp));
591 rsdp->signature = RSDP_SIGNATURE;
592 memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
593 rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
594 rsdp->checksum -= checksum(rsdp, 20);
596 dprintf(1, "ACPI tables: RSDP=%p RSDT=%p\n", rsdp, rsdt);
600 find_resume_vector(void)
602 dprintf(4, "rsdp=%p\n", RsdpAddr);
603 if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
605 struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
606 dprintf(4, "rsdt=%p\n", rsdt);
607 if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
609 void *end = (void*)rsdt + rsdt->length;
611 for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
612 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
613 if (!fadt || fadt->signature != FACP_SIGNATURE)
615 dprintf(4, "fadt=%p\n", fadt);
616 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
617 dprintf(4, "facs=%p\n", facs);
618 if (! facs || facs->signature != FACS_SIGNATURE)
621 dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
622 return facs->firmware_waking_vector;