-; 5.6 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ
-;=========================================================================================
-;
-#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ )
-;
-; Start restriction; Maximum frequency
- #if (DEVICE == MB91461R)
- #error: Frequency is not supported by this device.
- #endif
-; End restriction
-;
- #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
- #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
- #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz
- #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
- #set MUL_G 0x13 ; 0x48Fh: PLLMULG;
- ; Clock Divider
- #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz
- #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz
- #set EXTBUSCLOCK 0x02 ; 0x487h: DIV1R_T; => /3 ; 27 MHz
- ; CAN Clock
- #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz
- #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz
- #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
- ; Voltage Regulator
- #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
- #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
- ; Memory Controller
- #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
- #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
- #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
-#endif
-;
-;=========================================================================================
-; 5.7 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ
-;=========================================================================================
-;
-#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ )
-;
-; Start restriction; Maximum frequency
- #if (DEVICE == MB91461R)
- #error: Frequency is not supported by this device.
- #endif
-; End restriction
-;
- #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
- #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
- #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz
- #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
- #set MUL_G 0x13 ; 0x48Fh: PLLMULG;
- ; Clock Divider
- #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz
- #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz
- #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 40 MHz
- ; CAN Clock
- #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz
- #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz
- #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
- ; Voltage Regulator
- #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
- #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
- ; Memory Controller
- #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
- #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
- #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
-#endif
-;
-;=========================================================================================
-; 5.8 CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ
-;=========================================================================================
-;
-#if (CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ )
-;
-; Start restriction; Maximum frequency
- #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\
- (DEVICE == MB91461R) || (DEVICE == MB91467R)
- #error: Frequency is not supported by this device.
- #endif
-; End restriction
-;
- #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
- #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
- #set PLLSPEED 0x0117 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 96 MHz
- #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
- #set MUL_G 0x17 ; 0x48Fh: PLLMULG;
- ; Clock Divider
- #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
- #set PERCLOCK 0x05 ; 0x486h: DIV0R_P; => /6 ; 16 MHz
- #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
- ; CAN Clock
- #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 192 MHz
- #set PSDVC 0x0B ; 0x4C0h: CANPRE_DVC; => /12 ; 16 MHz
- #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
- ; Voltage Regulator
- #if (DEVICE == MB91469G)
- #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
- #else
- #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
- #endif
- #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
- ; Memory Controller
- #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
- #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
- #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
-#endif
-;
-;=========================================================================================
-; 5.9 CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ
-;=========================================================================================
-;
-#if (CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ )
-;
-; Start restriction; Maximum frequency
- #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\
- (DEVICE == MB91461R) || (DEVICE == MB91467R) || (DEVICE == MB91467D)
- #error: Frequency is not supported by this device.
- #endif
-; End restriction
-;
- #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
- #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
- #set PLLSPEED 0x0118 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 100 MHz
- #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
- #set MUL_G 0x17 ; 0x48Fh: PLLMULG;
- ; Clock Divider
- #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 100 MHz
- #set PERCLOCK 0x04 ; 0x486h: DIV0R_P; => /5 ; 20 MHz
- #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 50 MHz
- ; CAN Clock
- #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 200 MHz
- #set PSDVC 0x09 ; 0x4C0h: CANPRE_DVC; => /10 ; 20 MHz
- #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
- ; Voltage Regulator
- #if (DEVICE == MB91469G)
- #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
- #else
- #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
- #endif
- #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
- ; Memory Controller
- #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
- #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
- #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
-#endif
-;
-;=========================================================================================
-; 5.10 CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ
-;=========================================================================================
-;
-#if (CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )
-;
-; Start restriction; Maximum frequency
- #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\
- (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\
- (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X)
- #error: Frequency is not supported by this device.
- #endif
-; End restriction
-;
- #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
- #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
- #set PLLSPEED 0x0105 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz
- #set DIV_G 0x0B ; 0x48Eh: PLLDIVG;
- #set MUL_G 0x1F ; 0x48Fh: PLLMULG;
- ; Clock Divider
- #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz
- #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz
- #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz
- ; CAN Clock
- #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz
- #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz
- #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
- ; Voltage Regulator
- ; -
- ; Memory Controller
- ; -
-#endif
-;
-;=========================================================================================
-; 5.11 CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ
-;=========================================================================================
-;
-#if (CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )
-;
-; Start restriction; Maximum frequency
- #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\
- (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\
- (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X)
- #error: Frequency is not supported by this device.
- #endif
-; End restriction
-;
- #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
- #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
- #set PLLSPEED 0x0102 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz
- #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
- #set MUL_G 0x1F ; 0x48Fh: PLLMULG;
- ; Clock Divider
- #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz
- #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz
- #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz
- ; CAN Clock
- #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz
- #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz
- #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
- ; Voltage Regulator
- ; -
- ; Memory Controller
- ; -
-#endif
-;
-;=========================================================================================