4 ;=========================================================================================
5 ; 4.1 Controller Device
6 ;=========================================================================================
7 #set MB91464A 2 ; MB91460 series
9 #set MB91467B 10 ; MB91460 series
11 #set MB91467C 11 ; MB91460 series
13 #set MB91467D 4 ; MB91460 series
15 #set MB91469G 6 ; MB91460 series
17 #set MB91465K 3 ; MB91460 series
19 #set MB91463N 8 ; MB91460 series
21 #set MB91461R 1 ; MB91460 series
22 #set MB91467R 5 ; MB91460 series
24 #set MB91465X 9 ; MB91460 series
26 #set others 7 ; MB91460 series
29 #set DEVICE MB91465K ; <<< select device
31 #set BOOT_FLASH_SEC OFF ; <<< BOOT and Flash Security Vector
32 ;=========================================================================================
33 ; 4.3 Stack Type and Stack Size
34 ;=========================================================================================
36 #set USRSTACK 0 ; user stack: for main program
37 #set SYSSTACK 1 ; system stack: for main program and
40 #set STACKUSE SYSSTACK ; <<< set active stack
42 #set STACK_RESERVE ON ; <<< reserve stack area in
44 #set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack
45 #set STACK_USR_SIZE 0x2 ; <<< byte size of User stack
47 ; - If the active stack is set to SYSSTACK, it is used for main program and interrupts.
48 ; In this case, the user stack could be set to a dummy size. If the active stack is
49 ; set to user stack, it is used for the main program but the system stack is
50 ; automatically activated, if an interrupt is serviced. Both stack areas must have a
52 ; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module.
53 ; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the
54 ; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.
55 ; - Even if they are reverved in other modules, they are still initialised in this
58 ; Note: Several library functions require quite a big stack (due to ANSI).
59 ; Check the stack information files (*.stk) in the LIB\911 directory.
61 ;=========================================================================================
62 ; 4.4 Copy code from Flash to I-RAM
63 ;=========================================================================================
65 #set I_RAM ON ; <<< select if code in section IRAM
67 ; If this option is activated code located in the section IRAM is copied during startup
68 ; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.
70 ;=========================================================================================
71 ; 4.7 Clock Configuration
72 ;=========================================================================================
73 ;=========================================================================================
74 ; 4.7.1 Clock Selection
75 ;=========================================================================================
80 ; Sub-oscillation input: 32 kHz
81 #set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11
83 ; Oscillation input: 4 MHz
84 #set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23
86 ; MB91461R only: Oscillation input: 10 MHz
87 #set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41
89 ; MB91461R only: Oscillation input: 20 MHz
90 #set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51
97 #set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
98 ; ; <<< Select clock configuration
100 ;=========================================================================================
101 ; 4.7.2 Select Clock Modulator
102 ;=========================================================================================
104 #set CLOMO OFF ; <<< Enable /disable clock modulator
106 #set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR
108 ; Please refer to the data sheet of the device if you enable clock modulation. The
109 ; register CMPR dependant on the PLL-Clock.
111 ; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the
112 ; clock for the CAN is not influenced by the clock modulation. If the CLKCAN
113 ; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if
114 ; the clock modulator is enabled).
116 ; Note: If the clock modulator is enabled, the wait states of the internal flash wait
117 ; states must be adapted to maximum frequency. Please check the wait states
120 ; Note: This feature is not supported by every device, e.g. MB91461. Please check the
123 ;=========================================================================================
124 ; 4.8 External Bus Interface
126 ; The rest of the configuration is only applicable for devices with an external bus
129 ; If the device does not offer an external bus interface, the configuration can be
130 ; stoped at this point.
132 ;=========================================================================================
133 ; 5 Definition of Configurations
134 ;=========================================================================================
136 #set NOCLOCK 0 ; do not touch CKSCR register
137 #set MAINCLOCK 1 ; select main clock
138 ; ; MB91461R : 1/4 of oscillation input
139 ; ; Others: 1/2 of oscillation input
140 #set MAINPLLCLOCK 2 ; select main clock with PLL
141 #set SUBCLOCK 3 ; select subclock (if available)
143 #set PSCLOCK_CLKB 0x00 ; select core clock (initial)
144 #set PSCLOCK_PLL 0x10 ; select PLL output (x)
145 #set PSCLOCK_MAIN 0x30 ; select Main Oscillation
147 ;=========================================================================================
148 ; 5.1 CLOCKSPEED == CLOCK_USER <<<
149 ;=========================================================================================
150 ; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the
151 ; corresponding application note.
153 #if (CLOCKSPEED == CLOCK_USER )
154 #set CLOCKSOURCE MAINPLLCLOCK ; <<< Clocksource
155 #set ENABLE_SUBCLOCK OFF ; <<< Subclock: ON/OFF
156 #set PLLSPEED 0x010F ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
157 #set DIV_G 0x0F ; <<< 0x48Eh: PLLDIVG;
158 #set MUL_G 0x0F ; <<< 0x48Fh: PLLMULG;
160 #set CPUCLOCK 0x00 ; <<< 0x486h: DIV0R_B; => /1 ; 64 MHz
161 #set PERCLOCK 0x03 ; <<< 0x486h: DIV0R_P; => /4 ; 16 MHz
162 #set EXTBUSCLOCK 0x01 ; <<< 0x487h: DIV1R_T; => /2 ; 32 MHz
164 #set PSCLOCKSOURCE PSCLOCK_PLL ; <<< 0x4C0h: CANPRE; => PLLx;128 MHz
165 #set PSDVC 0x07 ; <<< 0x4C0h: CANPRE_DVC;=> /8 ; 16 MHz
166 #set CANCLOCK 0x00 ; <<< 0x4C1h: CANCKD;
168 #set REGULATORSEL 0x06 ; <<< 0x4CEh: REGSEL;
169 #set REGULATORCTRL 0x00 ; <<< 0x4CFh: REGCTR;
171 #set FLASHCONTROL 0x032 ; <<< 0x7002h: FCHCR;
172 #set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT;
173 #set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2;
176 ;=========================================================================================
177 ; 5.2 CLOCKSPEED == NO_CLOCK
178 ;=========================================================================================
180 #if (CLOCKSPEED == NO_CLOCK )
181 #set CLOCKSOURCE NOCLOCK
183 ;=========================================================================================
184 ; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
185 ;=========================================================================================
187 #if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )
189 ; Start restriction; Maximum frequency
190 #if (DEVICE == MB91461R)
191 #error: Frequency is not supported by this device.
195 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
196 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
197 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
198 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
199 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
201 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
202 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz
203 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
205 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz
206 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz
207 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
209 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
210 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
212 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
213 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
214 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
217 ;=========================================================================================
218 ; 6 Section and Data Declaration
219 ;=========================================================================================
224 ;=========================================================================================
225 ; 6.1 Define Stack Size
226 ;=========================================================================================
227 .SECTION SSTACK, STACK, ALIGN=4
228 #if STACK_RESERVE == ON
229 .EXPORT __systemstack, __systemstack_top
231 .RES.B STACK_SYS_SIZE
235 .SECTION USTACK, STACK, ALIGN=4
236 #if STACK_RESERVE == ON
237 .EXPORT __userstack, __userstack_top
239 .RES.B STACK_USR_SIZE
243 ;=========================================================================================
244 ; 6.2 Define Sections
245 ;=========================================================================================
246 .section DATA, data, align=4
247 .section INIT, data, align=4
248 .section IRAM, code, align=4
249 .section CONST, const, align=4
250 .section INTVECT, const, align=4
257 #if (BOOT_FLASH_SEC == OFF)
266 ;-----------------------------------------------------------------------------------------
267 ; MACRO Clear RC Watchdog
268 ;-----------------------------------------------------------------------------------------
269 #macro ClearRCwatchdog
270 LDI #0x4C7,R7 ; clear RC watchdog
273 ;-----------------------------------------------------------------------------------------
275 ;-----------------------------------------------------------------------------------------
276 #macro wait_loop loop_number
283 .section CODE, code, align=4
284 .section CODE_START, code, align=4
285 #pragma section CODE=IRAM,attr=CODE
288 ;=========================================================================================
290 ;=========================================================================================
291 __start: ; start point
295 ANDCCR #0xEF ; disable interrupts
296 STILM #31 ; set interrupt level to low prior
297 ClearRCwatchdog ; clear harware watchdog
299 ;=========================================================================================
300 ; 7.1 Initialise Stack Pointer and Table Base Register
301 ;=========================================================================================
302 #if STACKUSE == SYSSTACK
304 LDI #__userstack_top, SP ; initialize SP
306 LDI #__systemstack_top, SP ; initialize SP
309 #if STACKUSE == USRSTACK
311 LDI #__systemstack_top, SP ; initialize SP
313 LDI #__userstack_top, SP ; initialize SP
316 LDI #INTVECT, R0 ; set Table Base
320 #if (CLOCKSOURCE != NOCLOCK)
321 ;=========================================================================================
322 ; 7.2 Check for CSV reset and set CSV
323 ;=========================================================================================
324 ; Start restriction; No clock supervisor (CSV)
325 #if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N)
327 LDI:20 #0x04AD, R0 ; CSVCR
328 BORL #0x8, @R0 ; Enable Main Osc CSV
329 BTSTH #0x4, @R0 ; Check for Main Osc missing
330 BEQ NoMAINCSVreset ; Main osc available -> branch
332 BANDL #0x7, @R0 ; Disable Main Osc CSV
334 LDI #noClockStartup, R0 ; Main Clock missing -> no
335 JMP @R0 ; clock startup
340 BORL #0x4, @R0 ; Enable Sub Osc CSV
341 BTSTH #0x2, @R0 ; Check for Sub Osc missing
342 BEQ NoSUBCSVreset ; Sub osc available -> branch
344 BANDL #0xB, @R0 ; Disable Sub Osc SCSV
345 #if (CLOCKSOURCE == SUBCLOCK)
346 LDI #noClockStartup, R0 ; Sub Clock missing -> no
347 JMP @R0 ; clock startup
351 ;=========================================================================================
352 ; 7.3 Check Clock Condition
353 ;=========================================================================================
354 LDI #0x484, R0 ; Check for Default Values
359 ;=========================================================================================
360 ; 7.4 Restore Default Settings after Reset
361 ;=========================================================================================
362 ;=========================================================================================
363 ; 7.4.1 Disable Clock Modulator
364 ;=========================================================================================
365 LDI #0x04BB, R0 ; Clock Modulator Control Reg
366 BANDL #0xD, @R0 ; Disable Frequency modulation
368 BTSTL #8, @R0 ; Wait until Frequency modulation
369 BNE FMODwait ; is disabled
371 BANDL #0xE, @R0 ; Power down clock modulator
373 ;=========================================================================================
374 ; 7.4.2 Check if running on Sub Clock, change to Main Clock
375 ;=========================================================================================
376 LDI:20 #0x0484,R12 ; Check if running on sub clock
383 LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped
387 BANDL #0xE, @R12 ; Start Main Oscillation
389 LDI #0x4C8, R0 ; Main Stabilisation Wait Time
390 LDI #0x04, R1 ; 32.7 ms
394 mainStabTime: ; Wait for stabilisation time
395 ClearRCwatchdog ; clear harware watchdog
402 LDI:20 #0x0484, R12 ; disable sub clock as source
403 BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2)
406 ;=========================================================================================
407 ; 7.4.3 Disable Sub Clock
408 ;=========================================================================================
409 #if ENABLE_SUBCLOCK != ON
410 LDI #0x0484, R0 ; Clock source control reg CLKR
411 BANDL #0x7, @R0 ; Disable PLL
414 ;=========================================================================================
415 ; 7.4.4 Check if running on PLL, Gear Down PLL
416 ;=========================================================================================
417 LDI:20 #0x0484,R12 ; Check if running on PLL
424 LDI:20 #0x0490, R11 ; clear flags
428 STB R1, @R11 ; Set Flag for Simulator; no Effekt on
431 BANDL #0xC, @R12 ; disable PLL as clock source
432 ; Clock Source = 0x00 (Main/2)
434 LDI:20 #0x048E,R12 ; check if DivG != 0
441 ClearRCwatchdog ; clear harware watchdog
442 BTSTL #4, @R11 ; Gear Down
445 LDI #0x00,R1 ; Clear Flags
449 ;=========================================================================================
451 ;=========================================================================================
452 LDI #0x0484, R0 ; Clock source control reg CLKR
453 BANDL #0xB, @R0 ; Disable PLL
455 ;=========================================================================================
456 ; 7.4.6 Set to Main Clock
457 ;=========================================================================================
458 LDI:20 #0x0484,R12 ; Check if running on PLL
459 BANDL #0xC, @R12 ; disable PLL as clock source
460 ; Clock Source = 0x00 (Main/2)
463 ;=========================================================================================
464 ; 7.5 Set Memory Controller
465 ;=========================================================================================
466 ; Start restriction; No embedded flash
467 #if DEVICE != MB91461R
469 LDI #0x7002, R1 ; FLASH Controller Reg.
470 LDI #FLASHCONTROL, R2 ; Flash Controller Settings
471 STH R2, @R1 ; set register
472 LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg.
473 LDI #FLASHREADT, R2 ; wait settings
474 STH R2, @R1 ; set register
475 LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg.
476 LDI #FLASHMWT2, R2 ; wait settings
477 STB R2, @R1 ; set register
481 ;=========================================================================================
483 ;=========================================================================================
484 ;=========================================================================================
485 ; 7.6.1 Set Voltage Regulator Settings
486 ;=========================================================================================
487 ; Start restriction; No regulator settings
488 #if DEVICE != MB91461R
490 LDI #0x04CF, R0 ; REGCTR
491 LDI #REGULATORCTRL, R1
494 LDI #0x04CE, R0 ; REGSEL
495 LDI #REGULATORSEL, R1
499 ;=========================================================================================
500 ; 7.6.2 Power on Clock Modulator - Clock Modulator Part I
501 ;=========================================================================================
503 LDI #0x04BB, R0 ; Clock Modulator Control Reg
504 LDI #0x11, R1 ; Load value to Power on CM
505 ORB R1, @R0 ; Power on clock modulaor
508 ;=========================================================================================
509 ; 7.6.3 Set CLKR Register w/o Clock Mode
510 ;=========================================================================================
511 ; Set Clock source (Base Clock) for the three clock tree selections
512 ; This select Base clock is used to select afterwards the 3
513 ; Clocks for the diffenrent internal trees.
514 ; When PLL is used, first pll multiplication ratio is set and PLL is
515 ; enabled. After waiting the PLL stabilisation time via timebase
516 ; timer, PLL clock is selected as clock source.
517 LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N
521 LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG
525 LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG
529 ;=========================================================================================
531 ;=========================================================================================
532 #if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )
533 LDI #0x0484, R0 ; Clock source control reg CLKR
534 LDI #0x04, R1 ; Use PLL x1, enable PLL
535 ORB R1, @R0 ; store data to CLKR register
539 #if ENABLE_SUBCLOCK == ON
540 LDI #0x0484, R0 ; Clock source control reg CLKR
541 LDI #0x08, R1 ; enable subclock operation
542 ORB R1, @R0 ; store data to CLKR register
543 LDI #0x4CA, R0 ; Sub Clock oszilation
544 LDI #0x00, R1 ; stabilitsation time = 32 ms
549 ;=========================================================================================
550 ; 7.6.5 Wait for PLL oscillation stabilisation
551 ;=========================================================================================
552 #if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))
553 LDI #0x0482, R12 ; TimeBaseTimer TBCR
554 LDI #0x00, R1 ; set 1024 us @ 2 MHz
557 BANDH #7, @R12 ; clear interrupt flag
559 LDI #0x0483, R0 ; clearTimeBaseTimer CTBR
565 BANDH #7, @R12 ; clear interrupt flag
566 BORH #8, @R12 ; set interrupt flag for simulator
569 ClearRCwatchdog ; clear harware watchdog
574 ;=========================================================================================
576 ;=========================================================================================
577 ;=========================================================================================
578 ; 7.6.6.1 Set CPU and peripheral clock
579 ;=========================================================================================
580 ; CPU and peripheral clock are set in one register
581 LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB)
582 LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting
584 ;=========================================================================================
585 ; 7.6.6.2 Set External Bus interface clock
586 ;=========================================================================================
587 ; set External Bus clock
588 ; Be aware to do smooth clock setting, to avoid wrong clock setting
589 ; Take care, always write 0 to the lower 4 bits of DIVR1 register
590 LDI #0x0487, R2 ; Set DIVR1
591 LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting
594 ;=========================================================================================
595 ; 7.6.6.3 Set CAN clock prescaler
596 ;=========================================================================================
597 ; Set CAN Prescaler, only clock relevant parameter
598 LDI #0x04C0, R0 ; Set CAN ClockParameter Register
599 LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider
600 STB R1, @R0 ; Set Divider
602 LDI #0x04c1, R0 ; Set CAN Clock enable Register
603 LDI #CANCLOCK, R1 ; Load CANCLOCK
604 STB R1, @R0 ; set CANCLOCK
606 ;=========================================================================================
607 ; 7.6.6.4 Switch Main Clock Mode
608 ;=========================================================================================
609 #if CLOCKSOURCE == MAINCLOCK
611 ;=========================================================================================
612 ; 7.6.6.5 Switch Subclock Mode
613 ;=========================================================================================
614 #elif ( (CLOCKSOURCE == SUBCLOCK) )
615 #if ENABLE_SUBCLOCK == ON
618 ClearRCwatchdog ; clear harware watchdog
619 BTSTH #8, @R12 ; wait until sub clock stabilisation
620 BEQ subStabTime ; time is over
624 LDI #0x0484, R0 ; Clock source control reg CLKR
625 LDI #0x01, R1 ; load value to select main clock
626 ORB R1, @R0 ; enable main clock (1/2 external)
627 LDI #0x03, R1 ; load value to select subclock
628 ORB R1, @R0 ; enable subclock as clock source
630 #error: Wrong setting! The clock source is subclock, but the subclock is disabled.
633 ;=========================================================================================
634 ; 7.6.7 Switch to PLL Mode
635 ;=========================================================================================
636 #elif ( (CLOCKSOURCE == MAINPLLCLOCK) )
639 LDI #0x0490, R0 ; PLL Ctrl Register
641 STB R1, @R0 ; Clear Flag
643 STB R1, @R0 ; Set Flag for Simulator; no Effekt on
646 LDI #0x0484, R3 ; Clock source control reg CLKR
647 BORL #0x2, @R3 ; enable PLL as clock source
651 ClearRCwatchdog ; clear harware watchdog
652 LDUB @R0, R2 ; LOAD PLLCTR to R2
653 AND R1, R2 ; GRUP, counter reach 0
657 STB R1, @R0 ; Clear Gear-Up Flag
662 ;=========================================================================================
663 ; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II
664 ;=========================================================================================
665 #if CLOMO == ON ; Only applicable if Modulator is on
666 LDI #0x04B8, R0 ; Clock Modulation Parameter Reg
667 LDI #CMPR, R1 ; Load CMP value
668 STH R1, @R0 ; Store CMP value in CMPR
670 LDI #0x04BB, R0 ; Clock Modulator Control Reg
671 LDI #0x13, R1 ; Load value to FM on CM
678 ;=========================================================================================
679 ; 7.7 Set BusInterface
680 ;=========================================================================================
681 ; Start restriction; No ext. bus interface
682 #if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) && \
683 (DEVICE != MB91463N) && (DEVICE != MB91465X)
687 emu_sram_cs_mb91461r:
690 #endif ; #endif (excl. devices)
693 ;=========================================================================================
694 ; 7.8 Copy code from Flash to I-RAM
695 ;=========================================================================================
699 LDI #sizeof(IRAM), R13
711 ;=========================================================================================
713 ;=========================================================================================
714 ;=========================================================================================
716 ;=========================================================================================
718 ; According to ANSI, the DATA section must be cleared during start-up
720 LDI #sizeof DATA &~0x3, R1
729 LDI:8 #sizeof DATA & 0x3, R1
730 LDI #DATA + (sizeof DATA & ~0x3), R13
741 ;=========================================================================================
742 ; 7.11 Copy Init section from ROM to RAM
743 ;=========================================================================================
745 ; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area.
747 ; The Application must copy the Section (Init) into the RAM area.
750 LDI #sizeof(INIT), R2
776 ;=========================================================================================
777 ; 7.14 call main routine
778 ;=========================================================================================
779 ClearRCwatchdog ; clear harware watchdog
780 LDI:8 #0, r4 ; Set the 1st parameter for main to 0.
782 LDI:8 #0, r5 ; Set the 2nd parameter for main to 0.
783 ;=========================================================================================
784 ; 7.15 Return from main function
785 ;=========================================================================================