ohci0 finally goes in operational mode -- silly confusion with

{set,write}32 *shame*

diff --git a/exception.c b/exception.c
index 39a1654e6cfb6e77b1efbf6168b920670567aefd..4362569f21d06032e5762952e525759c98ac0b66 100644 (file)
--- a/exception.c
+++ b/exception.c
@@ -56,7 +56,6 @@ void exception_handler(int exception)
        }
 
        irq_restore(cookie);
        }
 
        irq_restore(cookie);

-       _CPU_ISR_Enable(); //wtf

 }
 
 void exception_init(void)
 }
 
 void exception_init(void)

diff --git a/irq.c b/irq.c
index 389ae75fc81358e79f6a5528c2e26799d573173b..fad24848b1ca26813e7e4c933ddd02b73679e366 100644 (file)
--- a/irq.c
+++ b/irq.c
@@ -157,5 +157,6 @@ u32 irq_kill() {
 
 void irq_restore(u32 cookie) {
        _CPU_ISR_Restore(cookie);
 
 void irq_restore(u32 cookie) {
        _CPU_ISR_Restore(cookie);

+       _CPU_ISR_Enable(); //wtf :/

 }
 
 }
 

diff --git a/ohci.c b/ohci.c
index 959e5a4dd15c5dfe286a6329a7a7eb00598453aa..26aae244b68606c1abcdf8536b5731d7d9189438 100644 (file)
--- a/ohci.c
+++ b/ohci.c
@@ -55,36 +55,6 @@ void ohci_init() {
        /* enable interrupts of both usb host controllers */
        set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 
        /* enable interrupts of both usb host controllers */
        set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 

-
-       
-          u32 temp = 0;
-          u32 hcctrl = read32(OHCI0_HC_CONTROL);
-          switch(hcctrl & OHCI_CTRL_HCFS) {
-                  case OHCI_USB_OPER:
-                          temp = 0;
-                          break;
-                  case OHCI_USB_SUSPEND:
-                  case OHCI_USB_RESUME:
-                          hcctrl &= OHCI_CTRL_RWC;
-                          hcctrl |= OHCI_USB_RESUME;
-                          temp = 10;
-                          break;
-                  case OHCI_USB_RESET:
-                          hcctrl &= OHCI_CTRL_RWC;
-                          hcctrl |= OHCI_USB_RESET;
-                          temp = 50;
-                          break;
-          }
-          write32(OHCI0_HC_CONTROL, hcctrl);
-          (void) read32(OHCI0_HC_CONTROL);
-          udelay(temp*1000);
-
-          memset(&hcca_oh0, 0, sizeof(struct ohci_hcca));
-
-
-       dbg_op_state();
-
-

        /* reset HC */
        write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 
        /* reset HC */
        write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 


@@ -102,7 +72,6 @@ void ohci_init() {
           now we're in the SUSPEND state ... must go OPERATIONAL
           within 2msec else HC enters RESUME */
 
           now we're in the SUSPEND state ... must go OPERATIONAL
           within 2msec else HC enters RESUME */
 

-

           u32 cookie = irq_kill();
 
        /* Tell the controller where the control and bulk lists are
           u32 cookie = irq_kill();
 
        /* Tell the controller where the control and bulk lists are


@@ -127,7 +96,7 @@ void ohci_init() {
        }
        
        /* start HC operations */
        }
        
        /* start HC operations */

-       write32(OHCI0_HC_CONTROL, (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_RWC) | OHCI_CONTROL_INIT | OHCI_USB_OPER);
+       write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);

 
        /* wake on ConnectStatusChange, matching external hubs */
        set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 
        /* wake on ConnectStatusChange, matching external hubs */
        set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);


@@ -136,7 +105,6 @@ void ohci_init() {
        write32(OHCI0_HC_INT_STATUS, ~0);
        write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 
        write32(OHCI0_HC_INT_STATUS, ~0);
        write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 

-

        irq_restore(cookie);
 
        dbg_op_state();
        irq_restore(cookie);
 
        dbg_op_state();